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Thu, 09 Oct 2025 01:45:50 -0700 (PDT) From: Liangbin Lian To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, quentin.schulz@cherry.de, kever.yang@rock-chips.com, naoki@radxa.com, honyuenkwun@gmail.com, inindev@gmail.com, ivan8215145640@gmail.com, neil.armstrong@linaro.org, mani@kernel.org, dsimic@manjaro.org, pbrobinson@gmail.com, alchark@gmail.com, didi.debian@cknow.org, jjm2473@gmail.com, jbx6244@gmail.com, andrew@lunn.ch Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley Subject: [PATCH v5 1/3] dt-bindings: vendor-prefixes: Document LinkEase Date: Thu, 9 Oct 2025 16:44:14 +0800 Message-ID: <20251009084416.45542-2-jjm2473@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251009084416.45542-1-jjm2473@gmail.com> References: <20251009084416.45542-1-jjm2473@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LinkEase is a company focusing on the research and development of network equipment and related software and hardware from Shenzhen. Add vendor prefix for it. Acked-by: Conor Dooley Signed-off-by: Liangbin Lian --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 9ec8947dfcad..db496416b250 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -873,6 +873,8 @@ patternProperties: description: Lincoln Technology Solutions "^lineartechnology,.*": description: Linear Technology + "^linkease,.*": + description: Shenzhen LinkEase Network Technology Co., Ltd. "^linksprite,.*": description: LinkSprite Technologies, Inc. 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Thu, 09 Oct 2025 01:45:56 -0700 (PDT) From: Liangbin Lian To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, quentin.schulz@cherry.de, kever.yang@rock-chips.com, naoki@radxa.com, honyuenkwun@gmail.com, inindev@gmail.com, ivan8215145640@gmail.com, neil.armstrong@linaro.org, mani@kernel.org, dsimic@manjaro.org, pbrobinson@gmail.com, alchark@gmail.com, didi.debian@cknow.org, jjm2473@gmail.com, jbx6244@gmail.com, andrew@lunn.ch Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley Subject: [PATCH v5 2/3] dt-bindings: arm: rockchip: Add LinkEase EasePi R1 Date: Thu, 9 Oct 2025 16:44:15 +0800 Message-ID: <20251009084416.45542-3-jjm2473@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251009084416.45542-1-jjm2473@gmail.com> References: <20251009084416.45542-1-jjm2473@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LinkEase EasePi R1 is a high-performance mini router based on RK3568. Acked-by: Conor Dooley Signed-off-by: Liangbin Lian --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 28db6bd6aa5b..ec2271cfb7e1 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -726,6 +726,11 @@ properties: - const: lckfb,tspi-rk3566 - const: rockchip,rk3566 =20 + - description: LinkEase EasePi R1 + items: + - const: linkease,easepi-r1 + - const: rockchip,rk3568 + - description: Luckfox Core3576 Module based boards items: - enum: --=20 2.51.0 From nobody Fri Dec 19 08:56:23 2025 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD1852D1913 for ; Thu, 9 Oct 2025 08:46:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 09 Oct 2025 01:46:01 -0700 (PDT) Received: from localhost.localdomain ([223.74.108.47]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-794e1bf7604sm2130924b3a.55.2025.10.09.01.45.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 09 Oct 2025 01:46:01 -0700 (PDT) From: Liangbin Lian To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, quentin.schulz@cherry.de, kever.yang@rock-chips.com, naoki@radxa.com, honyuenkwun@gmail.com, inindev@gmail.com, ivan8215145640@gmail.com, neil.armstrong@linaro.org, mani@kernel.org, dsimic@manjaro.org, pbrobinson@gmail.com, alchark@gmail.com, didi.debian@cknow.org, jjm2473@gmail.com, jbx6244@gmail.com, andrew@lunn.ch Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/3] arm64: dts: rockchip: add LinkEase EasePi R1 Date: Thu, 9 Oct 2025 16:44:16 +0800 Message-ID: <20251009084416.45542-4-jjm2473@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251009084416.45542-1-jjm2473@gmail.com> References: <20251009084416.45542-1-jjm2473@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LinkEase EasePi R1 [1] is a high-performance mini router. Specification: - Rockchip RK3568 - 2GB/4GB LPDDR4 RAM - 16GB on-board eMMC - 1x M.2 key for 2280 NVMe (PCIe 3.0) - 1x USB 3.0 Type-A - 1x USB 2.0 Type-C (for USB flashing) - 2x 1000 Base-T (native, RTL8211F) - 2x 2500 Base-T (PCIe, RTL8125B) - 1x HDMI 2.0 Output - 12v DC Jack - 1x Power key connected to PMIC - 2x LEDs (one static power supplied, one GPIO controlled) [1] https://doc.linkease.com/zh/guide/easepi-r1/hardware.html Signed-off-by: Liangbin Lian Reviewed-by: Andrew Lunn --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3568-easepi-r1.dts | 686 ++++++++++++++++++ 2 files changed, 687 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 099520962ffb..7646ffd7f309 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -127,6 +127,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-nanopi-r3s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-bigtreetech-cb2-manta.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3566-bigtreetech-pi2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-bpi-r2-pro.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-easepi-r1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-fastrhino-r66s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-fastrhino-r68s.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts b/arch/arm64= /boot/dts/rockchip/rk3568-easepi-r1.dts new file mode 100644 index 000000000000..d41a691dfd6c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts @@ -0,0 +1,686 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model =3D "LinkEase EasePi R1"; + compatible =3D "linkease,easepi-r1", "rockchip,rk3568"; + + aliases { + mmc0 =3D &sdmmc0; + mmc1 =3D &sdhci; + mmc2 =3D &sdmmc2; + + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + }; + + chosen: chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + adc-keys { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 0>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + + button-recovery { + label =3D "Recovery"; + linux,code =3D ; + press-threshold-microvolt =3D <1750>; + }; + }; + + dc_12v: regulator-dc-12v { + compatible =3D "regulator-fixed"; + regulator-name =3D "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&dc_12v>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&dc_12v>; + }; + + pcie30_avdd0v9: regulator-pcie30-avdd0v9 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + vin-supply =3D <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc3v3_sys>; + }; + + regulator-vdd0v95-25glan { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwr_25g_pin>; + enable-active-high; + gpio =3D <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + regulator-name =3D "vdd0v95_25glan"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <950000>; + regulator-boot-on; + regulator-always-on; + vin-supply =3D <&vcc3v3_sys>; + }; + + vcc3v3_nvme: regulator-vcc3v3-nvme { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_nvme"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + gpio =3D <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&dc_12v>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc3v3_nvme_en>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&rk809 1>; + clock-names =3D "ext_clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + post-power-on-delay-ms =3D <200>; + reset-gpios =3D <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + hdmi-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&status_led_pin>; + + status_led: led-status { + gpios =3D <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; + color =3D ; + function =3D LED_FUNCTION_STATUS; + label =3D "green:status"; + linux,default-trigger =3D "heartbeat"; + }; + }; + +}; + +&gmac0 { + phy-mode =3D "rgmii-id"; + clock_in_out =3D "input"; + + assigned-clocks =3D <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents =3D <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates =3D <0>, <125000000>; + phy-handle =3D <&rgmii_phy0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + status =3D "okay"; +}; + +&gmac1 { + phy-mode =3D "rgmii-id"; + clock_in_out =3D "input"; + + assigned-clocks =3D <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents =3D <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates =3D <0>, <125000000>; + phy-handle =3D <&rgmii_phy1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + status =3D "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + pinctrl-0 =3D <ð_phy0_reset_pin>; + pinctrl-names =3D "default"; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + pinctrl-0 =3D <ð_phy1_reset_pin>; + pinctrl-names =3D "default"; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + }; +}; + +&combphy0 { + status =3D "okay"; +}; + +&combphy1 { + status =3D "okay"; +}; + +&combphy2 { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +&gpu { + mali-supply =3D <&vdd_gpu>; + status =3D "okay"; +}; + +&hdmi { + avdd-0v9-supply =3D <&vdda0v9_image>; + avdd-1v8-supply =3D <&vcca1v8_image>; + status =3D "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + vdd_cpu: regulator@1c { + compatible =3D "tcs,tcs4525"; + reg =3D <0x1c>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + #clock-cells =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + system-power-controller; + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc3v3_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name =3D "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name =3D "vdd_gpu"; + regulator-always-on; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name =3D "vdd_npu"; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name =3D "vdda0v9_image"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name =3D "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name =3D "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name =3D "vccio_acodec"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name =3D "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name =3D "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name =3D "vcca1v8_image"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name =3D "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name =3D "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + }; +}; + +&i2s0_8ch { + status =3D "okay"; +}; + +/* ETH3 */ +&pcie2x1 { + reset-gpios =3D <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&pcie30phy { + data-lanes =3D <1 2>; + status =3D "okay"; +}; + +/* ETH2 */ +&pcie3x1 { + num-lanes =3D <1>; + reset-gpios =3D <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +/* M.2 Key for 2280 NVMe */ +&pcie3x2 { + num-lanes =3D <1>; + reset-gpios =3D <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_nvme>; + status =3D "okay"; +}; + +&pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins =3D <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + gmac1 { + eth_phy1_reset_pin: eth-phy1-reset-pin { + rockchip,pins =3D <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + status_led_pin: status-led-pin { + rockchip,pins =3D + <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie-nic { + pwr_25g_pin: pwr-25g-pin { + rockchip,pins =3D <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + nvme { + vcc3v3_nvme_en: vcc3v3-nvme-en { + rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; + +&pmu_io_domains { + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcc3v3_pmu>; + vccio1-supply =3D <&vccio_acodec>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcc_1v8>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_1v8>; + vccio7-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcca_1v8>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + max-frequency =3D <200000000>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status =3D "okay"; +}; + +/* Micro SD card slot is not populated */ +&sdmmc0 { + max-frequency =3D <150000000>; + no-sdio; + no-mmc; + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply =3D <&vcc3v3_sd>; + vqmmc-supply =3D <&vccio_sd>; + status =3D "disabled"; +}; + +/* Wifi module is not populated */ +&sdmmc2 { + max-frequency =3D <150000000>; + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq =3D <&sdio_pwrseq>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sys>; + vqmmc-supply =3D <&vcc_1v8>; + status =3D "disabled"; +}; + +&tsadc { + rockchip,hw-tshut-mode =3D <1>; + rockchip,hw-tshut-polarity =3D <0>; + status =3D "okay"; +}; + +&uart2 { + status =3D "okay"; +}; + +/* OTG Only USB2.0, Only device mode */ +&usb_host0_xhci { + phys =3D <&usb2phy0_otg>; + phy-names =3D "usb2-phy"; + extcon =3D <&usb2phy0>; + maximum-speed =3D "high-speed"; + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usb_host1_xhci { + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy0_host { + phy-supply =3D <&vcc5v0_sys>; + status =3D "okay"; +}; + +&usb2phy0_otg { + status =3D "okay"; +}; + +&vop { + assigned-clocks =3D <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents =3D <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi_in_vp0>; + }; +}; --=20 2.51.0