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Thu, 09 Oct 2025 07:11:46 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 5997BhrN002158; Thu, 9 Oct 2025 07:11:43 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 49jvnmbgy0-1; Thu, 09 Oct 2025 07:11:43 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 5997BgLn002134; Thu, 9 Oct 2025 07:11:42 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-riteshk-hyd.qualcomm.com [10.147.241.247]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 5997Bg9c002125; Thu, 09 Oct 2025 07:11:42 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2314801) id A5E0B5015BD; Thu, 9 Oct 2025 12:41:41 +0530 (+0530) From: Ritesh Kumar To: robin.clark@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jessica.zhang@oss.qualcomm.com, sean@poorly.run, marijn.suijten@somainline.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_mahap@quicinc.com, andersson@kernel.org, konradybcio@kernel.org, mani@kernel.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, vkoul@kernel.org, kishon@kernel.org, cros-qcom-dts-watchers@chromium.org Cc: Ritesh Kumar , linux-phy@lists.infradead.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, quic_vproddut@quicinc.com Subject: [PATCH 4/5] arm64: dts: qcom: Add edp reference clock for edp phy Date: Thu, 9 Oct 2025 12:41:26 +0530 Message-Id: <20251009071127.26026-5-quic_riteshk@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20251009071127.26026-1-quic_riteshk@quicinc.com> References: <20251009071127.26026-1-quic_riteshk@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=BMW+bVQG c=1 sm=1 tr=0 ts=68e76033 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=x6icFKpwvdMA:10 a=COk6AnOGAAAA:8 a=FSaGvECU0n0iTL-qRsYA:9 a=TjNXssC_j7lpFel5tvFf:22 a=nl4s5V0KI7Kw-pW0DWrs:22 a=pHzHmUro8NiASowvMSCR:22 a=xoEH_sTeL_Rfw54TyV31:22 X-Proofpoint-GUID: sLVfe5q2JoXHIfvIz1jePNEUbirAHlJ9 X-Proofpoint-ORIG-GUID: sLVfe5q2JoXHIfvIz1jePNEUbirAHlJ9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA4MDEyMSBTYWx0ZWRfX9A55SsHT+xp9 9fUMYvet+5ZI4TfYLFdZ88gOVr5RdSxtt7yCcZntDO9FBF5oVrZLgDzr590DTKVb7y6T2zMVU9o Uvf8SWT1jAssVAC7Vqzg3Vic6rf88MAFqLRDH+2UM1mri2Hp30p/akJ6GJnWZNJvbqeXX83hrDe tByDNRLngs3ZdR3NhXBoXdKZp7NaEtNpPUG0VZ0P8ULwHC+JU9Ads9x95uuvoz6EPBTAhVNHl9e 6i05EQFxUMR0KGYOorzk24/3nPiN1YKDQ3xO/tzoD0GpmW4Suot1yuFsrPGdENx8tU0ya9XvwCO 3CUjYStpIj2lt4ddpHbTdNZD0RX+v0+VN9bCUdA3SDrLzygneBNuN03tF/Sf25gj/YsMdgjJamN 97F+BM4cy7qo4sMWMZsc8iaCb3lNdw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-09_02,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 phishscore=0 clxscore=1011 impostorscore=0 malwarescore=0 priorityscore=1501 adultscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510080121 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add edp reference clock for edp phy on lemans, sc7280 and x1e80100 chipsets. Signed-off-by: Ritesh Kumar --- arch/arm64/boot/dts/qcom/lemans.dtsi | 12 ++++++++---- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++++-- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 12 ++++++++---- 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index cf685cb186ed..e8deb50f248b 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5034,9 +5034,11 @@ <0x0 0x0aec2000 0x0 0x1c8>; =20 clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "edp_ref"; =20 #clock-cells =3D <1>; #phy-cells =3D <0>; @@ -5053,9 +5055,11 @@ <0x0 0x0aec5000 0x0 0x1c8>; =20 clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "edp_ref"; =20 #clock-cells =3D <1>; #phy-cells =3D <0>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 4b04dea57ec8..1af79bddcf38 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -5222,10 +5222,12 @@ <0 0x0aec2600 0 0xa0>, <0 0x0aec2000 0 0x1c0>; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>, + clocks =3D <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_EDP_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "edp_ref"; =20 #clock-cells =3D <1>; #phy-cells =3D <0>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 51576d9c935d..c42c292267cc 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5817,9 +5817,11 @@ <0 0x0aec2000 0 0x1c8>; =20 clocks =3D <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>; + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "edp_ref"; =20 power-domains =3D <&rpmhpd RPMHPD_MX>; =20 @@ -5837,9 +5839,11 @@ <0 0x0aec5000 0 0x1c8>; =20 clocks =3D <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>; + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "edp_ref"; =20 power-domains =3D <&rpmhpd RPMHPD_MX>; =20 --=20 2.17.1