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charset="utf-8" Add edp reference clock for qcom,edp-phy which is required to be enabled before eDP PHY initialization. Signed-off-by: Ritesh Kumar --- Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Docu= mentation/devicetree/bindings/phy/qcom,edp-phy.yaml index eb97181cbb95..95e9210f4163 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -37,12 +37,13 @@ properties: - description: PLL register block =20 clocks: - maxItems: 2 + maxItems: 3 =20 clock-names: items: - const: aux - const: cfg_ahb + - const: edp_ref =20 "#clock-cells": const: 1 @@ -75,8 +76,8 @@ examples: <0x0aec2600 0xa0>, <0x0aec2000 0x19c>; =20 - clocks =3D <&dispcc 0>, <&dispcc 1>; - clock-names =3D "aux", "cfg_ahb"; + clocks =3D <&dispcc 0>, <&dispcc 1>, <&dispcc 2>; + clock-names =3D "aux", "cfg_ahb", "edp_ref"; =20 #clock-cells =3D <1>; #phy-cells =3D <0>; --=20 2.17.1 From nobody Fri Dec 19 08:58:01 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE5972C21F8; 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charset="utf-8" Update clock entry in edp phy example node of sa8775p and sc7280 to add edp referece clock. Signed-off-by: Ritesh Kumar --- .../devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml | 6 ++++-- .../devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mds= s.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.ya= ml index e2730a2f25cf..5c0fa95244d7 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -200,9 +200,11 @@ examples: <0x0aec2000 0x1c8>; =20 clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "edp_ref"; =20 #clock-cells =3D <1>; #phy-cells =3D <0>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml index b643d3adf669..02568b6e349e 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml @@ -357,10 +357,12 @@ examples: <0xaec2600 0xa0>, <0xaec2000 0x1c0>; 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charset="utf-8" Commit 77d2fa54a9457 ("scsi: ufs: qcom : Refactor phy_power_on/off calls") lead to edp reference clock to be turned off, leading to below phy poweron failure on lemans edp phy. phy phy-aec2a00.phy.10: phy poweron failed --> -110 edp reference clock is required to be enabled before edp PHY initialization. This change adds support for voting the clock from edp phy driver. Signed-off-by: Ritesh Kumar --- drivers/phy/qualcomm/phy-qcom-edp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index f1b51018683d..b544b5988fa6 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -103,7 +103,7 @@ struct qcom_edp { =20 struct phy_configure_opts_dp dp_opts; =20 - struct clk_bulk_data clks[2]; + struct clk_bulk_data clks[3]; struct regulator_bulk_data supplies[2]; =20 bool is_edp; @@ -1094,6 +1094,7 @@ static int qcom_edp_phy_probe(struct platform_device = *pdev) =20 edp->clks[0].id =3D "aux"; edp->clks[1].id =3D "cfg_ahb"; + edp->clks[2].id =3D "edp_ref"; ret =3D devm_clk_bulk_get(dev, ARRAY_SIZE(edp->clks), edp->clks); if (ret) return ret; --=20 2.17.1 From nobody Fri Dec 19 08:58:01 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 997D12C0F97; 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charset="utf-8" Add edp reference clock for edp phy on lemans, sc7280 and x1e80100 chipsets. Signed-off-by: Ritesh Kumar --- arch/arm64/boot/dts/qcom/lemans.dtsi | 12 ++++++++---- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++++-- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 12 ++++++++---- 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index cf685cb186ed..e8deb50f248b 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5034,9 +5034,11 @@ <0x0 0x0aec2000 0x0 0x1c8>; =20 clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "edp_ref"; =20 #clock-cells =3D <1>; #phy-cells =3D <0>; @@ -5053,9 +5055,11 @@ <0x0 0x0aec5000 0x0 0x1c8>; =20 clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "edp_ref"; =20 #clock-cells =3D <1>; #phy-cells =3D <0>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 4b04dea57ec8..1af79bddcf38 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -5222,10 +5222,12 @@ <0 0x0aec2600 0 0xa0>, <0 0x0aec2000 0 0x1c0>; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>, + clocks =3D <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_EDP_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "edp_ref"; =20 #clock-cells =3D <1>; #phy-cells =3D <0>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 51576d9c935d..c42c292267cc 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5817,9 +5817,11 @@ <0 0x0aec2000 0 0x1c8>; =20 clocks =3D <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>; + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "edp_ref"; =20 power-domains =3D <&rpmhpd RPMHPD_MX>; =20 @@ -5837,9 +5839,11 @@ <0 0x0aec5000 0 0x1c8>; =20 clocks =3D <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>; + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; clock-names =3D "aux", - "cfg_ahb"; + "cfg_ahb", + "edp_ref"; =20 power-domains =3D <&rpmhpd RPMHPD_MX>; =20 --=20 2.17.1 From nobody Fri Dec 19 08:58:01 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99754296BB7; Thu, 9 Oct 2025 07:12:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759993928; cv=none; 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charset="utf-8" Define edp reference clock as fixed clock and add it for edp phy on sc8180x and sc8280xp chipsets. Signed-off-by: Ritesh Kumar --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 11 ++++++-- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 36 +++++++++++++++++--------- 2 files changed, 33 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qc= om/sc8180x.dtsi index 85c2afcb417d..392cc9eede48 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -27,6 +27,12 @@ #size-cells =3D <2>; =20 clocks { + edp_ref_clk: edp-ref-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <19200000>; + }; + xo_board_clk: xo-board { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -3492,8 +3498,9 @@ <0 0x0aec2000 0 0x19c>; =20 clocks =3D <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>; - clock-names =3D "aux", "cfg_ahb"; + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&edp_ref_clk>; + clock-names =3D "aux", "cfg_ahb", "edp_ref"; =20 power-domains =3D <&rpmhpd SC8180X_MX>; =20 diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 279e5e6beae2..d0a976aea46d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -29,6 +29,12 @@ #size-cells =3D <2>; =20 clocks { + edp_ref_clk: edp-ref-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <19200000>; + }; + xo_board_clk: xo-board-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -3792,8 +3798,9 @@ <0 0x08909000 0 0x1c8>; =20 clocks =3D <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc1 DISP_CC_MDSS_AHB_CLK>; - clock-names =3D "aux", "cfg_ahb"; + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&edp_ref_clk>; + clock-names =3D "aux", "cfg_ahb", "edp_ref"; power-domains =3D <&rpmhpd SC8280XP_MX>; =20 #clock-cells =3D <1>; @@ -3810,8 +3817,9 @@ <0 0x0890c000 0 0x1c8>; =20 clocks =3D <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, - <&dispcc1 DISP_CC_MDSS_AHB_CLK>; - clock-names =3D "aux", "cfg_ahb"; + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&edp_ref_clk>; + clock-names =3D "aux", "cfg_ahb", "edp_ref"; power-domains =3D <&rpmhpd SC8280XP_MX>; =20 #clock-cells =3D <1>; @@ -5022,8 +5030,9 @@ <0 0x0aec2000 0 0x1c8>; =20 clocks =3D <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, - <&dispcc0 DISP_CC_MDSS_AHB_CLK>; - clock-names =3D "aux", "cfg_ahb"; + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&edp_ref_clk>; + clock-names =3D "aux", "cfg_ahb", "edp_ref"; power-domains =3D <&rpmhpd SC8280XP_MX>; =20 #clock-cells =3D <1>; @@ -5040,8 +5049,9 @@ <0 0x0aec5000 0 0x1c8>; =20 clocks =3D <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, - <&dispcc0 DISP_CC_MDSS_AHB_CLK>; - clock-names =3D "aux", "cfg_ahb"; + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&edp_ref_clk>; + clock-names =3D "aux", "cfg_ahb", "edp_ref"; power-domains =3D <&rpmhpd SC8280XP_MX>; =20 #clock-cells =3D <1>; @@ -6368,8 +6378,9 @@ <0 0x220c2000 0 0x1c8>; =20 clocks =3D <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, - <&dispcc1 DISP_CC_MDSS_AHB_CLK>; - clock-names =3D "aux", "cfg_ahb"; + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&edp_ref_clk>; + clock-names =3D "aux", "cfg_ahb", "edp_ref"; power-domains =3D <&rpmhpd SC8280XP_MX>; =20 #clock-cells =3D <1>; @@ -6386,8 +6397,9 @@ <0 0x220c5000 0 0x1c8>; =20 clocks =3D <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, - <&dispcc1 DISP_CC_MDSS_AHB_CLK>; - clock-names =3D "aux", "cfg_ahb"; + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&edp_ref_clk>; + clock-names =3D "aux", "cfg_ahb", "edp_ref"; power-domains =3D <&rpmhpd SC8280XP_MX>; =20 #clock-cells =3D <1>; --=20 2.17.1