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Wed, 08 Oct 2025 18:58:58 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Conor Dooley , Alexandre Ghiti , Emil Renner Berthing , Andrew Morton , Rob Herring , Krzysztof Kozlowski , Samuel Holland Subject: [PATCH v2 14/18] riscv: alternative: Allow calls with alternate link registers Date: Wed, 8 Oct 2025 18:57:50 -0700 Message-ID: <20251009015839.3460231-15-samuel.holland@sifive.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251009015839.3460231-1-samuel.holland@sifive.com> References: <20251009015839.3460231-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Alternative assembly code may wish to use an alternate link register to minimize the number of clobbered registers. Apply the offset fix to all jalr (not jr) instructions, i.e. where rd is not x0. Signed-off-by: Samuel Holland --- (no changes since v1) arch/riscv/kernel/alternative.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternativ= e.c index 7eb3cb1215c62..249ee55d05475 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -121,8 +121,8 @@ void riscv_alternative_fix_offsets(void *alt_ptr, unsig= ned int len, if (!riscv_insn_is_jalr(insn2)) continue; =20 - /* if instruction pair is a call, it will use the ra register */ - if (RV_EXTRACT_RD_REG(insn) !=3D 1) + /* if instruction pair is a call, it will save a link register */ + if (RV_EXTRACT_RD_REG(insn) =3D=3D 0) continue; =20 riscv_alternative_fix_auipc_jalr(alt_ptr + i * sizeof(u32), --=20 2.47.2