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Wed, 08 Oct 2025 18:58:55 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Conor Dooley , Alexandre Ghiti , Emil Renner Berthing , Andrew Morton , Rob Herring , Krzysztof Kozlowski , Samuel Holland Subject: [PATCH v2 12/18] riscv: mm: Expose all page table bits to assembly code Date: Wed, 8 Oct 2025 18:57:48 -0700 Message-ID: <20251009015839.3460231-13-samuel.holland@sifive.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251009015839.3460231-1-samuel.holland@sifive.com> References: <20251009015839.3460231-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pgtable-32.h and pgtable-64.h are not usable by assembly code files, so move all page table field definitions to pgtable-bits.h. This allows handling more complex PTE transformations in out-of-line assembly code. Signed-off-by: Samuel Holland --- (no changes since v1) arch/riscv/include/asm/pgtable-32.h | 11 ------- arch/riscv/include/asm/pgtable-64.h | 30 ------------------- arch/riscv/include/asm/pgtable-bits.h | 42 +++++++++++++++++++++++++-- 3 files changed, 40 insertions(+), 43 deletions(-) diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/p= gtable-32.h index 90ef35a7c1a52..eb556ab95732d 100644 --- a/arch/riscv/include/asm/pgtable-32.h +++ b/arch/riscv/include/asm/pgtable-32.h @@ -17,17 +17,6 @@ =20 #define MAX_POSSIBLE_PHYSMEM_BITS 34 =20 -/* - * rv32 PTE format: - * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 - * PFN reserved for SW D A G U X W R V - */ -#define _PAGE_PFN_MASK GENMASK(31, 10) - -#define _PAGE_NOCACHE 0 -#define _PAGE_IO 0 -#define _PAGE_MTMASK 0 - #define ALT_FIXUP_MT(_val) #define ALT_UNFIX_MT(_val) =20 diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/p= gtable-64.h index 5531752b608e4..60c2615e46724 100644 --- a/arch/riscv/include/asm/pgtable-64.h +++ b/arch/riscv/include/asm/pgtable-64.h @@ -68,20 +68,6 @@ typedef struct { #define __pmd(x) ((pmd_t) { (x) }) #define PTRS_PER_PMD (PAGE_SIZE / sizeof(pmd_t)) =20 -/* - * rv64 PTE format: - * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2= | 1 | 0 - * N MT RSV PFN reserved for SW D A G U X W= R V - */ -#define _PAGE_PFN_MASK GENMASK(53, 10) - -/* - * [63] Svnapot definitions: - * 0 Svnapot disabled - * 1 Svnapot enabled - */ -#define _PAGE_NAPOT_SHIFT 63 -#define _PAGE_NAPOT BIT(_PAGE_NAPOT_SHIFT) /* * Only 64KB (order 4) napot ptes supported. */ @@ -111,18 +97,6 @@ enum napot_cont_order { =20 #if defined(CONFIG_RISCV_ISA_SVPBMT) || defined(CONFIG_ERRATA_THEAD_MAE) =20 -/* - * [62:61] Svpbmt Memory Type definitions: - * - * 00 - PMA Normal Cacheable, No change to implied PMA memory type - * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory - * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory - * 11 - Rsvd Reserved for future standard use - */ -#define _PAGE_NOCACHE (1UL << 61) -#define _PAGE_IO (2UL << 61) -#define _PAGE_MTMASK (3UL << 61) - /* * ALT_FIXUP_MT * @@ -174,10 +148,6 @@ enum napot_cont_order { =20 #else =20 -#define _PAGE_NOCACHE 0 -#define _PAGE_IO 0 -#define _PAGE_MTMASK 0 - #define ALT_FIXUP_MT(_val) =20 #endif /* CONFIG_RISCV_ISA_SVPBMT || CONFIG_ERRATA_THEAD_MAE */ diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm= /pgtable-bits.h index 179bd4afece46..18c50cbd78bf5 100644 --- a/arch/riscv/include/asm/pgtable-bits.h +++ b/arch/riscv/include/asm/pgtable-bits.h @@ -6,6 +6,16 @@ #ifndef _ASM_RISCV_PGTABLE_BITS_H #define _ASM_RISCV_PGTABLE_BITS_H =20 +/* + * rv32 PTE format: + * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 + * PFN reserved for SW D A G U X W R V + * + * rv64 PTE format: + * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 = | 1 | 0 + * N MT RSV PFN reserved for SW D A G U X W = R V + */ + #define _PAGE_ACCESSED_OFFSET 6 =20 #define _PAGE_PRESENT (1 << 0) @@ -21,6 +31,36 @@ #define _PAGE_SPECIAL (1 << 8) /* RSW: 0x1 */ #define _PAGE_TABLE _PAGE_PRESENT =20 +#define _PAGE_PFN_SHIFT 10 +#ifdef CONFIG_64BIT +#define _PAGE_PFN_MASK GENMASK(53, 10) +#else +#define _PAGE_PFN_MASK GENMASK(31, 10) +#endif /* CONFIG_64BIT */ + +#if defined(CONFIG_RISCV_ISA_SVPBMT) || defined(CONFIG_ERRATA_THEAD_MAE) +/* + * [62:61] Svpbmt Memory Type definitions: + * + * 00 - PMA Normal Cacheable, No change to implied PMA memory type + * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory + * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory + * 11 - Rsvd Reserved for future standard use + */ +#define _PAGE_NOCACHE (UL(1) << 61) +#define _PAGE_IO (UL(2) << 61) +#define _PAGE_MTMASK (UL(3) << 61) +#else +#define _PAGE_NOCACHE 0 +#define _PAGE_IO 0 +#define _PAGE_MTMASK 0 +#endif /* CONFIG_RISCV_ISA_SVPBMT || CONFIG_ERRATA_THEAD_MAE */ + +#ifdef CONFIG_RISCV_ISA_SVNAPOT +#define _PAGE_NAPOT_SHIFT 63 +#define _PAGE_NAPOT BIT(_PAGE_NAPOT_SHIFT) +#endif /* CONFIG_RISCV_ISA_SVNAPOT */ + /* * _PAGE_PROT_NONE is set on not-present pages (and ignored by the hardwar= e) to * distinguish them from swapped out pages @@ -30,8 +70,6 @@ /* Used for swap PTEs only. */ #define _PAGE_SWP_EXCLUSIVE _PAGE_ACCESSED =20 -#define _PAGE_PFN_SHIFT 10 - /* * when all of R/W/X are zero, the PTE is a pointer to the next level * of the page table; otherwise, it is a leaf PTE. --=20 2.47.2