From nobody Fri Dec 19 08:58:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E50DB2DE6F7; Thu, 9 Oct 2025 10:54:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760007261; cv=none; b=XXQuvrTK/poLNgPocM1khlfiAi7/xKwAbyHcHTdF1WVADjRz4QXqvQqnGp+yMPso6DNNsg33kwEEWivU2+X8beoGieKeXZ0EIBmb832tEwX7Bez9Pso6vq4/f+JEG0NflMzShZ0theo8eS9rTxasLK0HpeVxA8v96Z3p4vAjhzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760007261; c=relaxed/simple; bh=WJGC3xsX+N06n8UEa1fPxLlGi8484pc+qISN079PghU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jeBktW1zOb0VkAwlBJMWEf96D3GXEPfFMAO76An2sPV0vTpKkW9dr52or11CxLituptuDFeLsAavv0Mo/ra61AMgIB6I/4pSW2xVWibGGFq21r6EHwBmrgz0X2RNoBnXuhv0+0JQhMCN54lattO6zkjpKPuA10BZ7TgCdIZCXRU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=N2PyAJ3/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="N2PyAJ3/" Received: by smtp.kernel.org (Postfix) with ESMTPS id 912EAC4CEF9; Thu, 9 Oct 2025 10:54:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760007260; bh=WJGC3xsX+N06n8UEa1fPxLlGi8484pc+qISN079PghU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=N2PyAJ3/JjTkmUQhAP2yeKClFUn50o5SsrRw5rgaLTl3tyy/L86hN/jHSSWzPG5OF YJSiInIFHsCEAlf+FdrYr+8cukCLzF14KAE95+qPgZ9LrkIelRhmMvOEY+I+nS73xl LFXgpGoLz2l4FgmDmBgS2h60M8/Z37bz37Uh9oTYDyl+PvNUzKyBdexp2fK8KOrdx4 6r9O46XBYo884SBZMmqLz+eCL8v1yBiNqrwtVaEaWjIfOEg0cO9OiPCR/fo/cRnQab G6/e2JHJOocTIF5lOeFQ5IsmRNssYKCBy61sVbhQHgbNb1hOzG5Fo0/CLKXddfvz8G JE3ai31qc6RQQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8078ACCD187; Thu, 9 Oct 2025 10:54:20 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Thu, 09 Oct 2025 12:54:17 +0200 Subject: [PATCH 1/5] dt-bindings: arm: fsl: Add GOcontroll Moduline IV/Mini Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251009-mini_iv-v1-1-f3889c492457@gocontroll.com> References: <20251009-mini_iv-v1-0-f3889c492457@gocontroll.com> In-Reply-To: <20251009-mini_iv-v1-0-f3889c492457@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760007259; l=1035; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=YdrnHfiDG3B0bwOljviUk0FaT/LUxjf/C85CSrfJE3s=; b=p6e/cI8s74gDArLUc9ZfZeMa2Z13mKMWv5y8MtX41NjmGh7J/JuTcLDgUI/X9PFKvIlKB8Y2n kvvhw9jZ+qDBkEt8tsFZ+NIOICP9simjsWcYWrIqM4lQEh2Ltvbc0Lx X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Document the compatible strings for the Moduline IV and Mini. Signed-off-by: Maud Spierings Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 00cdf490b0620..41eb19e3530da 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -963,6 +963,8 @@ properties: - fsl,imx8mm-evkb # i.MX8MM EVKB Board - gateworks,imx8mm-gw75xx-0x # i.MX8MM Gateworks Board - gateworks,imx8mm-gw7904 + - gocontroll,moduline-iv + - gocontroll,moduline-mini - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development = Kit - gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development = Kit - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development = Kit --=20 2.51.0 From nobody Fri Dec 19 08:58:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EFF92DECA0; Thu, 9 Oct 2025 10:54:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760007261; cv=none; b=BiPm4B+dcVs9gpAPFtatVxo0V8ng8mv15juf3pnJkGjBd1Vd3Nw2NJmFyDwC16FIL8wzVRttBhcupwKMODgh5fLx1Z7fRJi3IY6SpQjA7Oa2LDwUOWzHnjpZVKFDWSr17Zrz8a3LVA9dqqouUm6Wq2DGCrGAgppBZtV0Q8bcY5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760007261; c=relaxed/simple; bh=NuxJQ4PCNhlMAsAch1wEwPEUb1yF+bxyo517P+mfhjc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GObCfZtzgBXc7B946F2TlnFBIb54MkSqWv/pBc7hJnD+3mFP45gxVMTMk57mWEqxfOSnOaK/QueVzqYCkg09y39YHBt89a1vs7GgG+PKg3C1pdKJBZayKRQPGLDbppaSVf7+YhVJQnni7WqILK6RYKFDVbHvCEG5uopVzurgAQg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=p9uGDcb5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p9uGDcb5" Received: by smtp.kernel.org (Postfix) with ESMTPS id A702BC4CEFE; Thu, 9 Oct 2025 10:54:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760007260; bh=NuxJQ4PCNhlMAsAch1wEwPEUb1yF+bxyo517P+mfhjc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=p9uGDcb5fFeyDaWEd7eoSINvn4U5E7CulzIlD6MWBi4RmnGIKWRqdrBNjfdbNhoX0 TR97wcG4bTvoeTQMsyESA92ONF8PqMa+HnM1oJGHKMpTclcqp2Gb89jyf8wTFPMdFU zE5qIzzj1WiFktLfP47wo1Blo4SChwsFy1BEuXiZMRf4ISUZ6ptofGd3ILKWA6ywWo mTI8tMmYWCdiB1PJiTDeaChRjdzERe1mwzmN6dufW6hYUIIZbeSBz/eYkUaqJ+isDB EXumWGVl6iVSFnmLoN30GamLj92wgE8GJZWh0MCtx/eblE8I8vwdEgP3kTrOQhhdV8 FjXxXRpM+9GOQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97FE1CCD18A; Thu, 9 Oct 2025 10:54:20 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Thu, 09 Oct 2025 12:54:18 +0200 Subject: [PATCH 2/5] arm64: dts: imx8mm: Add pinctrl config definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251009-mini_iv-v1-2-f3889c492457@gocontroll.com> References: <20251009-mini_iv-v1-0-f3889c492457@gocontroll.com> In-Reply-To: <20251009-mini_iv-v1-0-f3889c492457@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760007259; l=1757; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=MAE7xeBSUg/gATbefV1ey2N4qXKmne123cPaX7vCeFU=; b=wQgTu+w0L9+UOad9IVAW/wdFGnCuejvrzxIZKqv17++B+1TagqnNdYzFlaOFMcnVPeiEuxxUQ 4U4xKPEhItlBQIvezmmmA/IGX6HZE1lusgTAlC/FH2zo7y+3fFae6vP X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Currently to configure each IOMUXC_SW_PAD_CTL_PAD the raw value of this register is written in the dts, these values are not obvious. Add defines which describe the fields of this register which can be or-ed together to produce readable settings. Signed-off-by: Maud Spierings --- arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h | 33 ++++++++++++++++++++++= ++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/bo= ot/dts/freescale/imx8mm-pinfunc.h index b1f11098d248e..31557b7b9ccc1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h @@ -6,6 +6,39 @@ #ifndef __DTS_IMX8MM_PINFUNC_H #define __DTS_IMX8MM_PINFUNC_H =20 +/* Drive Strength */ +#define MX8MM_DSE_X1 0x0 +#define MX8MM_DSE_X2 0x4 +#define MX8MM_DSE_X4 0x2 +#define MX8MM_DSE_X6 0x6 + +/* Slew Rate */ +#define MX8MM_FSEL_FAST 0x10 +#define MX8MM_FSEL_SLOW 0x0 + +/* Open Drain */ +#define MX8MM_ODE_ENABLE 0x20 +#define MX8MM_ODE_DISABLE 0x0 + +#define MX8MM_PULL_DOWN 0x0 +#define MX8MM_PULL_UP 0x40 + +/* Hysteresis */ +#define MX8MM_HYS_CMOS 0x0 +#define MX8MM_HYS_SCHMITT 0x80 + +#define MX8MM_PULL_ENABLE 0x100 +#define MX8MM_PULL_DISABLE 0x0 + +/* SION force input mode */ +#define MX8MM_SION 0x40000000 + +/* long defaults */ +#define MX8MM_USDHC_DATA_DEFAULT (MX8MM_FSEL_FAST | MX8MM_PULL_UP | \ + MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) +#define MX8MM_I2C_DEFAULT (MX8MM_DSE_X6 | MX8MM_PULL_UP | MX8MM_HYS_SCHMIT= T | \ + MX8MM_PULL_ENABLE | MX8MM_SION) + /* * The pin function ID is a tuple of * --=20 2.51.0 From nobody Fri Dec 19 08:58:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBF2E2DE6FC; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="j7+1aLcN" Received: by smtp.kernel.org (Postfix) with ESMTPS id B5382C116D0; Thu, 9 Oct 2025 10:54:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760007260; bh=9MM/UZ4L2wsqN4A7R9/XNM5qY3KWuRiCCtPnwmfK+1Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=j7+1aLcNi8UgysyEbZoltZ4DV5b33RslRruhr16OaQIe1CqcABQRChuEiDSA0dseR dW84F/iISufuhLyALkt3PhlWG9McuXzYdZUDCZnqqiYLMPdHuBeIk8OPqMw2lyENNU RgD5oJ5/thCgZulcG5WAjKhiHzNpokWrynAn7JfBR580CR3sSZR1ezMd7nFLjKv1fi MCb8XjHA3MciWwFuAZ4R9pa/7mmILNF6mA7NDpAg6msuN/RRdi2zlP4t2EuhlvzU8k NVzV8l5coqEKWhNIWiNbKa/Yl77A52ji6GYhW9Swi2gPh/wV94Atjsr4Elk7fL22Kh zCaCHR6Bz4GRQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9332CCD18C; Thu, 9 Oct 2025 10:54:20 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Thu, 09 Oct 2025 12:54:19 +0200 Subject: [PATCH 3/5] arm64: dts: freescale: add Ka-Ro Electronics tx8m-1610 COM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251009-mini_iv-v1-3-f3889c492457@gocontroll.com> References: <20251009-mini_iv-v1-0-f3889c492457@gocontroll.com> In-Reply-To: <20251009-mini_iv-v1-0-f3889c492457@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760007259; l=14868; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=CKLOQaO6unaE+E83cje9uohVXRu3Eil4/Ut+dV8Brcg=; b=dysHhe9AomvYhCagprW+9Rq2zmox5WR0oNewEuZSPyyRS3gUWp7mXACPQb/wG9LNQhQoRPJPx EXZSUlyKqIjASOGj2dA53zRVWYxWXpQFu6gd2uYLHoKOGWpjn0VEp8N X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings The Ka-Ro Electronics tx8m-1610 is a COM based on the imx8mm SOC. It has 1 GB of ram and 4 GB of eMMC storage on board. Add it to enable boards based on this module Signed-off-by: Maud Spierings --- .../arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi | 562 +++++++++++++++++= ++++ 1 file changed, 562 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi b/arch/arm= 64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi new file mode 100644 index 0000000000000..6ed86b10c4310 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi @@ -0,0 +1,562 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 Lothar Wa=C3=9Fmann + * 2025 Maud Spierings + */ + +#include "imx8mm.dtsi" + +/ { + reg_3v3_etn: regulator-3v3-etn { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio1 23 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_reg_3v3_etn>; + pinctrl-names =3D "default"; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "3v3-etn"; + vin-supply =3D <®_vdd_3v3>; + }; +}; + +&A53_0 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply =3D <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 =3D <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + }; + }; +}; + +&fec1 { + assigned-clocks =3D <&clk IMX8MM_CLK_ENET_AXI>, + <&clk IMX8MM_CLK_ENET_TIMER>, + <&clk IMX8MM_CLK_ENET_REF>, + <&clk IMX8MM_CLK_ENET_REF>; + assigned-clock-parents =3D <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_50M>; + assigned-clock-rates =3D <0>, <100000000>, <50000000>, <50000000>; + clocks =3D <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET_TIMER>, + <&clk IMX8MM_CLK_ENET_REF>; + phy-handle =3D <ðphy0>; + phy-mode =3D "rmii"; + phy-supply =3D <®_3v3_etn>; + pinctrl-0 =3D <&pinctrl_fec1>; + pinctrl-names =3D "default"; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-0 =3D <&pinctrl_ethphy_rst>; + pinctrl-names =3D "default"; + reset-delay-us =3D <25000>; + reset-gpios =3D <&gpio1 29 GPIO_ACTIVE_LOW>; + reset-post-delay-us =3D <100>; + + ethphy0: ethernet-phy@0 { + reg =3D <0>; + clocks =3D <&clk IMX8MM_CLK_ENET_REF>; + smsc,disable-energy-detect; + }; + }; +}; + +&gpio1 { + gpio-line-names =3D "SODIMM_152", + "SODIMM_42", + "SODIMM_153", + "PMIC_IRQ_B", + "SODIMM_154", + "SODIMM_155", + "SODIMM_156", + "SODIMM_157", + "SODIMM_158", + "SODIMM_159", + "SODIMM_161", + "SODIMM_162", + "SODIMM_34", + "SODIMM_36", + "SODIMM_27", + "SODIMM_28", + "", + "", + "", + "", + "", + "", + "", + "ENET_POWER", + "", + "", + "", + "", + "ENET_nINT", + "ENET_nRST", + "", + ""; +}; + +&gpio2 { + gpio-line-names =3D "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_51", + "SODIMM_57", + "SODIMM_56", + "SODIMM_52", + "SODIMM_53", + "SODIMM_54", + "SODIMM_55", + "SODIMM_15", + "SODIMM_45", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +&gpio3 { + gpio-line-names =3D "SODIMM_103", + "SODIMM_104", + "SODIMM_105", + "SODIMM_106", + "SODIMM_107", + "SODIMM_112", + "SODIMM_108", + "SODIMM_109", + "SODIMM_95", + "SODIMM_110", + "SODIMM_96", + "SODIMM_97", + "SODIMM_98", + "SODIMM_99", + "SODIMM_113", + "SODIMM_114", + "SODIMM_115", + "SODIMM_101", + "SODIMM_100", + "SODIMM_77", + "SODIMM_72", + "SODIMM_73", + "SODIMM_74", + "SODIMM_75", + "SODIMM_76", + "SODIMM_43", + "", + "", + "", + "", + "", + ""; +}; + +&gpio4 { + gpio-line-names =3D "SODIMM_178", + "SODIMM_180", + "SODIMM_184", + "SODIMM_185", + "SODIMM_186", + "SODIMM_187", + "SODIMM_188", + "SODIMM_189", + "SODIMM_190", + "SODIMM_191", + "SODIMM_179", + "SODIMM_181", + "SODIMM_192", + "SODIMM_193", + "SODIMM_194", + "SODIMM_195", + "SODIMM_196", + "SODIMM_197", + "SODIMM_198", + "SODIMM_199", + "SODIMM_182", + "SODIMM_79", + "SODIMM_78", + "SODIMM_84", + "SODIMM_87", + "SODIMM_86", + "SODIMM_85", + "SODIMM_83", + "SODIMM_81", + "SODIMM_80", + "SODIMM_90", + "SODIMM_93"; +}; + +&gpio5 { + gpio-line-names =3D "SODIMM_92", + "SODIMM_91", + "SODIMM_89", + "SODIMM_144", + "SODIMM_143", + "SODIMM_146", + "SODIMM_68", + "SODIMM_67", + "SODIMM_70", + "SODIMM_69", + "SODIMM_48", + "SODIMM_46", + "SODIMM_47", + "SODIMM_44", + "PMIC_SCL", + "PMIC_SDA", + "SODIMM_41", + "SODIMM_40", + "SODIMM_148", + "SODIMM_149", + "SODIMM_150", + "SODIMM_151", + "SODIMM_60", + "SODIMM_59", + "SODIMM_64", + "SODIMM_63", + "SODIMM_62", + "SODIMM_61", + "SODIMM_66", + "SODIMM_65", + "", + ""; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_i2c1>; + pinctrl-1 =3D <&pinctrl_i2c1_gpio>; + pinctrl-names =3D "default", "gpio"; + scl-gpios =3D <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + pmic: pmic@4b { + compatible =3D "rohm,bd71847"; + reg =3D <0x4b>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&pinctrl_pmic>; + pinctrl-names =3D "default"; + rohm,reset-snvs-powered; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <900000>; + regulator-min-microvolt =3D <780000>; + regulator-name =3D "buck1"; + regulator-ramp-delay =3D <1250>; + }; + + reg_vdd_arm: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <950000>; + regulator-min-microvolt =3D <805000>; + regulator-name =3D "buck2"; + regulator-ramp-delay =3D <1250>; + rohm,dvs-run-voltage =3D <950000>; + rohm,dvs-idle-voltage =3D <810000>; + }; + + reg_vdd_dram: BUCK3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <900000>; + regulator-min-microvolt =3D <805000>; + regulator-name =3D "buck3"; + }; + + reg_vdd_3v3: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "buck4"; + }; + + reg_vdd_1v8: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1950000>; + regulator-min-microvolt =3D <1700000>; + regulator-name =3D "buck5"; + }; + + BUCK6 { + regulator-always-on; + regulator-boot-on; + /* + * The default output voltage is 1.1V, bumped + * to 1.35V in HW by a 499R/2.2K voltage divider in the + * feedback path. + */ + regulator-max-microvolt =3D <1100000>; + regulator-min-microvolt =3D <1100000>; + regulator-name =3D "buck6"; + }; + + reg_snvs_1v8: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1980000>; + regulator-min-microvolt =3D <1620000>; + regulator-name =3D "ldo1"; + }; + + reg_snvs_0v8: LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <900000>; + regulator-min-microvolt =3D <760000>; + regulator-name =3D "ldo2"; + }; + + reg_vdda_1v8: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1890000>; + regulator-min-microvolt =3D <1710000>; + regulator-name =3D "ldo3"; + }; + + reg_vdd_phy_0v9: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1000000>; + regulator-min-microvolt =3D <855000>; + regulator-name =3D "ldo4"; + }; + + ldo5_reg: LDO5 { + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "ldo5"; + }; + + reg_vdd_phy_1v2: LDO6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1260000>; + regulator-min-microvolt =3D <1140000>; + regulator-name =3D "ldo6"; + }; + }; + }; +}; + +&iomuxc { + pinctrl_ethphy_int: etnphy-intgrp { + fsl,pins =3D < + MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_ethphy_rst: etnphy-rstgrp { + fsl,pins =3D < + MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins =3D < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK + (MX8MM_FSEL_FAST | MX8MM_SION) + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER + MX8MM_FSEL_FAST + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL + MX8MM_FSEL_FAST + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 + (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_reg_3v3_etn: reg-3v3-etngrp { + fsl,pins =3D < + MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABL= E) + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABL= E) + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABL= E) + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABL= E) + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; +}; + +&usdhc1 { + assigned-clocks =3D <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates =3D <400000000>; + bus-width =3D <8>; + non-removable; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + vmmc-supply =3D <®_vdd_3v3>; + vqmmc-supply =3D <®_vdd_1v8>; + status =3D "okay"; +}; --=20 2.51.0 From nobody Fri Dec 19 08:58:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 515872E03EC; Thu, 9 Oct 2025 10:54:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760007262; cv=none; b=inXhZe1hS0Tm0Pft/P+loXG82AUKeIgJsmdb+/H6bM/pNeT7kWHFK6fcTQG377SYZ0Fb70kxNWDZWZF3alWVEuz3NBbGdbJOZiB7948yecDN75K0hCXK+EPEITanddOPzpa7TbxpapS/2G4vIHuyVBmM8hAFGFVQhJkz2L0W5eQ= ARC-Message-Signature: i=1; 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b=DApKCTftLYX4nqcEhKW71T5GCMC/QDMa54Lp1svvdLhr1VQHOVcKboFBmu50JwHx7 Ta9G1BZr5+O3egrenFyCqBZ77MVRoTV+Czyyt1b69kS7Fs8UJAR58mDXt4HYVx5Mev q6fQ2S7kHh3CUTfenDMocKw7oE/3YNCk0M9LOa4YUeAF8Y5vos9qTRJ2zg0FqrKjGH l8j/fYmb7yHB66YE80tLFU/QtlZkimVUvBZjOEHd/8yrTLB+r7mzE2L8sAZHUXXqCo pT9y/ZVuTztXOD0bpeccLW2EhJO+CLgli9gN/nSLqrfcdB4QrZ5wTEnjvuW2vBTfPZ kKtEmrJ8jGy/g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C13E1CCD18D; Thu, 9 Oct 2025 10:54:20 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Thu, 09 Oct 2025 12:54:20 +0200 Subject: [PATCH 4/5] arm64: dts: freescale: Add the GOcontroll Moduline IV Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251009-mini_iv-v1-4-f3889c492457@gocontroll.com> References: <20251009-mini_iv-v1-0-f3889c492457@gocontroll.com> In-Reply-To: <20251009-mini_iv-v1-0-f3889c492457@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760007259; l=21257; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=0yXzKEUYfT4keMFDN+Hrwke4qT9WvutaureIG0Gfc/U=; b=oFCQpwrU9szlsPKGpH9vG8lSbG3RP+on2YMpq9qzCr8bMwrxuTsOAsiLWDQhh/Q+qoORHpUM7 PZZFtNlWIgiDKNru2Sgg2u167JSWmD35UcFuO+ASBgGI5teGjr4gBtZ X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings The Moduline IV is a part of the wider GOcontroll Moduline ecosystem. These are embedded controllers that focus on modularity with their swappable IO modules. Features: - up to 8 Moduline IO modules - 4 CAN busses - 1 LIN bus - 1 Ethernet - 4 RGB leds - optional Wi-Fi/Bluetooth - optional 4G/GPS Signed-off-by: Maud Spierings --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx8mm-tx8m-1610-moduline-iv-306-d.dts | 801 +++++++++++++++++= ++++ 2 files changed, 803 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 525ef180481d3..b2fef44e0a370 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -124,6 +124,8 @@ imx8mm-evk-pcie-ep-dtbs +=3D imx8mm-evk.dtb imx-pcie0-e= p.dtbo imx8mm-evkb-pcie-ep-dtbs +=3D imx8mm-evkb.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-evk-pcie-ep.dtb imx8mm-evkb-pcie-ep.dtb =20 +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-tx8m-1610-moduline-iv-306-d.dtb + dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-iot-gateway.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306= -d.dts b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306-d.d= ts new file mode 100644 index 0000000000000..52a8caf4e078e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306-d.dts @@ -0,0 +1,801 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Maud Spierings + */ + +/dts-v1/; + +#include "imx8mm-tx8m-1610.dtsi" +#include + +/ { + chassis-type =3D "embedded"; + compatible =3D "gocontroll,moduline-iv", "fsl,imx8mm"; + hardware =3D "Moduline IV V3.06-D"; + model =3D "GOcontroll Moduline IV"; + + aliases { + usb-host =3D &usbotg2; + usbotg =3D &usbotg1; + spi0 =3D &ecspi2; /* spidev number compatibility */ + spi1 =3D &ecspi3; /* spidev number compatibility */ + spi2 =3D &ecspi1; /* spidev number compatibility */ + }; + + chosen { + stdout-path =3D "serial2:115200n8"; + }; + + mcp_clock: mcp-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <20000000>; + }; + + reg_3v3_m2: regulator-3v3-m2 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio4 8 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_reg_m2>; + pinctrl-names =3D "default"; + power-supply =3D <®_6v4>; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "3v3-m.2"; + }; + + reg_5v0: regulator-5v0 { + compatible =3D "regulator-fixed"; + power-supply =3D <®_6v4>; + regulator-always-on; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "5v0"; + }; + + reg_6v4: regulator-6v4 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt =3D <6400000>; + regulator-min-microvolt =3D <6400000>; + regulator-name =3D "6v4"; + }; + + reg_can1_stby: regulator-can1-stby { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio3 16 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&pinctrl_can1_reg>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "can1-stby"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio3 17 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&pinctrl_can2_reg>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "can2-stby"; + }; + + reg_can3_stby: regulator-can3-stby { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio1 11 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&pinctrl_can3_reg>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "can3-stby"; + }; + + reg_can4_stby: regulator-can4-stby { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio3 8 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&pinctrl_can4_reg>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "can4-stby"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + pinctrl-0 =3D <&pinctrl_wl_reg>; + pinctrl-names =3D "default"; + post-power-on-delay-ms =3D <100>; + power-off-delay-us =3D <500000>; + reset-gpios =3D <&gpio3 3 GPIO_ACTIVE_LOW>; + }; +}; + +/* SPI 2 */ +&ecspi1 { + pinctrl-0 =3D <&pinctrl_ecspi1>; + pinctrl-names =3D "default"; + cs-gpios =3D < + &gpio1 9 GPIO_ACTIVE_LOW + &gpio1 0 GPIO_ACTIVE_LOW + &gpio5 2 GPIO_ACTIVE_LOW + &gpio4 27 GPIO_ACTIVE_LOW + &gpio3 1 GPIO_ACTIVE_LOW + >; + status =3D "okay"; + + connector@0 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <0>; + i2c-bus =3D <&i2c2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio1 5 GPIO_ACTIVE_LOW>; + slot-number =3D <3>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_vdd_3v3>; + }; + + connector@1 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <1>; + i2c-bus =3D <&i2c2>; + interrupt-parent =3D <&gpio5>; + interrupts =3D <21 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio3 15 GPIO_ACTIVE_LOW>; + slot-number =3D <4>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_vdd_3v3>; + }; + + connector@2 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <2>; + i2c-bus =3D <&i2c2>; + interrupt-parent =3D <&gpio5>; + interrupts =3D <1 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio4 25 GPIO_ACTIVE_LOW>; + slot-number =3D <5>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_vdd_3v3>; + }; + + connector@3 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <3>; + i2c-bus =3D <&i2c2>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio4 28 GPIO_ACTIVE_LOW>; + slot-number =3D <6>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_vdd_3v3>; + }; + + adc@4 { + compatible =3D "microchip,mcp3004"; + reg =3D <4>; + spi-max-frequency =3D <2300000>; + vref-supply =3D <®_vdd_3v3>; + }; +}; + +&ecspi2 { + pinctrl-0 =3D <&pinctrl_ecspi2>; + pinctrl-names =3D "default"; + cs-gpios =3D < + &gpio3 23 GPIO_ACTIVE_LOW + &gpio5 9 GPIO_ACTIVE_LOW + &gpio3 2 GPIO_ACTIVE_LOW + &gpio5 25 GPIO_ACTIVE_LOW + >; + status =3D "okay"; + + connector@0 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <0>; + i2c-bus =3D <&i2c2>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <19 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio3 24 GPIO_ACTIVE_LOW>; + slot-number =3D <7>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_vdd_3v3>; + }; + + connector@1 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <1>; + i2c-bus =3D <&i2c2>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <22 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio3 21 GPIO_ACTIVE_LOW>; + slot-number =3D <8>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_vdd_3v3>; + }; + + can@2 { // reg vdd? + compatible =3D "microchip,mcp25625"; + reg =3D <2>; + clocks =3D <&mcp_clock>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&pinctrl_can1>; + pinctrl-names =3D "default"; + spi-max-frequency =3D <10000000>; + xceiver-supply =3D <®_can1_stby>; + }; + + can@3 { + compatible =3D "microchip,mcp25625"; + reg =3D <3>; + clocks =3D <&mcp_clock>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&pinctrl_can2>; + pinctrl-names =3D "default"; + spi-max-frequency =3D <10000000>; + xceiver-supply =3D <®_can2_stby>; + }; +}; + +&ecspi3 { + pinctrl-0 =3D <&pinctrl_ecspi3>; + pinctrl-names =3D "default"; + cs-gpios =3D < + &gpio1 4 GPIO_ACTIVE_LOW + &gpio1 10 GPIO_ACTIVE_LOW + &gpio5 5 GPIO_ACTIVE_LOW + &gpio5 4 GPIO_ACTIVE_LOW + >; + status =3D "okay"; + + connector@0 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <0>; + i2c-bus =3D <&i2c2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <6 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio1 8 GPIO_ACTIVE_LOW>; + slot-number =3D <1>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_vdd_3v3>; + }; + + connector@1 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <1>; + i2c-bus =3D <&i2c2>; + interrupt-parent =3D <&gpio5>; + interrupts =3D <20 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio3 11 GPIO_ACTIVE_LOW>; + slot-number =3D <2>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_vdd_3v3>; + }; + + can@2 { + compatible =3D "microchip,mcp25625"; + reg =3D <2>; + clocks =3D <&mcp_clock>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&pinctrl_can3>; + pinctrl-names =3D "default"; + spi-max-frequency =3D <10000000>; + xceiver-supply =3D <®_can3_stby>; + }; + + can@3 { + compatible =3D "microchip,mcp25625"; + reg =3D <3>; + clocks =3D <&mcp_clock>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&pinctrl_can4>; + pinctrl-names =3D "default"; + spi-max-frequency =3D <10000000>; + xceiver-supply =3D <®_can4_stby>; + }; +}; + +&gpu_2d { + status =3D "disabled"; +}; + +&gpu_3d { + status =3D "disabled"; +}; + +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c2>; + pinctrl-1 =3D <&pinctrl_i2c2_gpio>; + scl-gpios =3D <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; +}; + +&i2c3 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_i2c3>; + pinctrl-1 =3D <&pinctrl_i2c3_gpio>; + pinctrl-names =3D "default", "gpio"; + scl-gpios =3D <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + lp5012@14 { + compatible =3D "ti,lp5012"; + reg =3D <0x14>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + multi-led@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + color =3D ; + label =3D "case-led1"; + + led@0 { + color =3D ; + reg =3D <0>; + }; + + led@1 { + color =3D ; + reg =3D <1>; + }; + + led@2 { + color =3D ; + reg =3D <2>; + }; + }; + + multi-led@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + color =3D ; + label =3D "case-led2"; + + led@0 { + color =3D ; + reg =3D <0>; + }; + + led@1 { + color =3D ; + reg =3D <1>; + }; + + led@2 { + color =3D ; + reg =3D <2>; + }; + }; + + multi-led@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + color =3D ; + label =3D "case-led3"; + + led@0 { + color =3D ; + reg =3D <0>; + }; + + led@1 { + color =3D ; + reg =3D <1>; + }; + + led@2 { + color =3D ; + reg =3D <2>; + }; + }; + + multi-led@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + color =3D ; + label =3D "case-led4"; + + led@0 { + color =3D ; + reg =3D <0>; + }; + + led@1 { + color =3D ; + reg =3D <1>; + }; + + led@2 { + color =3D ; + reg =3D <2>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 + MX8MM_DSE_X1 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can1_reg: can1reggrp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can2: can2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can2_reg: can2reggrp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can3: can3grp { + fsl,pins =3D < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can3_reg: can3reggrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can4: can4grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can4_reg: can4reggrp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins =3D < + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins =3D < + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 + MX8MM_DSE_X1 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 + MX8MM_DSE_X1 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 + MX8MM_DSE_X1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_reg_m2: reg-m2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 + MX8MM_DSE_X1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc2: pinctrlusdhc2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + >; + }; + + pinctrl_wl_int: wlintgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 + (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_wl_reg: wlreggrp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 + MX8MM_DSE_X1 + >; + }; +}; + +&uart1 { + pinctrl-0 =3D <&pinctrl_uart1>; + pinctrl-names =3D "default"; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + device-wakeup-gpios =3D <&gpio5 13 GPIO_ACTIVE_HIGH>; + interrupt-names =3D "host-wakeup"; + interrupt-parent =3D <&gpio3>; + interrupts =3D <25 IRQ_TYPE_EDGE_FALLING>; + max-speed =3D <921600>; + pinctrl-0 =3D <&pinctrl_bt>; + pinctrl-names =3D "default"; + shutdown-gpios =3D <&gpio1 1 GPIO_ACTIVE_HIGH>; + vbat-supply =3D <®_3v3_m2>; + vddio-supply =3D <®_3v3_m2>; + }; +}; + +&uart2 { + pinctrl-0 =3D <&pinctrl_uart2>; + pinctrl-names =3D "default"; + uart-has-rtscts; + status =3D "okay"; +}; + +&uart3 { + pinctrl-0 =3D <&pinctrl_uart3>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart4 { + pinctrl-0 =3D <&pinctrl_uart4>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&usbotg1 { + disable-over-current; + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode =3D "host"; + vbus-supply =3D <®_5v0>; + status =3D "okay"; +}; + +&usdhc2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + cap-power-off-card; + keep-power-in-suspend; + max-frequency =3D <50000000>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + pinctrl-0 =3D <&pinctrl_usdhc2>; + pinctrl-names =3D "default"; + sd-uhs-sdr25; + vmmc-supply =3D <®_3v3_m2>; + status =3D "okay"; + + wifi@1 { + compatible =3D "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; + reg =3D <1>; + pinctrl-0 =3D <&pinctrl_wl_int>; + pinctrl-names =3D "default"; + interrupt-names =3D "host-wake"; + interrupt-parent =3D <&gpio3>; + interrupts =3D <20 IRQ_TYPE_LEVEL_LOW>; + brcm,board-type =3D "GOcontroll,moduline"; + }; +}; + +&vpu_blk_ctrl { + status =3D "disabled"; +}; + +&vpu_g1 { + status =3D "disabled"; +}; + +&vpu_g2 { + status =3D "disabled"; +}; + +&wdog1 { + status =3D "okay"; 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Thu, 9 Oct 2025 10:54:20 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Thu, 09 Oct 2025 12:54:21 +0200 Subject: [PATCH 5/5] arm64: dts: freescale: Add the GOcontroll Moduline Mini Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251009-mini_iv-v1-5-f3889c492457@gocontroll.com> References: <20251009-mini_iv-v1-0-f3889c492457@gocontroll.com> In-Reply-To: <20251009-mini_iv-v1-0-f3889c492457@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1760007259; l=18111; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=J647DtXUTxsNjsDze9wWBSEDDuxvPBUjd4pLpGoUQyo=; b=Gg2hKW2ohesxe3eBFG3qKEvyyM4ex/761Mw+Yu8/ToUPCr8JG8QWWLC+YHXO6vJ/JhHLUd5yb 3SFhmuWVAP3CxbvYWfniBkEcnSPYvfVir6Sw171p8uY2PPxazoFnkFp X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings The Moduline Mini is a part of the wider GOcontroll Moduline ecosystem. The= se are embedded controllers that focus on modularity with their swappable IO modules. Features: - up to 4 Moduline IO modules - 2 CAN busses - 1 Ethernet - 4 RGB leds - 1 3D accelerometer - optional Wi-Fi/Bluetooth - optional 4G/GPS Signed-off-by: Maud Spierings --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../imx8mm-tx8m-1610-moduline-mini-111.dts | 691 +++++++++++++++++= ++++ 2 files changed, 692 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index b2fef44e0a370..0a84c7dc89e39 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -125,6 +125,7 @@ imx8mm-evkb-pcie-ep-dtbs +=3D imx8mm-evkb.dtb imx-pcie0= -ep.dtbo dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-evk-pcie-ep.dtb imx8mm-evkb-pcie-ep.dtb =20 dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-tx8m-1610-moduline-iv-306-d.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-tx8m-1610-moduline-mini-111.dtb =20 dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-icore-mx8mm-edimm2.2.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-1= 11.dts b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-111.d= ts new file mode 100644 index 0000000000000..651524781a7ba --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-111.dts @@ -0,0 +1,691 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Maud Spierings + */ + +/dts-v1/; + +#include "imx8mm-tx8m-1610.dtsi" +#include + +/ { + chassis-type =3D "embedded"; + compatible =3D "gocontroll,moduline-mini", "fsl,imx8mm"; + hardware =3D "Moduline Mini V1.11"; + model =3D "GOcontroll Moduline Mini"; + + aliases { + usb-host =3D &usbotg2; + usbotg =3D &usbotg1; + spi0 =3D &ecspi2; /* spidev number compatibility */ + spi1 =3D &ecspi3; /* spidev number compatibility */ + spi2 =3D &ecspi1; /* spidev number compatibility */ + }; + + chosen { + stdout-path =3D "serial2:115200n8"; + }; + + mcp_clock: mcp-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <20000000>; + }; + + reg_3v3_comm: regulator-3v3-communication { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio1 11 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_reg_comm>; + pinctrl-names =3D "default"; + power-supply =3D <®_6v4>; + /* also powers the cellular modem which can't vote on the regulator */ + regulator-always-on; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "3v3_comm"; + }; + + reg_5v0: regulator-5v0 { + compatible =3D "regulator-fixed"; + power-supply =3D <®_6v4>; + regulator-always-on; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "5v0"; + }; + + reg_6v4: regulator-6v4 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt =3D <6400000>; + regulator-min-microvolt =3D <6400000>; + regulator-name =3D "6v4"; + }; + + reg_can1_stby: regulator-can1-stby { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&pinctrl_can1_reg>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "can1-stby"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible =3D "regulator-fixed"; + gpio =3D <&gpio3 15 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&pinctrl_can2_reg>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "can2-stby"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + pinctrl-0 =3D <&pinctrl_wl_reg>; + pinctrl-names =3D "default"; + post-power-on-delay-ms =3D <100>; + power-off-delay-us =3D <500000>; + reset-gpios =3D <&gpio5 28 GPIO_ACTIVE_LOW>; + }; +}; + +&ecspi1 { + pinctrl-0 =3D <&pinctrl_ecspi1>; + pinctrl-names =3D "default"; + cs-gpios =3D < + &gpio4 27 GPIO_ACTIVE_LOW + &gpio3 23 GPIO_ACTIVE_LOW + &gpio3 1 GPIO_ACTIVE_LOW + >; + status =3D "okay"; + + connector@0 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <0>; + i2c-bus =3D <&i2c2>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio4 28 GPIO_ACTIVE_LOW>; + slot-number =3D <3>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_vdd_3v3>; + }; + + connector@1 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <1>; + i2c-bus =3D <&i2c2>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <19 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio3 21 GPIO_ACTIVE_LOW>; + slot-number =3D <4>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_vdd_3v3>; + }; + + adc@2 { + compatible =3D "microchip,mcp3004"; + reg =3D <2>; + spi-max-frequency =3D <2300000>; + vref-supply =3D <®_vdd_3v3>; + }; +}; + +&ecspi2 { + pinctrl-0 =3D <&pinctrl_ecspi2>; + pinctrl-names =3D "default"; + cs-gpios =3D < + &gpio3 24 GPIO_ACTIVE_LOW + &gpio3 9 GPIO_ACTIVE_LOW + >; + status =3D "okay"; + + can@0 { + compatible =3D "microchip,mcp25625"; + reg =3D <0>; + clocks =3D <&mcp_clock>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <22 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&pinctrl_can1>; + pinctrl-names =3D "default"; + spi-max-frequency =3D <10000000>; + xceiver-supply =3D <®_can1_stby>; + }; + + can@1 { + compatible =3D "microchip,mcp25625"; + reg =3D <1>; + clocks =3D <&mcp_clock>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&pinctrl_can2>; + pinctrl-names =3D "default"; + spi-max-frequency =3D <10000000>; + xceiver-supply =3D <®_can2_stby>; + }; +}; + +&ecspi3 { + pinctrl-0 =3D <&pinctrl_ecspi3>; + pinctrl-names =3D "default"; + cs-gpios =3D < + &gpio1 9 GPIO_ACTIVE_LOW + &gpio1 2 GPIO_ACTIVE_LOW + >; + status =3D "okay"; + + connector@0 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <0>; + i2c-bus =3D <&i2c2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <10 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio1 7 GPIO_ACTIVE_LOW>; + slot-number =3D <1>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_vdd_3v3>; + }; + + connector@1 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <1>; + i2c-bus =3D <&i2c2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <5 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio5 21 GPIO_ACTIVE_LOW>; + slot-number =3D <2>; + spi-max-frequency =3D <54000000>; + sync-gpios =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply =3D <®_6v4>; + vddp-supply =3D <®_5v0>; + vdd-supply =3D <®_vdd_3v3>; + }; +}; + +&gpu_2d { + status =3D "disabled"; +}; + +&gpu_3d { + status =3D "disabled"; +}; + +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_i2c2>; + pinctrl-1 =3D <&pinctrl_i2c2_gpio>; + pinctrl-names =3D "default", "gpio"; + scl-gpios =3D <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; +}; + +&i2c3 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_i2c3>; + pinctrl-1 =3D <&pinctrl_i2c3_gpio>; + pinctrl-names =3D "default", "gpio"; + scl-gpios =3D <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + lp5012@14 { + compatible =3D "ti,lp5012"; + reg =3D <0x14>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + multi-led@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + color =3D ; + label =3D "case-led1"; + + led@0 { + reg =3D <0>; + color =3D ; + }; + + led@1 { + reg =3D <1>; + color =3D ; + }; + + led@2 { + reg =3D <2>; + color =3D ; + }; + }; + + multi-led@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + color =3D ; + label =3D "case-led2"; + + led@0 { + reg =3D <0>; + color =3D ; + }; + + led@1 { + reg =3D <1>; + color =3D ; + }; + + led@2 { + reg =3D <2>; + color =3D ; + }; + }; + + multi-led@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + color =3D ; + label =3D "case-led3"; + + led@0 { + reg =3D <0>; + color =3D ; + }; + + led@1 { + reg =3D <1>; + color =3D ; + }; + + led@2 { + reg =3D <2>; + color =3D ; + }; + }; + + multi-led@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + color =3D ; + label =3D "case-led4"; + + led@0 { + reg =3D <0>; + color =3D ; + }; + + led@1 { + reg =3D <1>; + color =3D ; + }; + + led@2 { + reg =3D <2>; + color =3D ; + }; + }; + }; + + accelerometer@18 { + compatible =3D "st,lis2dw12"; + reg =3D <0x18>; + interrupt-parent =3D <&gpio5>; + interrupts =3D <3 IRQ_TYPE_EDGE_RISING>, <5 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 =3D <&pinctrl_lis_int>; + pinctrl-names =3D "default"; + vddio-supply =3D <®_vdd_3v3>; + vdd-supply =3D <®_vdd_3v3>; + }; + + humidity-sensor@5f { + compatible =3D "st,hts221"; + reg =3D <0x5f>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <10 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 =3D <&pinctrl_hts_int>; + pinctrl-names =3D "default"; + vdd-supply =3D <®_vdd_3v3>; + }; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 + MX8MM_DSE_X1 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can1_reg: can1reggrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can2: can2grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can2_reg: can2reggrp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins =3D < + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins =3D < + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 + MX8MM_DSE_X1 + >; + }; + + pinctrl_hts_int: htsintgrp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 + (MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_lis_int: lisintgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 + (MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 + (MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_reg_comm: reg_commgrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 + MX8MM_DSE_X1 + >; + }; + + pinctrl_sysfs_gpios: sysfsgpiogrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 + MX8MM_DSE_X1 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 + MX8MM_DSE_X1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc2: pinctrlusdhc2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + >; + }; + + pinctrl_wl_int: wlintgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 + (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_wl_reg: wlreggrp { + fsl,pins =3D < + MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 + MX8MM_DSE_X1 + >; + }; +}; + +&uart1 { + pinctrl-0 =3D <&pinctrl_uart1>; + pinctrl-names =3D "default"; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + device-wakeup-gpios =3D <&gpio5 13 GPIO_ACTIVE_HIGH>; + interrupt-names =3D "host-wakeup"; + interrupt-parent =3D <&gpio3>; + interrupts =3D <25 IRQ_TYPE_EDGE_FALLING>; + max-speed =3D <921600>; + pinctrl-0 =3D <&pinctrl_bt>; + pinctrl-names =3D "default"; + shutdown-gpios =3D <&gpio1 1 GPIO_ACTIVE_HIGH>; + vbat-supply =3D <®_3v3_comm>; + vddio-supply =3D <®_3v3_comm>; + }; +}; + +&uart2 { + pinctrl-0 =3D <&pinctrl_uart2>; + pinctrl-names =3D "default"; + uart-has-rtscts; + status =3D "okay"; +}; + +&uart3 { + pinctrl-0 =3D <&pinctrl_uart3>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&usbotg1 { + disable-over-current; + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode =3D "host"; + vbus-supply =3D <®_5v0>; + status =3D "okay"; +}; + +&usdhc2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + cap-power-off-card; + keep-power-in-suspend; + max-frequency =3D <50000000>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + pinctrl-0 =3D <&pinctrl_usdhc2>; + pinctrl-names =3D "default"; + sd-uhs-sdr25; + vmmc-supply =3D <®_3v3_comm>; + status =3D "okay"; + + wifi@1 { + compatible =3D "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; + reg =3D <1>; + pinctrl-0 =3D <&pinctrl_wl_int>; + pinctrl-names =3D "default"; + interrupt-names =3D "host-wake"; + interrupt-parent =3D <&gpio3>; + interrupts =3D <20 IRQ_TYPE_LEVEL_LOW>; + brcm,board-type =3D "GOcontroll,moduline"; + }; +}; + +&vpu_blk_ctrl { + status =3D "disabled"; +}; + +&vpu_g1 { + status =3D "disabled"; +}; + +&vpu_g2 { + status =3D "disabled"; +}; + +&wdog1 { + status =3D "okay"; +}; --=20 2.51.0