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Miller" Cc: linux-arm-msm@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, Abhinaba Rakshit X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA4MDEyMSBTYWx0ZWRfXwvg9MSXueKpw MsaaPUtFAQZTekPbwMvrplZ0Nzg58eEvJYugbUaq00hYLHVzm+o7nf/lWtusZokbHHbIVnaI4un UPK+Ow3VAifRBv4DYW0Z6o2SSHE++axpzhmMhFB1rDMHA2hnXcBtrcBgZn8uHYiZxThZ7Pf2PhM /Ek+5QWFVLa6sElJM2n/p7NPxFhlgrM/pywU/py2knlemvYm0cKnjhoRpcbdvFL17SmNsBA8cHn hMQM3Ts68aKYNUvULpCdiee1doqUTcJ/9p9DGjQb7GffYzC8EVsM6lCHEsQqxiySWFKgInAbIRG 3TIlagkqDUCn+XUlIwnn4wZkqF7liuD4HJowVAPaGZJiYhOxn9mQs1cVbILdYS1gtBg64H/UkE2 vdi+slvM/he4WbPlzyMOZ78Xt08e8Q== X-Proofpoint-GUID: 0zCA5G_f97sx6px0ZEOkSZkYjQs2ih47 X-Proofpoint-ORIG-GUID: 0zCA5G_f97sx6px0ZEOkSZkYjQs2ih47 X-Authority-Analysis: v=2.4 cv=SJxPlevH c=1 sm=1 tr=0 ts=68e753f3 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=EUspDBNiAAAA:8 a=IdboCmTcumTcOcSitEMA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-09_01,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 impostorscore=0 spamscore=0 phishscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510080121 Add separate ICE nodes for eMMC and UFS for QCS615 platform. Signed-off-by: Abhinaba Rakshit --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 51 +++++++++++++++++++++-----------= ---- 1 file changed, 30 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qco= m/sm6150.dtsi index 3d2a1cb02b628a5db7ca14bea784429be5a020f9..bc1167b86e3896b9a54290e6a55= ee2fa75a48c27 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -549,11 +549,9 @@ rng@793000 { sdhc_1: mmc@7c4000 { compatible =3D "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x0 0x007c4000 0x0 0x1000>, - <0x0 0x007c5000 0x0 0x1000>, - <0x0 0x007c8000 0x0 0x8000>; + <0x0 0x007c5000 0x0 0x1000>; reg-names =3D "hc", - "cqhci", - "ice"; + "cqhci"; =20 interrupts =3D , ; @@ -562,12 +560,10 @@ sdhc_1: mmc@7c4000 { =20 clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_SDCC1_ICE_CORE_CLK>; + <&rpmhcc RPMH_CXO_CLK>; clock-names =3D "iface", "core", - "xo", - "ice"; + "xo"; =20 resets =3D <&gcc GCC_SDCC1_BCR>; =20 @@ -587,6 +583,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, dma-coherent; =20 status =3D "disabled"; + qcom,ice =3D <&ice_mmc>; =20 sdhc1_opp_table: opp-table { compatible =3D "operating-points-v2"; @@ -613,6 +610,15 @@ opp-384000000 { }; }; =20 + ice_mmc: crypto@7c8000 { + compatible =3D "qcom,qcs615-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg =3D <0x0 0x7c8000 0x0 0x8000>; + clocks =3D <&gcc GCC_SDCC1_ICE_CORE_CLK>; + freq-table-hz =3D <75000000 300000000>; + status =3D "disabled"; + }; + gpi_dma0: dma-controller@800000 { compatible =3D "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; reg =3D <0x0 0x800000 0x0 0x60000>; @@ -1249,10 +1255,8 @@ pcie_phy: phy@1c0e000 { =20 ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg =3D <0x0 0x01d84000 0x0 0x3000>, - <0x0 0x01d90000 0x0 0x8000>; - reg-names =3D "std", - "ice"; + reg =3D <0x0 0x01d84000 0x0 0x3000>; + reg-names =3D "std"; =20 interrupts =3D ; =20 @@ -1260,7 +1264,6 @@ ufs_mem_hc: ufshc@1d84000 { <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; @@ -1270,8 +1273,7 @@ ufs_mem_hc: ufshc@1d84000 { "core_clk_unipro", "ref_clk", "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "ice_core_clk"; + "rx_lane0_sync_clk"; =20 resets =3D <&gcc GCC_UFS_PHY_BCR>; reset-names =3D "rst"; @@ -1297,6 +1299,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, #reset-cells =3D <1>; =20 status =3D "disabled"; + qcom,ice =3D <&ice>; =20 ufs_opp_table: opp-table { compatible =3D "operating-points-v2"; @@ -1308,8 +1311,7 @@ opp-50000000 { /bits/ 64 <37500000>, /bits/ 64 <0>, /bits/ 64 <0>, - /bits/ 64 <0>, - /bits/ 64 <75000000>; + /bits/ 64 <0>; required-opps =3D <&rpmhpd_opp_low_svs>; }; =20 @@ -1320,8 +1322,7 @@ opp-100000000 { /bits/ 64 <75000000>, /bits/ 64 <0>, /bits/ 64 <0>, - /bits/ 64 <0>, - /bits/ 64 <150000000>; + /bits/ 64 <0>; required-opps =3D <&rpmhpd_opp_svs>; }; =20 @@ -1332,8 +1333,7 @@ opp-200000000 { /bits/ 64 <150000000>, /bits/ 64 <0>, /bits/ 64 <0>, - /bits/ 64 <0>, - /bits/ 64 <300000000>; + /bits/ 64 <0>; required-opps =3D <&rpmhpd_opp_nom>; }; }; @@ -1360,6 +1360,15 @@ ufs_mem_phy: phy@1d87000 { status =3D "disabled"; }; =20 + ice: crypto@1d90000 { + compatible =3D "qcom,qcs615-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg =3D <0x0 0x01d90000 0x0 0x8000>; + clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + freq-table-hz =3D <75000000 300000000>; + status =3D "disabled"; + }; + cryptobam: dma-controller@1dc4000 { compatible =3D "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg =3D <0x0 0x01dc4000 0x0 0x24000>; --=20 2.34.1