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charset="utf-8" Update the bindings to support reading ID state and VBUS, as per the HD3SS3220 data sheet. The ID pin is kept high if VBUS is not at VSafe0V and asserted low once VBUS is at VSafe0V, enforcing the Type-C requirement that VBUS must be at VSafe0V before re-enabling VBUS. Add id-gpios property to describe the input gpio for USB ID pin and vbus- supply property to describe the regulator for USB VBUS. Signed-off-by: Krishna Kurapati --- .../devicetree/bindings/usb/ti,hd3ss3220.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml b/Docu= mentation/devicetree/bindings/usb/ti,hd3ss3220.yaml index bec1c8047bc0..c869eece39a7 100644 --- a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml +++ b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml @@ -25,6 +25,19 @@ properties: interrupts: maxItems: 1 =20 + id-gpios: + description: + An input gpio for USB ID pin. Upon detecting a UFP device, HD3SS3220 + will keep ID pin high if VBUS is not at VSafe0V. Once VBUS is at VSa= fe0V, + the HD3SS3220 will assert ID pin low. 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Wed, 08 Oct 2025 10:58:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGY4sUxC2tkm7oYuuyKz8ydAmypwi3ie0On6gCk1oXghiSu6JmLInMP6vDCt0OA/hoeAYbvzg== X-Received: by 2002:a17:90b:1b04:b0:32b:6145:fa63 with SMTP id 98e67ed59e1d1-33b5114d48fmr5471911a91.4.1759946295416; Wed, 08 Oct 2025 10:58:15 -0700 (PDT) Received: from hu-kriskura-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-33b529f51b5sm1275726a91.7.2025.10.08.10.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Oct 2025 10:58:15 -0700 (PDT) From: Krishna Kurapati To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus , Liam Girdwood , Mark Brown , Biju Das Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krishna Kurapati Subject: [PATCH v2 2/2] usb: typec: hd3ss3220: Enable VBUS based on ID pin state Date: Wed, 8 Oct 2025 23:27:50 +0530 Message-Id: <20251008175750.1770454-3-krishna.kurapati@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251008175750.1770454-1-krishna.kurapati@oss.qualcomm.com> References: <20251008175750.1770454-1-krishna.kurapati@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA4MDEyMSBTYWx0ZWRfX25hhlxiLpe/2 DSsZ3WlLKomsjrkMSBOpJdvn4Z3ds33BIP0hriXvkPbbaRaAUubcEB2lN49/uk/KPeQCdPyHMVr iVQLDeSfE335P2S7EbYmcYdMtHM7+b0DUJ0Ch5hZwYxwN3WhnkcBLbi31LpkSi2nfvHoWlahemT 6iaB/szYmqxXE3kcuqoQgmsjUIKnAISC1wSBJgu3h+PgwaZOmOKNI5zOO3WHj59jngmBD1n/96p J2OM/evonWUoXBPMUzHdS5EgeoH2fdYAq0mBKXrtk2lIoy1QcmaNPjlANlcOfIB01CGc1zqxIEP TU5E7vkCjafbcRHiIW96FVDKrNPwSUIELGOHVWESh6yM7T10z2oy32OUI9GJgHpENap7N2ur1tt p3XlzXtETTO7leQMQLXbvXF8tRvjIA== X-Proofpoint-ORIG-GUID: mAlF_2_bUA4Khot4GkTxQObgp48OSpUo X-Proofpoint-GUID: mAlF_2_bUA4Khot4GkTxQObgp48OSpUo X-Authority-Analysis: v=2.4 cv=VK3QXtPX c=1 sm=1 tr=0 ts=68e6a639 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=x6icFKpwvdMA:10 a=EUspDBNiAAAA:8 a=3eHL1KmHa9FwJ4YL2wMA:9 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-08_05,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 phishscore=0 clxscore=1015 impostorscore=0 bulkscore=0 spamscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510080121 Content-Type: text/plain; charset="utf-8" There is a ID pin present on HD3SS3220 controller that can be routed to SoC. As per the datasheet: "Upon detecting a UFP device, HD3SS3220 will keep ID pin high if VBUS is not at VSafe0V. Once VBUS is at VSafe0V, the HD3SS3220 will assert ID pin low. This is done to enforce Type-C requirement that VBUS must be at VSafe0V before re-enabling VBUS" Add support to read the ID pin state and enable VBUS accordingly. Signed-off-by: Krishna Kurapati --- drivers/usb/typec/hd3ss3220.c | 60 +++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/usb/typec/hd3ss3220.c b/drivers/usb/typec/hd3ss3220.c index 3ecc688dda82..0e81e92f253c 100644 --- a/drivers/usb/typec/hd3ss3220.c +++ b/drivers/usb/typec/hd3ss3220.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include =20 #define HD3SS3220_REG_CN_STAT 0x08 #define HD3SS3220_REG_CN_STAT_CTRL 0x09 @@ -54,6 +56,11 @@ struct hd3ss3220 { struct delayed_work output_poll_work; enum usb_role role_state; bool poll; + + struct gpio_desc *id_gpiod; + int id_irq; + + struct regulator *vbus; }; =20 static int hd3ss3220_set_power_opmode(struct hd3ss3220 *hd3ss3220, int pow= er_opmode) @@ -319,6 +326,28 @@ static const struct regmap_config config =3D { .max_register =3D 0x0A, }; =20 +static irqreturn_t hd3ss3220_id_isr(int irq, void *dev_id) +{ + struct hd3ss3220 *hd3ss3220 =3D dev_id; + int ret; + int id; + + if (IS_ERR_OR_NULL(hd3ss3220->vbus)) + return IRQ_HANDLED; + + id =3D hd3ss3220->id_gpiod ? gpiod_get_value_cansleep(hd3ss3220->id_gpiod= ) : 1; + + if (!id) { + ret =3D regulator_enable(hd3ss3220->vbus); + if (ret) + dev_err(hd3ss3220->dev, "enable vbus regulator failed\n"); + } else { + regulator_disable(hd3ss3220->vbus); + } + + return IRQ_HANDLED; +} + static int hd3ss3220_probe(struct i2c_client *client) { struct typec_capability typec_cap =3D { }; @@ -354,6 +383,37 @@ static int hd3ss3220_probe(struct i2c_client *client) hd3ss3220->role_sw =3D usb_role_switch_get(hd3ss3220->dev); } =20 + hd3ss3220->id_gpiod =3D devm_gpiod_get_optional(hd3ss3220->dev, "id", GPI= OD_IN); + if (IS_ERR(hd3ss3220->id_gpiod)) + return PTR_ERR(hd3ss3220->id_gpiod); + + if (hd3ss3220->id_gpiod) { + hd3ss3220->id_irq =3D gpiod_to_irq(hd3ss3220->id_gpiod); + if (hd3ss3220->id_irq < 0) { + dev_err(hd3ss3220->dev, "failed to get ID IRQ\n"); + return hd3ss3220->id_irq; + } + + ret =3D devm_request_threaded_irq(hd3ss3220->dev, + hd3ss3220->id_irq, NULL, + hd3ss3220_id_isr, + IRQF_TRIGGER_RISING | + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + dev_name(hd3ss3220->dev), hd3ss3220); + if (ret < 0) { + dev_err(hd3ss3220->dev, "failed to get id irq\n"); + return ret; + } + } + + hd3ss3220->vbus =3D devm_regulator_get_optional(hd3ss3220->dev, "vbus"); + if (PTR_ERR(hd3ss3220->vbus) =3D=3D -ENODEV) + hd3ss3220->vbus =3D NULL; + + if (IS_ERR(hd3ss3220->vbus)) + return dev_err_probe(hd3ss3220->dev, + PTR_ERR(hd3ss3220->vbus), "failed to get vbus\n"); + if (IS_ERR(hd3ss3220->role_sw)) { ret =3D PTR_ERR(hd3ss3220->role_sw); goto err_put_fwnode; --=20 2.34.1