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charset="utf-8" Remove eMMC support from the IPQ5424 RDP466 board configuration to resolve GPIO pin conflicts with SPI NAND interface. The IPQ5424 RDP466 board is designed with NOR + NAND as the default boot mode configuration. The eMMC controller and SPI NAND controller share the same GPIO pins, creating a hardware conflict: Signed-off-by: Md Sadre Alam Reviewed-by: Konrad Dybcio --- Change in [v2] * updated board name commit message header Change in [v1] * Removed eMMC node arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 30 --------------------- 1 file changed, 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/= dts/qcom/ipq5424-rdp466.dts index 7c32fb8f9f73..de71b72ae6dc 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -124,13 +124,6 @@ &qusb_phy_1 { status =3D "okay"; }; =20 -&sdhc { - pinctrl-0 =3D <&sdc_default_state>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - &sleep_clk { clock-frequency =3D <32000>; }; @@ -201,29 +194,6 @@ mosi-pins { }; }; =20 - sdc_default_state: sdc-default-state { - clk-pins { - pins =3D "gpio5"; - function =3D "sdc_clk"; - drive-strength =3D <8>; - bias-disable; - }; - - cmd-pins { - pins =3D "gpio4"; - function =3D "sdc_cmd"; - drive-strength =3D <8>; - bias-pull-up; - }; - - data-pins { - pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; - function =3D "sdc_data"; - drive-strength =3D <8>; - bias-pull-up; - }; - }; - qpic_snand_default_state: qpic-snand-default-state { clock-pins { pins =3D "gpio5"; --=20 2.34.1