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charset="utf-8" Enable QPIC SPI NAND flash controller support on the IPQ5424 RDP466 reference design platform. The RDP466 board features a SPI NAND flash device connected to the QPIC controller for primary storage. This patch enables the QPIC BAM DMA controller and SPI NAND interface of QPIC, and configures the necessary pin control settings for proper operation. Reviewed-by: Konrad Dybcio Signed-off-by: Md Sadre Alam --- Change in [v2] * Added Reviewed-by tag * Added \n before status in qpic_nand node Change in [v1] * Enable bam and spi nand for ipq5424 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 44 +++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/= dts/qcom/ipq5424-rdp466.dts index 738618551203..7c32fb8f9f73 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -224,6 +224,29 @@ data-pins { }; }; =20 + qpic_snand_default_state: qpic-snand-default-state { + clock-pins { + pins =3D "gpio5"; + function =3D "qspi_clk"; + drive-strength =3D <8>; + bias-pull-down; + }; + + cs-pins { + pins =3D "gpio4"; + function =3D "qspi_cs"; + drive-strength =3D <8>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "qspi_data"; + drive-strength =3D <8>; + bias-pull-down; + }; + }; + uart0_pins: uart0-default-state { pins =3D "gpio10", "gpio11", "gpio12", "gpio13"; function =3D "uart0"; @@ -246,6 +269,27 @@ pcie3_default_state: pcie3-default-state { }; }; =20 +&qpic_bam { + status =3D "okay"; +}; + +&qpic_nand { + pinctrl-0 =3D <&qpic_snand_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + flash@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + nand-ecc-engine =3D <&qpic_nand>; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + }; +}; + &uart0 { pinctrl-0 =3D <&uart0_pins>; pinctrl-names =3D "default"; --=20 2.34.1