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charset="utf-8" Add device tree nodes for QPIC SPI NAND flash controller support on IPQ5332 SoC. The IPQ5332 SoC includes a QPIC controller that supports SPI NAND flash devices with hardware ECC capabilities and DMA support through BAM (Bus Access Manager). Signed-off-by: Md Sadre Alam --- Change in [v2] * No change Change in [v1] * Added qpic_bam node to describe BAM DMA controller * Added spi nand support for IPQ5332 arch/arm64/boot/dts/qcom/ipq5332.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qc= om/ipq5332.dtsi index 45fc512a3bab..af3fd55a85cf 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -423,6 +423,33 @@ blsp1_spi2: spi@78b7000 { status =3D "disabled"; }; =20 + qpic_bam: dma-controller@7984000 { + compatible =3D "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg =3D <0x07984000 0x1c000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QPIC_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + status =3D "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible =3D "qcom,ipq5332-snand", "qcom,ipq9574-snand"; + reg =3D <0x079b0000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names =3D "core", "aon", "iom"; + dmas =3D <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names =3D "tx", "rx", "cmd"; + status =3D "disabled"; + }; + usb: usb@8af8800 { compatible =3D "qcom,ipq5332-dwc3", "qcom,dwc3"; reg =3D <0x08af8800 0x400>; --=20 2.34.1