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charset="utf-8" Remove eMMC support from the IPQ5332 RDP442 board configuration to align with the board's default NOR+NAND boot mode design. The IPQ5332 RDP442 board is designed with NOR+NAND as the default boot mode configuration. The eMMC and SPI NAND interface share same GPIO Signed-off-by: Md Sadre Alam Reviewed-by: Konrad Dybcio --- Change in [v2] * updated board name commit message header Change in [v1] * Removed eMMC node arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts | 34 --------------------- 1 file changed, 34 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/= dts/qcom/ipq5332-rdp442.dts index ed8a54eb95c0..6e2abde9ed89 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts @@ -35,17 +35,6 @@ flash@0 { }; }; =20 -&sdhc { - bus-width =3D <4>; - max-frequency =3D <192000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-0 =3D <&sdc_default_state>; - pinctrl-names =3D "default"; - status =3D "okay"; -}; - &tlmm { i2c_1_pins: i2c-1-state { pins =3D "gpio29", "gpio30"; @@ -54,29 +43,6 @@ i2c_1_pins: i2c-1-state { bias-pull-up; }; =20 - sdc_default_state: sdc-default-state { - clk-pins { - pins =3D "gpio13"; - function =3D "sdc_clk"; - drive-strength =3D <8>; - bias-disable; - }; - - cmd-pins { - pins =3D "gpio12"; - function =3D "sdc_cmd"; - drive-strength =3D <8>; - bias-pull-up; - }; - - data-pins { - pins =3D "gpio8", "gpio9", "gpio10", "gpio11"; - function =3D "sdc_data"; - drive-strength =3D <8>; - bias-pull-up; - }; - }; - spi_0_data_clk_pins: spi-0-data-clk-state { pins =3D "gpio14", "gpio15", "gpio16"; function =3D "blsp0_spi"; --=20 2.34.1