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charset="utf-8" IPQ5424 contains the QPIC-SPI-NAND flash controller which is the same as the one found in IPQ9574. So let's document the IPQ5424 compatible and use IPQ9574 as the fallback. Acked-by: Rob Herring (Arm) Signed-off-by: Md Sadre Alam --- Change in [v2] * Added Acked-by tag Change in [v1] * Added support for qcom,ipq5424-snand compatible string to the device tree bindings. Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml= b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml index cb1f15224b45..39e086ced891 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml @@ -25,6 +25,7 @@ properties: - items: - enum: - qcom,ipq5018-snand + - qcom,ipq5424-snand - const: qcom,ipq9574-snand - const: qcom,ipq9574-snand =20 --=20 2.34.1 From nobody Mon Feb 9 12:27:15 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91CD52F5496; Wed, 8 Oct 2025 09:04:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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charset="utf-8" IPQ5332 contains the QPIC-SPI-NAND flash controller which is the same as the one found in IPQ9574. So let's document the IPQ5332 compatible and use IPQ9574 as the fallback. Acked-by: Rob Herring (Arm) Signed-off-by: Md Sadre Alam --- Change in [v2] * Added Acked-by tag Change in [v1] * Added support for qcom,ipq5332-snand compatible string to the device tree bindings. Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml= b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml index 39e086ced891..7d0571feb46d 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml @@ -25,6 +25,7 @@ properties: - items: - enum: - qcom,ipq5018-snand + - qcom,ipq5332-snand - qcom,ipq5424-snand - const: qcom,ipq9574-snand - const: qcom,ipq9574-snand --=20 2.34.1 From nobody Mon Feb 9 12:27:15 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA6192F5A24; Wed, 8 Oct 2025 09:04:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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charset="utf-8" BAM version 1.6.0 and later changed the behavior of the mask field in command elements for read operations. In newer BAM versions, the mask field for read commands contains the upper 4 bits of the destination address to support 36-bit addressing, while for write commands it continues to function as a traditional write mask. This change causes NAND enumeration failures on platforms like IPQ5424 that use BAM v1.6.0+, because the current code sets mask=3D0xffffffff for all commands. For read commands on newer BAM versions, this results in the hardware interpreting the destination address as 0xf_xxxxxxxx (invalid high memory) instead of the intended 0x0_xxxxxxxx address. Fixed this issue by: 1. Updating the bam_cmd_element structure documentation to reflect the dual purpose of the mask field 2. Modifying bam_prep_ce_le32() to set appropriate mask values based on command type: - For read commands: mask =3D 0 (32-bit addressing, upper bits =3D 0) - For write commands: mask =3D 0xffffffff (traditional write mask) 3. Maintaining backward compatibility with older BAM versions This fix enables proper NAND functionality on IPQ5424 and other platforms using BAM v1.6.0+ while preserving compatibility with existing systems. Signed-off-by: Md Sadre Alam --- Change in [v2] * No change Change in [v1] * Updated bam_prep_ce_le32() to set the mask field conditionally based on command type * Enhanced kernel-doc comments to clarify mask behavior for BAM v1.6.0+ include/linux/dma/qcom_bam_dma.h | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/include/linux/dma/qcom_bam_dma.h b/include/linux/dma/qcom_bam_= dma.h index 68fc0e643b1b..d9d07a9ab313 100644 --- a/include/linux/dma/qcom_bam_dma.h +++ b/include/linux/dma/qcom_bam_dma.h @@ -13,9 +13,12 @@ * supported by BAM DMA Engine. * * @cmd_and_addr - upper 8 bits command and lower 24 bits register address. - * @data - for write command: content to be written into peripheral regist= er. - * for read command: dest addr to write peripheral register value. - * @mask - register mask. + * @data - For write command: content to be written into peripheral regist= er. + * For read command: lower 32 bits of destination address. + * @mask - For write command: register write mask. + * For read command on BAM v1.6.0+: upper 4 bits of destination address. + * For read command on BAM < v1.6.0: ignored by hardware. + * Setting to 0 ensures 32-bit addressing compatibility. * @reserved - for future usage. * */ @@ -42,6 +45,10 @@ enum bam_command_type { * @addr: target address * @cmd: BAM command * @data: actual data for write and dest addr for read in le32 + * + * For BAM v1.6.0+, the mask field behavior depends on command type: + * - Write commands: mask =3D write mask (typically 0xffffffff) + * - Read commands: mask =3D upper 4 bits of destination address (0 for 32= -bit) */ static inline void bam_prep_ce_le32(struct bam_cmd_element *bam_ce, u32 addr, @@ -50,7 +57,11 @@ bam_prep_ce_le32(struct bam_cmd_element *bam_ce, u32 add= r, bam_ce->cmd_and_addr =3D cpu_to_le32((addr & 0xffffff) | ((cmd & 0xff) << 24)); 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charset="utf-8" Add device tree nodes for QPIC SPI NAND flash controller support on IPQ5424 SoC. The IPQ5424 SoC includes a QPIC controller that supports SPI NAND flash devices with hardware ECC capabilities and DMA support through BAM (Bus Access Manager). Signed-off-by: Md Sadre Alam --- Change in [v2] * No change Change in [v1] * Added qpic_bam node to describe BAM DMA controller * Added spi nand support for IPQ5424 arch/arm64/boot/dts/qcom/ipq5424.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index ef2b52f3597d..81f133568bb6 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -567,6 +567,33 @@ sdhc: mmc@7804000 { status =3D "disabled"; }; =20 + qpic_bam: dma-controller@7984000 { + compatible =3D "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg =3D <0x0 0x07984000 0x0 0x1c000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QPIC_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + status =3D "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible =3D "qcom,ipq5424-snand", "qcom,ipq9574-snand"; + reg =3D <0x0 0x079b0000 0x0 0x10000>; + #address-cells =3D <1>; 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charset="utf-8" Add device tree nodes for QPIC SPI NAND flash controller support on IPQ5332 SoC. The IPQ5332 SoC includes a QPIC controller that supports SPI NAND flash devices with hardware ECC capabilities and DMA support through BAM (Bus Access Manager). Signed-off-by: Md Sadre Alam --- Change in [v2] * No change Change in [v1] * Added qpic_bam node to describe BAM DMA controller * Added spi nand support for IPQ5332 arch/arm64/boot/dts/qcom/ipq5332.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qc= om/ipq5332.dtsi index 45fc512a3bab..af3fd55a85cf 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -423,6 +423,33 @@ blsp1_spi2: spi@78b7000 { status =3D "disabled"; }; =20 + qpic_bam: dma-controller@7984000 { + compatible =3D "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg =3D <0x07984000 0x1c000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QPIC_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + status =3D "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible =3D "qcom,ipq5332-snand", "qcom,ipq9574-snand"; + reg =3D <0x079b0000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; 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charset="utf-8" Enable QPIC SPI NAND flash controller support on the IPQ5424 RDP466 reference design platform. The RDP466 board features a SPI NAND flash device connected to the QPIC controller for primary storage. This patch enables the QPIC BAM DMA controller and SPI NAND interface of QPIC, and configures the necessary pin control settings for proper operation. Reviewed-by: Konrad Dybcio Signed-off-by: Md Sadre Alam --- Change in [v2] * Added Reviewed-by tag * Added \n before status in qpic_nand node Change in [v1] * Enable bam and spi nand for ipq5424 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 44 +++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/= dts/qcom/ipq5424-rdp466.dts index 738618551203..7c32fb8f9f73 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -224,6 +224,29 @@ data-pins { }; }; =20 + qpic_snand_default_state: qpic-snand-default-state { + clock-pins { + pins =3D "gpio5"; + function =3D "qspi_clk"; + drive-strength =3D <8>; + bias-pull-down; + }; + + cs-pins { + pins =3D "gpio4"; + function =3D "qspi_cs"; + drive-strength =3D <8>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "qspi_data"; + drive-strength =3D <8>; + bias-pull-down; + }; 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charset="utf-8" Enable QPIC SPI NAND flash controller support on the IPQ5332 reference design platform. Signed-off-by: Md Sadre Alam Reviewed-by: Konrad Dybcio --- Change in [v2] * No change Change in [v1] * Enable bam and spi nand for ipq5332 .../boot/dts/qcom/ipq5332-rdp-common.dtsi | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/= boot/dts/qcom/ipq5332-rdp-common.dtsi index b37ae7749083..8967861be5fd 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi @@ -78,4 +78,48 @@ gpio_leds_default: gpio-leds-default-state { drive-strength =3D <8>; bias-pull-down; }; + + qpic_snand_default_state: qpic-snand-default-state { + clock-pins { + pins =3D "gpio13"; + function =3D "qspi_clk"; + drive-strength =3D <8>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio12"; + function =3D "qspi_cs"; + drive-strength =3D <8>; + bias-disable; + }; + + data-pins { + pins =3D "gpio8", "gpio9", "gpio10", "gpio11"; + function =3D "qspi_data"; + drive-strength =3D <8>; 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charset="utf-8" Remove eMMC support from the IPQ5424 RDP466 board configuration to resolve GPIO pin conflicts with SPI NAND interface. The IPQ5424 RDP466 board is designed with NOR + NAND as the default boot mode configuration. The eMMC controller and SPI NAND controller share the same GPIO pins, creating a hardware conflict: Signed-off-by: Md Sadre Alam Reviewed-by: Konrad Dybcio --- Change in [v2] * updated board name commit message header Change in [v1] * Removed eMMC node arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 30 --------------------- 1 file changed, 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/= dts/qcom/ipq5424-rdp466.dts index 7c32fb8f9f73..de71b72ae6dc 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -124,13 +124,6 @@ &qusb_phy_1 { status =3D "okay"; }; =20 -&sdhc { - pinctrl-0 =3D <&sdc_default_state>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - &sleep_clk { clock-frequency =3D <32000>; }; @@ -201,29 +194,6 @@ mosi-pins { }; }; =20 - sdc_default_state: sdc-default-state { - clk-pins { - pins =3D "gpio5"; - function =3D "sdc_clk"; - drive-strength =3D <8>; - bias-disable; - }; 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charset="utf-8" Remove eMMC support from the IPQ5332 RDP442 board configuration to align with the board's default NOR+NAND boot mode design. The IPQ5332 RDP442 board is designed with NOR+NAND as the default boot mode configuration. The eMMC and SPI NAND interface share same GPIO Signed-off-by: Md Sadre Alam Reviewed-by: Konrad Dybcio --- Change in [v2] * updated board name commit message header Change in [v1] * Removed eMMC node arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts | 34 --------------------- 1 file changed, 34 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/= dts/qcom/ipq5332-rdp442.dts index ed8a54eb95c0..6e2abde9ed89 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts @@ -35,17 +35,6 @@ flash@0 { }; }; =20 -&sdhc { - bus-width =3D <4>; - max-frequency =3D <192000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-0 =3D <&sdc_default_state>; - pinctrl-names =3D "default"; - status =3D "okay"; -}; - &tlmm { i2c_1_pins: i2c-1-state { pins =3D "gpio29", "gpio30"; @@ -54,29 +43,6 @@ i2c_1_pins: i2c-1-state { bias-pull-up; }; =20 - sdc_default_state: sdc-default-state { - clk-pins { - pins =3D "gpio13"; - function =3D "sdc_clk"; - drive-strength =3D <8>; - bias-disable; - }; - - cmd-pins { - pins =3D "gpio12"; - function =3D "sdc_cmd"; - drive-strength =3D <8>; - bias-pull-up; - }; - - data-pins { - pins =3D "gpio8", "gpio9", "gpio10", "gpio11"; - function =3D "sdc_data"; - drive-strength =3D <8>; - bias-pull-up; - }; - }; - spi_0_data_clk_pins: spi-0-data-clk-state { pins =3D "gpio14", "gpio15", "gpio16"; function =3D "blsp0_spi"; --=20 2.34.1