From nobody Mon Feb 9 15:07:43 2026 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADE552EAB98 for ; Wed, 8 Oct 2025 06:00:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759903219; cv=none; b=Bu99M/6U9wFoCLTknavDtlzVVHeSz9yfgHgkJExRnFAeseKUQa0D99T2BgZXIFRRbfF20kAAFnzLXEAsNQwZBIW24Od5CytH0ZvnYgDsumI9VtVqSyjDtBWw4jybPtijnETqI9PYzxJkpX3M5vdccxb+i3J3rM/jwD2WoG8Lrt0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759903219; c=relaxed/simple; bh=nzwyDM4gckqzqJNKzHDxSnQmR8jk9Hn2kdBip+WceNU=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=EoQejvoicmvPr1EOjVwVOpvUcUs0rte/6H9b4mCWRgZfn5wJXcRivRRkGSGhkom9BGmdKsUHTWkDJRzES6Lh8gEpZcoHb6nwu5lPnL9mA07HqlfNC0UFdGZfCa5O8Na27xuDs6HTaVClnFuuajbNpDu9VbvQKWc0PPdLXQIh+/0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--royluo.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=wLPHVtV/; arc=none smtp.client-ip=209.85.210.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--royluo.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="wLPHVtV/" Received: by mail-pf1-f201.google.com with SMTP id d2e1a72fcca58-7810af03a63so12279264b3a.3 for ; Tue, 07 Oct 2025 23:00:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1759903217; x=1760508017; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=C1S1HZsALDo0cFpkSNcdQcWYCHmdJaR4xyHZpfVsouc=; b=wLPHVtV/1gA6apqpObONHAsP3HUPCZi5pWCMoXvlGAgUmIrtw3Ajh7I03X6LbVeICY RvC0uj1pk8i8gJ9gWwII+FKdHiIB1xwz8/+wWs8DDz5GeBlAfl6+mHD6sQ45eQqHJqb6 ra3eKXyDwtmBkQ+vvcw88z15+DI1a7RKaZHNqJUlap8U+N07xAq3t3FgQ2oEVJuH0oCK NIYBy96P0OizxIh0Jsjm053L2zuaMR54B7ERsgrCJQN7xqbBO44okUCoEqZSVmS+Xn3q JYakGazV1LDqFUTyS5M+/NpwZTra7arbee9dDMZd+AZnUS5UeDu79nFrp1HnocHiHAbb 60BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759903217; x=1760508017; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=C1S1HZsALDo0cFpkSNcdQcWYCHmdJaR4xyHZpfVsouc=; b=rPW/koDw3H8HJaZVCH7KDDcZ4HdDhn6eHYRvnFCkKt7h9Jq5LgYNWX2WRoQ3P43w7U nusqtj4T/ewbSC1hOe2KDvyldnVi7BU34xgeOabu1PPyEG9pbL2Dlc5hsbAEpYbRmkEo Uw/hZWNnA5Tyf8ZkDVoM58sP+mK7UEgNisbXw5ZrVRYNLjrO5LhZIgbSNmw1DJEYU4B4 Lhnau3tW4URLFGcuva/wG+qBdJeO3vKy2ySg2Glxlgm1dXIlbVcJdxAlZsIiY09QT5ht lQF7iuyidfBWRmco+hfqNiWfJ0Yc7cj9CX5MqezuZH3BuLYVmRYL845/8ouFQVk92Qza Y4wA== X-Forwarded-Encrypted: i=1; AJvYcCXbgDE9IfqWe0VdmiDvTKow+LcYS1JJ8za5X+od+A14u8+1i+VJEBA0Z876bnWBPzBZzdijS44JiVOf658=@vger.kernel.org X-Gm-Message-State: AOJu0YwoOZf2ep6bUuOEZ+Rr8zlwXZmd3c8C92LR3QIXKBotnDwtutfZ 6r89snCgJiIIut9EMWJvQMEzdyBB3iefdyvyn54Lc6ADN2WCN+8L+xK9sZPWfbiQP2ya3tpI0u3 X2TnhQQ== X-Google-Smtp-Source: AGHT+IFbK0pAsvf6VaWMTq944nLzy10OXYlG7R8jZOWZq55ApFRCkuPHayisagdgsjB5EBxRTvzYnCGYmT4= X-Received: from pjbrt15.prod.google.com ([2002:a17:90b:508f:b0:32d:def7:e60f]) (user=royluo job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:9191:b0:2b5:769f:2542 with SMTP id adf61e73a8af0-32da83db31cmr3085760637.36.1759903217050; Tue, 07 Oct 2025 23:00:17 -0700 (PDT) Date: Wed, 8 Oct 2025 05:59:58 +0000 In-Reply-To: <20251008060000.3136021-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251008060000.3136021-1-royluo@google.com> X-Mailer: git-send-email 2.51.0.710.ga91ca5db03-goog Message-ID: <20251008060000.3136021-3-royluo@google.com> Subject: [PATCH v2 2/4] usb: dwc3: Add Google Tensor SoC DWC3 glue driver From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , Badhri Jagan Sridharan , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the DWC3 USB controller found on Google Tensor G5. The controller features dual-role functionality and hibernation. The primary focus is implementing hibernation support in host mode, enabling the controller to enter a low-power state (D3). This is particularly relevant during system power state transition and runtime power management for power efficiency. Highlights: - Align suspend callback with dwc3_suspend_common() for deciding between a full teardown and hibernation in host mode. - Integration with `usb_psw_pd` and `usb_top_pd` power domains, managing their states and device links to support hibernation. - A notifier callback dwc3_google_usb_psw_pd_notifier() for `usb_psw_pd` power domain events to manage controller state transitions to/from D3. - Coordination of the `usbc_non_sticky` reset during power state transitions, asserting it on D3 entry and deasserting on D0 entry in hibernation scenario. - Handling of U2 (high-speed) and U3 (super-speed) PME interrupts that are generated by remote wakeup during hibernation. Co-developed-by: Joy Chakraborty Signed-off-by: Joy Chakraborty Co-developed-by: Naveen Kumar Signed-off-by: Naveen Kumar Signed-off-by: Roy Luo --- drivers/usb/dwc3/Kconfig | 10 + drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-google.c | 597 +++++++++++++++++++++++++++++++++ 3 files changed, 608 insertions(+) create mode 100644 drivers/usb/dwc3/dwc3-google.c diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 310d182e10b5..467515d5f937 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -189,4 +189,14 @@ config USB_DWC3_RTK or dual-role mode. Say 'Y' or 'M' if you have such device. =20 +config USB_DWC3_GOOGLE + tristate "Google Platform" + depends on OF && COMMON_CLK && RESET_CONTROLLER + default n + help + Support the DesignWare Core USB3 IP found on Google Tensor + SoCs, starting with the G5 generation. This driver includes + support for hibernation in host mode. + Say 'Y' or 'M' if you have one such device. + endif diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 830e6c9e5fe0..a94982630657 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) +=3D dwc3-imx8mp.o obj-$(CONFIG_USB_DWC3_XILINX) +=3D dwc3-xilinx.o obj-$(CONFIG_USB_DWC3_OCTEON) +=3D dwc3-octeon.o obj-$(CONFIG_USB_DWC3_RTK) +=3D dwc3-rtk.o +obj-$(CONFIG_USB_DWC3_GOOGLE) +=3D dwc3-google.o diff --git a/drivers/usb/dwc3/dwc3-google.c b/drivers/usb/dwc3/dwc3-google.c new file mode 100644 index 000000000000..67c51a051626 --- /dev/null +++ b/drivers/usb/dwc3/dwc3-google.c @@ -0,0 +1,597 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dwc3-google.c - Google DWC3 Specific Glue Layer + * + * Copyright (c) 2025, Google LLC + * Author: Roy Luo + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "core.h" +#include "glue.h" + +/* HOST CFG registers */ +#define HC_STATUS_OFFSET 0x0 +#define HC_STATUS_CURRENT_POWER_STATE_U2PMU GENMASK(1, 0) +#define HC_STATUS_CURRENT_POWER_STATE_U3PMU GENMASK(4, 3) + +#define HOST_CFG1_OFFSET 0x4 +#define HOST_CFG1_PME_EN BIT(3) +#define HOST_CFG1_PM_POWER_STATE_REQUEST GENMASK(5, 4) +#define HOST_CFG1_PM_POWER_STATE_D0 0x0 +#define HOST_CFG1_PM_POWER_STATE_D3 0x3 + +/* USBINT registers */ +#define USBINT_CFG1_OFFSET 0x0 +#define USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK BIT(2) +#define USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK BIT(3) +#define USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN BIT(8) +#define USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN BIT(9) +#define USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR BIT(14) +#define USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR BIT(15) + +#define USBINT_STATUS_OFFSET 0x4 +#define USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW BIT(2) +#define USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW BIT(3) + +#define DWC3_GOOGLE_MAX_RESETS 5 + +struct dwc3_google { + struct device *dev; + struct dwc3 dwc; + struct clk_bulk_data *clks; + int num_clks; + struct reset_control_bulk_data rsts[DWC3_GOOGLE_MAX_RESETS]; + int num_rsts; + struct reset_control *usbc_non_sticky_rst; + struct device *usb_psw_pd; + struct device_link *usb_psw_pd_dl; + struct notifier_block usb_psw_pd_nb; + struct device *usb_top_pd; + struct device_link *usb_top_pd_dl; + void __iomem *host_cfg_base; + void __iomem *usbint_base; + int hs_pme_irq; + int ss_pme_irq; + bool is_hibernation; +}; + +#define to_dwc3_google(d) container_of((d), struct dwc3_google, dwc) + +static int dwc3_google_rst_init(struct dwc3_google *google) +{ + int ret; + + google->num_rsts =3D 5; + google->rsts[0].id =3D "usbc_non_sticky"; + google->rsts[1].id =3D "usbc_sticky"; + google->rsts[2].id =3D "usb_drd_bus"; + google->rsts[3].id =3D "u2phy_apb"; + google->rsts[4].id =3D "usb_top_csr"; + + ret =3D devm_reset_control_bulk_get_exclusive(google->dev, + google->num_rsts, + google->rsts); + + if (ret < 0) + return ret; + + google->usbc_non_sticky_rst =3D google->rsts[0].rstc; + + return 0; +} + +static int dwc3_google_set_pmu_state(struct dwc3_google *google, int state) +{ + u32 reg; + int ret; + + reg =3D readl(google->host_cfg_base + HOST_CFG1_OFFSET); + reg &=3D ~HOST_CFG1_PM_POWER_STATE_REQUEST; + reg |=3D (FIELD_PREP(HOST_CFG1_PM_POWER_STATE_REQUEST, state) | + HOST_CFG1_PME_EN); + writel(reg, google->host_cfg_base + HOST_CFG1_OFFSET); + + ret =3D readl_poll_timeout(google->host_cfg_base + HC_STATUS_OFFSET, reg, + (FIELD_GET(HC_STATUS_CURRENT_POWER_STATE_U2PMU, reg) =3D=3D state && + FIELD_GET(HC_STATUS_CURRENT_POWER_STATE_U3PMU, reg) =3D=3D state), + 10, 10000); + + if (ret) + dev_err(google->dev, "failed to set PMU state %d\n", state); + + return ret; +} + +/* + * Clear pme interrupts and report their status. + * The hardware requires write-1 then write-0 sequence to clear the interr= upt bits. + */ +static u32 dwc3_google_clear_pme_irqs(struct dwc3_google *google) +{ + u32 irq_status, reg_set, reg_clear; + + irq_status =3D readl(google->usbint_base + USBINT_STATUS_OFFSET); + irq_status &=3D (USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW | + USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW); + if (!irq_status) + return irq_status; + + reg_set =3D readl(google->usbint_base + USBINT_CFG1_OFFSET); + reg_clear =3D reg_set; + if (irq_status & USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW) { + reg_set |=3D USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR; + reg_clear &=3D ~USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR; + } + if (irq_status & USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW) { + reg_set |=3D USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR; + reg_clear &=3D ~USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR; + } + + writel(reg_set, google->usbint_base + USBINT_CFG1_OFFSET); + writel(reg_clear, google->usbint_base + USBINT_CFG1_OFFSET); + + return irq_status; +} + +static void dwc3_google_enable_pme_irq(struct dwc3_google *google) +{ + u32 reg; + + reg =3D readl(google->usbint_base + USBINT_CFG1_OFFSET); + reg &=3D ~(USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK | + USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK); + reg |=3D (USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN | + USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN); + writel(reg, google->usbint_base + USBINT_CFG1_OFFSET); + + enable_irq(google->hs_pme_irq); + enable_irq(google->ss_pme_irq); + enable_irq_wake(google->hs_pme_irq); + enable_irq_wake(google->ss_pme_irq); +} + +static void dwc3_google_disable_pme_irq(struct dwc3_google *google) +{ + u32 reg; + + reg =3D readl(google->usbint_base + USBINT_CFG1_OFFSET); + reg &=3D ~(USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN | + USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN); + reg |=3D (USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK | + USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK); + writel(reg, google->usbint_base + USBINT_CFG1_OFFSET); + + disable_irq_wake(google->hs_pme_irq); + disable_irq_wake(google->ss_pme_irq); + disable_irq_nosync(google->hs_pme_irq); + disable_irq_nosync(google->ss_pme_irq); +} + +static irqreturn_t dwc3_google_resume_irq(int irq, void *data) +{ + struct dwc3_google *google =3D data; + struct dwc3 *dwc =3D &google->dwc; + u32 irq_status, dr_role; + + irq_status =3D dwc3_google_clear_pme_irqs(google); + dr_role =3D dwc->current_dr_role; + + if (!irq_status || !google->is_hibernation || + dr_role !=3D DWC3_GCTL_PRTCAP_HOST) { + dev_warn(google->dev, "spurious pme irq %d, hibernation %d, dr_role %u\n= ", + irq, google->is_hibernation, dr_role); + return IRQ_HANDLED; + } + + if (dwc->xhci) + pm_runtime_resume(&dwc->xhci->dev); + + return IRQ_HANDLED; +} + +static int dwc3_google_request_irq(struct dwc3_google *google, struct plat= form_device *pdev, + const char *irq_name, const char *req_name) +{ + int ret; + int irq; + + irq =3D platform_get_irq_byname(pdev, irq_name); + if (irq < 0) { + dev_err(google->dev, "invalid irq name %s\n", irq_name); + return irq; + } + + irq_set_status_flags(irq, IRQ_NOAUTOEN); + ret =3D devm_request_threaded_irq(google->dev, irq, NULL, + dwc3_google_resume_irq, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + req_name, google); + if (ret < 0) { + dev_err(google->dev, "failed to request irq %s\n", req_name); + return ret; + } + + return irq; +} + +static int dwc3_google_usb_psw_pd_notifier(struct notifier_block *nb, unsi= gned long action, void *d) +{ + struct dwc3_google *google =3D container_of(nb, struct dwc3_google, usb_p= sw_pd_nb); + int ret; + + if (!google->is_hibernation) + return NOTIFY_OK; + + if (action =3D=3D GENPD_NOTIFY_OFF) { + dev_dbg(google->dev, "enter D3 power state\n"); + dwc3_google_set_pmu_state(google, HOST_CFG1_PM_POWER_STATE_D3); + ret =3D reset_control_assert(google->usbc_non_sticky_rst); + if (ret) + dev_err(google->dev, "non sticky reset assert failed: %d\n", ret); + } else if (action =3D=3D GENPD_NOTIFY_ON) { + dev_dbg(google->dev, "enter D0 power state\n"); + dwc3_google_clear_pme_irqs(google); + ret =3D reset_control_deassert(google->usbc_non_sticky_rst); + if (ret) + dev_err(google->dev, "non sticky reset deassert failed: %d\n", ret); + dwc3_google_set_pmu_state(google, HOST_CFG1_PM_POWER_STATE_D0); + } + + return NOTIFY_OK; +} + +static void dwc3_google_pm_domain_deinit(struct dwc3_google *google) +{ + if (google->usb_top_pd_dl) + device_link_del(google->usb_top_pd_dl); + + if (!IS_ERR_OR_NULL(google->usb_top_pd)) { + device_set_wakeup_capable(google->usb_top_pd, false); + dev_pm_domain_detach(google->usb_top_pd, true); + } + + if (google->usb_psw_pd_dl) + device_link_del(google->usb_psw_pd_dl); + + if (!IS_ERR_OR_NULL(google->usb_psw_pd)) { + dev_pm_genpd_remove_notifier(google->usb_psw_pd); + dev_pm_domain_detach(google->usb_psw_pd, true); + } +} + +static int dwc3_google_pm_domain_init(struct dwc3_google *google) +{ + int ret; + + /* + * Establish PM RUNTIME link between dwc dev and its power domain usb_psw= _pd, + * register notifier block to handle hibernation. + */ + google->usb_psw_pd =3D dev_pm_domain_attach_by_name(google->dev, "usb_psw= _pd"); + if (IS_ERR_OR_NULL(google->usb_psw_pd)) { + dev_err(google->dev, "failed to get usb psw pd"); + ret =3D google->usb_psw_pd ? PTR_ERR(google->usb_psw_pd) : -ENODATA; + return ret; + } + + google->usb_psw_pd_nb.notifier_call =3D dwc3_google_usb_psw_pd_notifier; + ret =3D dev_pm_genpd_add_notifier(google->usb_psw_pd, &google->usb_psw_pd= _nb); + if (ret) { + dev_err(google->dev, "failed to add usb psw pd notifier"); + goto err; + } + + google->usb_psw_pd_dl =3D device_link_add(google->dev, google->usb_psw_pd, + DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (!google->usb_psw_pd_dl) { + dev_err(google->usb_psw_pd, "failed to add device link"); + ret =3D -ENODEV; + goto err; + } + + /* + * usb_top_pd is the parent power domain of usb_psw_pd. Keeping usb_top_p= d on + * while usb_psw_pd is off places the controller in a power-gated state, + * essential for hibernation. Acquire a handle to usb_top_pd and sets it = as + * wakeup-capable to allow the domain to be left on during system suspend. + */ + google->usb_top_pd =3D dev_pm_domain_attach_by_name(google->dev, "usb_top= _pd"); + if (IS_ERR_OR_NULL(google->usb_top_pd)) { + dev_err(google->dev, "failed to get usb top pd"); + ret =3D google->usb_top_pd ? PTR_ERR(google->usb_top_pd) : -ENODATA; + goto err; + } + device_set_wakeup_capable(google->usb_top_pd, true); + + google->usb_top_pd_dl =3D device_link_add(google->dev, google->usb_top_pd, + DL_FLAG_STATELESS); + if (!google->usb_top_pd_dl) { + dev_err(google->usb_top_pd, "failed to add device link"); + ret =3D -ENODEV; + goto err; + } + + return 0; + +err: + dwc3_google_pm_domain_deinit(google); + + return ret; +} + +static int dwc3_google_probe(struct platform_device *pdev) +{ + struct dwc3_probe_data probe_data =3D {}; + struct device *dev =3D &pdev->dev; + struct dwc3_google *google; + struct resource *res; + int ret; + + google =3D devm_kzalloc(&pdev->dev, sizeof(*google), GFP_KERNEL); + if (!google) + return -ENOMEM; + + google->dev =3D &pdev->dev; + + ret =3D dwc3_google_pm_domain_init(google); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "failed to init pdom\n"); + + ret =3D devm_clk_bulk_get_all_enabled(dev, &google->clks); + if (ret < 0) { + ret =3D dev_err_probe(&pdev->dev, ret, "failed to get and enable clks\n"= ); + goto err_deinit_pdom; + } + google->num_clks =3D ret; + + ret =3D dwc3_google_rst_init(google); + if (ret) { + ret =3D dev_err_probe(&pdev->dev, ret, "failed to get resets\n"); + goto err_deinit_pdom; + } + + ret =3D reset_control_bulk_deassert(google->num_rsts, google->rsts); + if (ret) { + ret =3D dev_err_probe(&pdev->dev, ret, "failed to deassert rsts\n"); + goto err_deinit_pdom; + } + + ret =3D dwc3_google_request_irq(google, pdev, "hs_pme_irq", "USB HS wakeu= p"); + if (ret < 0) { + ret =3D dev_err_probe(&pdev->dev, ret, "failed to request hs pme irq"); + goto err_reset_assert; + } + google->hs_pme_irq =3D ret; + + ret =3D dwc3_google_request_irq(google, pdev, "ss_pme_irq", "USB SS wakeu= p"); + if (ret < 0) { + ret =3D dev_err_probe(&pdev->dev, ret, "failed to request ss pme irq"); + goto err_reset_assert; + } + google->ss_pme_irq =3D ret; + + google->host_cfg_base =3D + devm_platform_ioremap_resource_byname(pdev, "host_cfg_csr"); + if (IS_ERR(google->host_cfg_base)) { + ret =3D dev_err_probe(&pdev->dev, PTR_ERR(google->host_cfg_base), + "invalid host cfg csr\n"); + goto err_reset_assert; + } + + google->usbint_base =3D + devm_platform_ioremap_resource_byname(pdev, "usbint_csr"); + if (IS_ERR(google->usbint_base)) { + ret =3D dev_err_probe(&pdev->dev, PTR_ERR(google->usbint_base), + "invalid usbint csr\n"); + goto err_reset_assert; + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "dwc3_core"); + if (!res) { + ret =3D dev_err_probe(dev, -ENODEV, "invalid dwc3 core memory\n"); + goto err_reset_assert; + } + + device_init_wakeup(dev, true); + + google->dwc.dev =3D dev; + probe_data.dwc =3D &google->dwc; + probe_data.res =3D res; + probe_data.ignore_clocks_and_resets =3D true; + ret =3D dwc3_core_probe(&probe_data); + if (ret) { + ret =3D dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); + goto err_reset_assert; + } + + return 0; + +err_reset_assert: + reset_control_bulk_assert(google->num_rsts, google->rsts); + +err_deinit_pdom: + dwc3_google_pm_domain_deinit(google); + + return ret; +} + +static void dwc3_google_remove(struct platform_device *pdev) +{ + struct dwc3 *dwc =3D platform_get_drvdata(pdev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + + dwc3_core_remove(&google->dwc); + + reset_control_bulk_assert(google->num_rsts, google->rsts); + + dwc3_google_pm_domain_deinit(google); +} + +static int dwc3_google_suspend(struct dwc3_google *google, pm_message_t ms= g) +{ + if (pm_runtime_suspended(google->dev)) + return 0; + + if (google->dwc.current_dr_role =3D=3D DWC3_GCTL_PRTCAP_HOST) { + /* + * Follow dwc3_suspend_common() guidelines for deciding between + * a full teardown and hibernation. + */ + if (PMSG_IS_AUTO(msg) || device_may_wakeup(google->dev)) { + dev_dbg(google->dev, "enter hibernation"); + pm_runtime_get_sync(google->usb_top_pd); + device_wakeup_enable(google->usb_top_pd); + dwc3_google_enable_pme_irq(google); + google->is_hibernation =3D true; + return 0; + } + } + + reset_control_bulk_assert(google->num_rsts, google->rsts); + clk_bulk_disable_unprepare(google->num_clks, google->clks); + + return 0; +} + +static int dwc3_google_resume(struct dwc3_google *google, pm_message_t msg) +{ + int ret; + + if (google->is_hibernation) { + dev_dbg(google->dev, "exit hibernation"); + dwc3_google_disable_pme_irq(google); + device_wakeup_disable(google->usb_top_pd); + pm_runtime_put_sync(google->usb_top_pd); + google->is_hibernation =3D false; + return 0; + } + + ret =3D clk_bulk_prepare_enable(google->num_clks, google->clks); + if (ret) + return ret; + + ret =3D reset_control_bulk_deassert(google->num_rsts, google->rsts); + if (ret) { + clk_bulk_disable_unprepare(google->num_clks, google->clks); + return ret; + } + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int dwc3_google_pm_suspend(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + int ret; + + ret =3D dwc3_pm_suspend(&google->dwc); + if (ret) + return ret; + + return dwc3_google_suspend(google, PMSG_SUSPEND); +} + +static int dwc3_google_pm_resume(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + int ret; + + ret =3D dwc3_google_resume(google, PMSG_RESUME); + if (ret) + return ret; + + return dwc3_pm_resume(&google->dwc); +} + +static void dwc3_google_complete(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + + dwc3_pm_complete(dwc); +} + +static int dwc3_google_prepare(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + + return dwc3_pm_prepare(dwc); +} +#else +#define dwc3_google_complete NULL +#define dwc3_google_prepare NULL +#endif /* CONFIG_PM_SLEEP */ + +#ifdef CONFIG_PM +static int dwc3_google_runtime_suspend(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + int ret; + + ret =3D dwc3_runtime_suspend(&google->dwc); + if (ret) + return ret; + + return dwc3_google_suspend(google, PMSG_AUTO_SUSPEND); +} + +static int dwc3_google_runtime_resume(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + int ret; + + ret =3D dwc3_google_resume(google, PMSG_AUTO_RESUME); + if (ret) + return ret; + + return dwc3_runtime_resume(&google->dwc); +} + +static int dwc3_google_runtime_idle(struct device *dev) +{ + return dwc3_runtime_idle(dev_get_drvdata(dev)); +} +#endif /* CONFIG_PM */ + +static const struct dev_pm_ops dwc3_google_dev_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(dwc3_google_pm_suspend, dwc3_google_pm_resume) + SET_RUNTIME_PM_OPS(dwc3_google_runtime_suspend, dwc3_google_runtime_resum= e, + dwc3_google_runtime_idle) + .complete =3D dwc3_google_complete, + .prepare =3D dwc3_google_prepare, +}; + +static const struct of_device_id dwc3_google_of_match[] =3D { + { .compatible =3D "google,gs5-dwc3" }, + { } +}; +MODULE_DEVICE_TABLE(of, dwc3_google_of_match); + +static struct platform_driver dwc3_google_driver =3D { + .probe =3D dwc3_google_probe, + .remove =3D dwc3_google_remove, + .driver =3D { + .name =3D "google-dwc3", + .pm =3D &dwc3_google_dev_pm_ops, + .of_match_table =3D dwc3_google_of_match, + }, +}; + +module_platform_driver(dwc3_google_driver); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("DesignWare DWC3 Google Glue Driver"); --=20 2.51.0.710.ga91ca5db03-goog