From nobody Mon Feb 9 08:15:54 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EFFF2EC559 for ; Wed, 8 Oct 2025 09:38:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759916333; cv=none; b=E4yBG9DeFww62fGiI76lV9T71HVCVMQFtxBKuKFEGJW73E1RGkZAXhtTEMH50RDaRpELyuI9hWC8ggcj/MkOXZPDRypyzqPfGB5ZtS7uqT5hG3g80zlfSW88RZOE9lFDzgb5pyOvaHr7NAnERvaEi84BoPH2hXRpbtGtsklqxc8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759916333; c=relaxed/simple; bh=xfEzirY/nt1DJN1CvcO4+exFhSIFPVcVcgxgsPcUUrc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=dm0SQCJxyw0njCwjs0M+0YdxGPl3DzjaWZTQ/TkP0I2tAQ0NOhKu1vcAQXuGQNmON4jw4LjYiNKBi1Um1F6J9KAo820tj3lZG2GuwMrcT/dwx65IuNkNovf9Z+bVjmzJXKg2/zwLR3EW28Ht07CyuuLrGhqWFxUWZkxPIPekiNA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1v6Qd8-0004Hl-17; Wed, 08 Oct 2025 11:38:42 +0200 Received: from moin.white.stw.pengutronix.de ([2a0a:edc0:0:b01:1d::7b] helo=bjornoya.blackshift.org) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1v6Qd6-002XwW-2O; Wed, 08 Oct 2025 11:38:40 +0200 Received: from hardanger.blackshift.org (p54b152ce.dip0.t-ipconnect.de [84.177.82.206]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) (Authenticated sender: mkl-all@blackshift.org) by smtp.blackshift.org (Postfix) with ESMTPSA id 7302A481D72; Wed, 08 Oct 2025 09:38:40 +0000 (UTC) From: Marc Kleine-Budde Date: Wed, 08 Oct 2025 11:38:30 +0200 Subject: [PATCH can-next] can: m_can: add support for optional reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251008-m_can-add-reset-v1-1-49f0bbf820c4@pengutronix.de> X-B4-Tracking: v=1; b=H4sIABUx5mgC/x2MQQqAMAzAviI9W+gUQfyKiHRb1R6csokI4t+dH gNJbkgSVRJ0xQ1RTk26hQymLMAtHGZB9ZmhoqoxRC2uo+OA7D1GSXIgT4bYkqtbtpCrPcqk13/ s4VODXAcMz/MC61XgcWsAAAA= X-Change-ID: 20251008-m_can-add-reset-af10ab0c38ab To: Chandrasekar Ramakrishnan , Vincent Mailhol , Philipp Zabel Cc: linux-can@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, Markus Schneider-Pargmann , Marc Kleine-Budde X-Mailer: b4 0.15-dev-b87af X-Developer-Signature: v=1; a=openpgp-sha256; l=4086; i=mkl@pengutronix.de; h=from:subject:message-id; bh=xfEzirY/nt1DJN1CvcO4+exFhSIFPVcVcgxgsPcUUrc=; b=owEBbQGS/pANAwAKAQx0Zd/5kJGcAcsmYgBo5jEdXsAQZgtVSn/CpYcb8dLxhrRo27mRHg1rP tzFee5m1aKJATMEAAEKAB0WIQSf+wzYr2eoX/wVbPMMdGXf+ZCRnAUCaOYxHQAKCRAMdGXf+ZCR nHCFB/9Povbb0Hd0ZpB/fx3g4c5Y9IlBKv73OWLXqZ6uXPBiLMep0kX9GgpykZG+Cvi0yNZzyc+ AknKIm0b9SK/d/LcVsD7vjabaOAD6BeGo1CrYv2uj7tfkH8y7jH6xpdt2y/L0qvyb55KVAcwEfI DfUqOUYBC0suetmY/ji030owr+hH6lOk7ioJpAG7a/r56YI4niPVxeqfrHzWbTKLuWpLqPGC/Mi byl1fJwYavpbS0fGjreCt9OYhu0uKVx3cr9ja28BJ/GzTSaxjSk2JiiZdHahniJwLBrxSyyYEKZ BkEk/NSPvSPq7aDfFTjd8UxjPdbSzKGytm6REKMoymRNwG/Q X-Developer-Key: i=mkl@pengutronix.de; a=openpgp; fpr=C1400BA0B3989E6FBC7D5B5C2B5EE211C58AEA54 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: mkl@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org This patch has been split from the original series [1]. In some SoCs (observed on the STM32MP15) the M_CAN IP core keeps the CAN state and CAN error counters over an internal reset cycle. The STM32MP15 SoC provides an external reset, which is shared between both M_CAN cores. Add support for an optional external reset. Take care of shared resets, de-assert reset during the probe phase in m_can_class_register() and while the interface is up, assert the reset otherwise. [1] https://lore.kernel.org/all/20250923-m_can-fix-state-handling-v3-0-06d8= baccadbf@pengutronix.de Reviewed-by: Philipp Zabel Reviewed-by: Markus Schneider-Pargmann Signed-off-by: Marc Kleine-Budde --- drivers/net/can/m_can/m_can.c | 27 ++++++++++++++++++++++++--- drivers/net/can/m_can/m_can.h | 1 + 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index e1d725979685..520e079d2bd4 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -23,6 +23,7 @@ #include #include #include +#include =20 #include "m_can.h" =20 @@ -1816,6 +1817,7 @@ static int m_can_close(struct net_device *dev) =20 close_candev(dev); =20 + reset_control_assert(cdev->rst); m_can_clk_stop(cdev); phy_power_off(cdev->transceiver); =20 @@ -2058,11 +2060,15 @@ static int m_can_open(struct net_device *dev) if (err) goto out_phy_power_off; =20 + err =3D reset_control_deassert(cdev->rst); + if (err) + goto exit_disable_clks; + /* open the can device */ err =3D open_candev(dev); if (err) { netdev_err(dev, "failed to open can device\n"); - goto exit_disable_clks; + goto out_reset_control_assert; } =20 if (cdev->is_peripheral) @@ -2118,6 +2124,8 @@ static int m_can_open(struct net_device *dev) else napi_disable(&cdev->napi); close_candev(dev); +out_reset_control_assert: + reset_control_assert(cdev->rst); exit_disable_clks: m_can_clk_stop(cdev); out_phy_power_off: @@ -2406,15 +2414,24 @@ int m_can_class_register(struct m_can_classdev *cde= v) } } =20 + cdev->rst =3D devm_reset_control_get_optional_shared(cdev->dev, NULL); + if (IS_ERR(cdev->rst)) + return dev_err_probe(cdev->dev, PTR_ERR(cdev->rst), + "Failed to get reset line\n"); + ret =3D m_can_clk_start(cdev); if (ret) return ret; =20 + ret =3D reset_control_deassert(cdev->rst); + if (ret) + goto clk_disable; + if (cdev->is_peripheral) { ret =3D can_rx_offload_add_manual(cdev->net, &cdev->offload, NAPI_POLL_WEIGHT); if (ret) - goto clk_disable; + goto out_reset_control_assert; } =20 if (!cdev->net->irq) { @@ -2443,8 +2460,10 @@ int m_can_class_register(struct m_can_classdev *cdev) KBUILD_MODNAME, cdev->net->irq, cdev->version); =20 /* Probe finished - * Stop clocks. They will be reactivated once the M_CAN device is opened + * Assert reset and stop clocks. + * They will be reactivated once the M_CAN device is opened */ + reset_control_assert(cdev->rst); m_can_clk_stop(cdev); =20 return 0; @@ -2452,6 +2471,8 @@ int m_can_class_register(struct m_can_classdev *cdev) rx_offload_del: if (cdev->is_peripheral) can_rx_offload_del(&cdev->offload); +out_reset_control_assert: + reset_control_assert(cdev->rst); clk_disable: m_can_clk_stop(cdev); =20 diff --git a/drivers/net/can/m_can/m_can.h b/drivers/net/can/m_can/m_can.h index bd4746c63af3..7b7600697c6b 100644 --- a/drivers/net/can/m_can/m_can.h +++ b/drivers/net/can/m_can/m_can.h @@ -86,6 +86,7 @@ struct m_can_classdev { struct device *dev; struct clk *hclk; struct clk *cclk; + struct reset_control *rst; =20 struct workqueue_struct *tx_wq; struct phy *transceiver; --- base-commit: 07fdad3a93756b872da7b53647715c48d0f4a2d0 change-id: 20251008-m_can-add-reset-af10ab0c38ab Best regards, -- =20 Marc Kleine-Budde