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Signed-off-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Reviewed-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_ctrls.c | 2 +- drivers/media/platform/qcom/iris/iris_platform_common.h | 4 ++-- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 4 ++-- drivers/media/platform/qcom/iris/iris_platform_qcs8300.h | 4 ++-- drivers/media/platform/qcom/iris/iris_platform_sm8250.c | 4 ++-- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 754a5ad718bc37630bb861012301df7a2e7342a1..9da050aa1f7ce8152dfa46a706e= 2c27adfb5d6ce 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -301,7 +301,7 @@ int iris_ctrls_init(struct iris_inst *inst) =20 void iris_session_init_caps(struct iris_core *core) { - struct platform_inst_fw_cap *caps; + const struct platform_inst_fw_cap *caps; u32 i, num_cap, cap_id; =20 caps =3D core->iris_platform_data->inst_fw_caps_dec; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 58d05e0a112eed25faea027a34c719c89d6c3897..17ed86bf78bb3b0bc3f0862253f= ba6505ac3d164 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -215,9 +215,9 @@ struct iris_platform_data { const char *fwname; u32 pas_id; struct platform_inst_caps *inst_caps; - struct platform_inst_fw_cap *inst_fw_caps_dec; + const struct platform_inst_fw_cap *inst_fw_caps_dec; u32 inst_fw_caps_dec_size; - struct platform_inst_fw_cap *inst_fw_caps_enc; + const struct platform_inst_fw_cap *inst_fw_caps_enc; u32 inst_fw_caps_enc_size; struct tz_cp_config *tz_cp_config_data; u32 core_arch; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 36d69cc73986b74534a2912524c8553970fd862e..cbf38e13f89e5c4c46e759fbb86= 777854d751552 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -19,7 +19,7 @@ #define VIDEO_ARCH_LX 1 #define BITRATE_MAX 245000000 =20 -static struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] =3D { +static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] =3D { { .cap_id =3D PROFILE_H264, .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, @@ -203,7 +203,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_d= ec[] =3D { }, }; =20 -static struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] =3D { +static const struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] =3D { { .cap_id =3D PROFILE_H264, .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/dri= vers/media/platform/qcom/iris/iris_platform_qcs8300.h index 35ea0efade73caa687d300779c5b1dc3b17a0128..87517361a1cf4b6fe53b8a14831= 88670df52c7e7 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h +++ b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h @@ -5,7 +5,7 @@ =20 #define BITRATE_MAX 245000000 =20 -static struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] =3D { +static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] =3D { { .cap_id =3D PROFILE_H264, .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, @@ -189,7 +189,7 @@ static struct platform_inst_fw_cap inst_fw_cap_qcs8300_= dec[] =3D { }, }; =20 -static struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] =3D { +static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] =3D { { .cap_id =3D PROFILE_H264, .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 16486284f8acccf6a95a27f6003e885226e28f4d..e29cba993fde922b579eb7e5a59= ae34bb46f9f0f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -17,7 +17,7 @@ #define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2) #define BITRATE_STEP 100 =20 -static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { +static const struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { { .cap_id =3D PIPE, .min =3D PIPE_1, @@ -38,7 +38,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec= [] =3D { }, }; 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Signed-off-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Reviewed-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/iris_platform_common.h | 10 +++++----- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 8 ++++---- drivers/media/platform/qcom/iris/iris_platform_sm8250.c | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 17ed86bf78bb3b0bc3f0862253fba6505ac3d164..5ffc1874e8c6362b1c650e912c2= 30e9c4e3bd160 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -41,11 +41,11 @@ enum pipe_type { PIPE_4 =3D 4, }; =20 -extern struct iris_platform_data qcs8300_data; -extern struct iris_platform_data sm8250_data; -extern struct iris_platform_data sm8550_data; -extern struct iris_platform_data sm8650_data; -extern struct iris_platform_data sm8750_data; +extern const struct iris_platform_data qcs8300_data; +extern const struct iris_platform_data sm8250_data; +extern const struct iris_platform_data sm8550_data; +extern const struct iris_platform_data sm8650_data; +extern const struct iris_platform_data sm8750_data; =20 enum platform_clk_type { IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index cbf38e13f89e5c4c46e759fbb86777854d751552..b444e816355624bca8248cce9da= 7adcd7caf6c5b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -737,7 +737,7 @@ static const u32 sm8550_enc_op_int_buf_tbl[] =3D { BUF_SCRATCH_2, }; =20 -struct iris_platform_data sm8550_data =3D { +const struct iris_platform_data sm8550_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, @@ -827,7 +827,7 @@ struct iris_platform_data sm8550_data =3D { * - controller_rst_tbl to sm8650_controller_reset_table * - fwname to "qcom/vpu/vpu33_p4.mbn" */ -struct iris_platform_data sm8650_data =3D { +const struct iris_platform_data sm8650_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, @@ -912,7 +912,7 @@ struct iris_platform_data sm8650_data =3D { .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 -struct iris_platform_data sm8750_data =3D { +const struct iris_platform_data sm8750_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, @@ -998,7 +998,7 @@ struct iris_platform_data sm8750_data =3D { * - inst_caps to platform_inst_cap_qcs8300 * - inst_fw_caps to inst_fw_cap_qcs8300 */ -struct iris_platform_data qcs8300_data =3D { +const struct iris_platform_data qcs8300_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index e29cba993fde922b579eb7e5a59ae34bb46f9f0f..66a5bdd24d8a0e98b0554a01943= 8bf4caa1dc43c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -314,7 +314,7 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] =3D { BUF_SCRATCH_2, }; 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In order to lower the amount of memory consumed by the driver, store the value and the corresponding indice in the read-write data and use the rest via the pointer to r/o capability data. Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_core.h | 4 +- drivers/media/platform/qcom/iris/iris_ctrls.c | 238 ++++++++++-------= ---- drivers/media/platform/qcom/iris/iris_instance.h | 3 +- .../platform/qcom/iris/iris_platform_common.h | 8 +- drivers/media/platform/qcom/iris/iris_vdec.c | 5 +- drivers/media/platform/qcom/iris/iris_venc.c | 5 +- 6 files changed, 135 insertions(+), 128 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index fb194c967ad4f9b5e00cd74f0d41e0b827ef14db..b5037ae8c71921753c165a86a27= 7a4a4b5083b30 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -115,8 +115,8 @@ struct iris_core { struct delayed_work sys_error_handler; struct list_head instances; /* encoder and decoder have overlapping caps, so two different arrays are= required */ - struct platform_inst_fw_cap inst_fw_caps_dec[INST_FW_CAP_MAX]; - struct platform_inst_fw_cap inst_fw_caps_enc[INST_FW_CAP_MAX]; + struct platform_inst_fw_cap_value inst_fw_caps_dec[INST_FW_CAP_MAX]; + struct platform_inst_fw_cap_value inst_fw_caps_enc[INST_FW_CAP_MAX]; }; =20 int iris_core_init(struct iris_core *core); diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 9da050aa1f7ce8152dfa46a706e2c27adfb5d6ce..0e9adb3982a49cfd7cbe5110cfd= 5f573f0f7bb38 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -194,26 +194,28 @@ static int iris_op_s_ctrl(struct v4l2_ctrl *ctrl) { struct iris_inst *inst =3D container_of(ctrl->handler, struct iris_inst, = ctrl_handler); enum platform_inst_fw_cap_type cap_id; - struct platform_inst_fw_cap *cap; + unsigned int cap_idx; struct vb2_queue *q; =20 - cap =3D &inst->fw_caps[0]; cap_id =3D iris_get_cap_id(ctrl->id); if (!iris_valid_cap_id(cap_id)) return -EINVAL; =20 + cap_idx =3D inst->fw_caps[cap_id].idx; + q =3D v4l2_m2m_get_src_vq(inst->m2m_ctx); if (vb2_is_streaming(q) && - (!(inst->fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED))) + (!(inst->inst_fw_caps[cap_id].flags & CAP_FLAG_DYNAMIC_ALLOWED))) return -EINVAL; =20 - cap[cap_id].flags |=3D CAP_FLAG_CLIENT_SET; + inst->fw_caps[cap_id].client_set =3D true; =20 inst->fw_caps[cap_id].value =3D ctrl->val; =20 if (vb2_is_streaming(q)) { - if (cap[cap_id].set) - cap[cap_id].set(inst, cap_id); + + if (inst->inst_fw_caps[cap_idx].set) + inst->inst_fw_caps[cap_idx].set(inst, cap_id); } =20 return 0; @@ -225,13 +227,14 @@ static const struct v4l2_ctrl_ops iris_ctrl_ops =3D { =20 int iris_ctrls_init(struct iris_inst *inst) { - struct platform_inst_fw_cap *cap =3D &inst->fw_caps[0]; u32 num_ctrls =3D 0, ctrl_idx =3D 0, idx =3D 0; u32 v4l2_id; int ret; =20 for (idx =3D 1; idx < INST_FW_CAP_MAX; idx++) { - if (iris_get_v4l2_id(cap[idx].cap_id)) + unsigned int cap_idx =3D inst->fw_caps[idx].idx; + + if (iris_get_v4l2_id(inst->inst_fw_caps[cap_idx].cap_id)) num_ctrls++; } =20 @@ -245,9 +248,11 @@ int iris_ctrls_init(struct iris_inst *inst) return ret; =20 for (idx =3D 1; idx < INST_FW_CAP_MAX; idx++) { + unsigned int cap_idx =3D inst->fw_caps[idx].idx; + const struct platform_inst_fw_cap *cap =3D &inst->inst_fw_caps[cap_idx]; struct v4l2_ctrl *ctrl; =20 - v4l2_id =3D iris_get_v4l2_id(cap[idx].cap_id); + v4l2_id =3D iris_get_v4l2_id(cap->cap_id); if (!v4l2_id) continue; =20 @@ -256,21 +261,21 @@ int iris_ctrls_init(struct iris_inst *inst) goto error; } =20 - if (cap[idx].flags & CAP_FLAG_MENU) { + if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_MENU) { ctrl =3D v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &iris_ctrl_ops, v4l2_id, - cap[idx].max, - ~(cap[idx].step_or_mask), - cap[idx].value); + cap[cap_idx].max, + ~(cap[cap_idx].step_or_mask), + inst->fw_caps[idx].value); } else { ctrl =3D v4l2_ctrl_new_std(&inst->ctrl_handler, &iris_ctrl_ops, v4l2_id, - cap[idx].min, - cap[idx].max, - cap[idx].step_or_mask, - cap[idx].value); + cap[cap_idx].min, + cap[cap_idx].max, + cap[cap_idx].step_or_mask, + inst->fw_caps[idx].value); } if (!ctrl) { ret =3D -EINVAL; @@ -312,14 +317,8 @@ void iris_session_init_caps(struct iris_core *core) if (!iris_valid_cap_id(cap_id)) continue; =20 - core->inst_fw_caps_dec[cap_id].cap_id =3D caps[i].cap_id; - core->inst_fw_caps_dec[cap_id].min =3D caps[i].min; - core->inst_fw_caps_dec[cap_id].max =3D caps[i].max; - core->inst_fw_caps_dec[cap_id].step_or_mask =3D caps[i].step_or_mask; + core->inst_fw_caps_dec[cap_id].idx =3D i; core->inst_fw_caps_dec[cap_id].value =3D caps[i].value; - core->inst_fw_caps_dec[cap_id].flags =3D caps[i].flags; - core->inst_fw_caps_dec[cap_id].hfi_id =3D caps[i].hfi_id; - core->inst_fw_caps_dec[cap_id].set =3D caps[i].set; } =20 caps =3D core->iris_platform_data->inst_fw_caps_enc; @@ -330,29 +329,23 @@ void iris_session_init_caps(struct iris_core *core) if (!iris_valid_cap_id(cap_id)) continue; =20 - core->inst_fw_caps_enc[cap_id].cap_id =3D caps[i].cap_id; - core->inst_fw_caps_enc[cap_id].min =3D caps[i].min; - core->inst_fw_caps_enc[cap_id].max =3D caps[i].max; - core->inst_fw_caps_enc[cap_id].step_or_mask =3D caps[i].step_or_mask; + core->inst_fw_caps_enc[cap_id].idx =3D i; core->inst_fw_caps_enc[cap_id].value =3D caps[i].value; - core->inst_fw_caps_enc[cap_id].flags =3D caps[i].flags; - core->inst_fw_caps_enc[cap_id].hfi_id =3D caps[i].hfi_id; - core->inst_fw_caps_enc[cap_id].set =3D caps[i].set; } } =20 static u32 iris_get_port_info(struct iris_inst *inst, - enum platform_inst_fw_cap_type cap_id) + unsigned int cap_idx) { if (inst->domain =3D=3D DECODER) { - if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) + if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_INPUT_PORT) return HFI_PORT_BITSTREAM; - else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) + else if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_OUTPUT_PORT) return HFI_PORT_RAW; } else { - if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) + if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_INPUT_PORT) return HFI_PORT_RAW; - else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) + else if (inst->inst_fw_caps[cap_idx].flags & CAP_FLAG_OUTPUT_PORT) return HFI_PORT_BITSTREAM; } =20 @@ -362,12 +355,13 @@ static u32 iris_get_port_info(struct iris_inst *inst, int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id) { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; u32 hfi_value =3D inst->fw_caps[cap_id].value; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32_ENUM, &hfi_value, sizeof(u32)); } @@ -375,12 +369,13 @@ int iris_set_u32_enum(struct iris_inst *inst, enum pl= atform_inst_fw_cap_type cap int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type ca= p_id) { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; u32 hfi_value =3D inst->fw_caps[cap_id].value; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32, &hfi_value, sizeof(u32)); } @@ -389,7 +384,8 @@ int iris_set_stage(struct iris_inst *inst, enum platfor= m_inst_fw_cap_type cap_id { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; struct v4l2_format *inp_f =3D inst->fmt_src; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; u32 height =3D inp_f->fmt.pix_mp.height; u32 width =3D inp_f->fmt.pix_mp.width; u32 work_mode =3D STAGE_2; @@ -401,7 +397,7 @@ int iris_set_stage(struct iris_inst *inst, enum platfor= m_inst_fw_cap_type cap_id =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32, &work_mode, sizeof(u32)); } @@ -409,12 +405,13 @@ int iris_set_stage(struct iris_inst *inst, enum platf= orm_inst_fw_cap_type cap_id int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type c= ap_id) { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; u32 work_route =3D inst->fw_caps[PIPE].value; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32, &work_route, sizeof(u32)); } @@ -422,19 +419,13 @@ int iris_set_pipe(struct iris_inst *inst, enum platfo= rm_inst_fw_cap_type cap_id) int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_typ= e cap_id) { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; - u32 hfi_id, hfi_value; - - if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { - hfi_id =3D inst->fw_caps[PROFILE_H264].hfi_id; - hfi_value =3D inst->fw_caps[PROFILE_H264].value; - } else { - hfi_id =3D inst->fw_caps[PROFILE_HEVC].hfi_id; - hfi_value =3D inst->fw_caps[PROFILE_HEVC].value; - } + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; + u32 hfi_value =3D inst->fw_caps[cap_id].value; =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32_ENUM, &hfi_value, sizeof(u32)); } @@ -442,19 +433,13 @@ int iris_set_profile(struct iris_inst *inst, enum pla= tform_inst_fw_cap_type cap_ int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type = cap_id) { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; - u32 hfi_id, hfi_value; - - if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { - hfi_id =3D inst->fw_caps[LEVEL_H264].hfi_id; - hfi_value =3D inst->fw_caps[LEVEL_H264].value; - } else { - hfi_id =3D inst->fw_caps[LEVEL_HEVC].hfi_id; - hfi_value =3D inst->fw_caps[LEVEL_HEVC].value; - } + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; + u32 hfi_value =3D inst->fw_caps[cap_id].value; =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32_ENUM, &hfi_value, sizeof(u32)); } @@ -462,20 +447,19 @@ int iris_set_level(struct iris_inst *inst, enum platf= orm_inst_fw_cap_type cap_id int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst= _fw_cap_type cap_id) { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; struct hfi_profile_level pl; =20 - if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { - pl.profile =3D inst->fw_caps[PROFILE_H264].value; + pl.profile =3D inst->fw_caps[cap_id].value; + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) pl.level =3D inst->fw_caps[LEVEL_H264].value; - } else { - pl.profile =3D inst->fw_caps[PROFILE_HEVC].value; + else pl.level =3D inst->fw_caps[LEVEL_HEVC].value; - } =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32_ENUM, &pl, sizeof(u32)); } @@ -484,7 +468,8 @@ int iris_set_header_mode_gen1(struct iris_inst *inst, e= num platform_inst_fw_cap_ { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; u32 header_mode =3D inst->fw_caps[cap_id].value; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; u32 hfi_val; =20 if (header_mode =3D=3D V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) @@ -494,7 +479,7 @@ int iris_set_header_mode_gen1(struct iris_inst *inst, e= num platform_inst_fw_cap_ =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32, &hfi_val, sizeof(u32)); } @@ -504,7 +489,8 @@ int iris_set_header_mode_gen2(struct iris_inst *inst, e= num platform_inst_fw_cap_ const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; u32 prepend_sps_pps =3D inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value; u32 header_mode =3D inst->fw_caps[cap_id].value; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; u32 hfi_val; =20 if (prepend_sps_pps) @@ -516,7 +502,7 @@ int iris_set_header_mode_gen2(struct iris_inst *inst, e= num platform_inst_fw_cap_ =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32_ENUM, &hfi_val, sizeof(u32)); } @@ -526,7 +512,8 @@ int iris_set_bitrate(struct iris_inst *inst, enum platf= orm_inst_fw_cap_type cap_ const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; u32 entropy_mode =3D inst->fw_caps[ENTROPY_MODE].value; u32 bitrate =3D inst->fw_caps[cap_id].value; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; u32 max_bitrate; =20 if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) @@ -541,7 +528,7 @@ int iris_set_bitrate(struct iris_inst *inst, enum platf= orm_inst_fw_cap_type cap_ =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32, &bitrate, sizeof(u32)); } @@ -552,12 +539,13 @@ int iris_set_peak_bitrate(struct iris_inst *inst, enu= m platform_inst_fw_cap_type u32 rc_mode =3D inst->fw_caps[BITRATE_MODE].value; u32 peak_bitrate =3D inst->fw_caps[cap_id].value; u32 bitrate =3D inst->fw_caps[BITRATE].value; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; =20 if (rc_mode !=3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) return 0; =20 - if (inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) { + if (inst->fw_caps[cap_id].client_set) { if (peak_bitrate < bitrate) peak_bitrate =3D bitrate; } else { @@ -568,7 +556,7 @@ int iris_set_peak_bitrate(struct iris_inst *inst, enum = platform_inst_fw_cap_type =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32, &peak_bitrate, sizeof(u32)); } @@ -579,7 +567,8 @@ int iris_set_bitrate_mode_gen1(struct iris_inst *inst, = enum platform_inst_fw_cap u32 bitrate_mode =3D inst->fw_caps[BITRATE_MODE].value; u32 frame_rc =3D inst->fw_caps[FRAME_RC_ENABLE].value; u32 frame_skip =3D inst->fw_caps[FRAME_SKIP_MODE].value; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; u32 rc_mode =3D 0; =20 if (!frame_rc) @@ -595,7 +584,7 @@ int iris_set_bitrate_mode_gen1(struct iris_inst *inst, = enum platform_inst_fw_cap =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32_ENUM, &rc_mode, sizeof(u32)); } @@ -606,7 +595,8 @@ int iris_set_bitrate_mode_gen2(struct iris_inst *inst, = enum platform_inst_fw_cap u32 bitrate_mode =3D inst->fw_caps[BITRATE_MODE].value; u32 frame_rc =3D inst->fw_caps[FRAME_RC_ENABLE].value; u32 frame_skip =3D inst->fw_caps[FRAME_SKIP_MODE].value; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; u32 rc_mode =3D 0; =20 if (!frame_rc) @@ -622,7 +612,7 @@ int iris_set_bitrate_mode_gen2(struct iris_inst *inst, = enum platform_inst_fw_cap =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32_ENUM, &rc_mode, sizeof(u32)); } @@ -631,7 +621,8 @@ int iris_set_entropy_mode_gen1(struct iris_inst *inst, = enum platform_inst_fw_cap { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; u32 entropy_mode =3D inst->fw_caps[cap_id].value; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; u32 hfi_val; =20 if (inst->codec !=3D V4L2_PIX_FMT_H264) @@ -642,7 +633,7 @@ int iris_set_entropy_mode_gen1(struct iris_inst *inst, = enum platform_inst_fw_cap =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32, &hfi_val, sizeof(u32)); } @@ -651,7 +642,8 @@ int iris_set_entropy_mode_gen2(struct iris_inst *inst, = enum platform_inst_fw_cap { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; u32 entropy_mode =3D inst->fw_caps[cap_id].value; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; u32 profile; =20 if (inst->codec !=3D V4L2_PIX_FMT_H264) @@ -667,7 +659,7 @@ int iris_set_entropy_mode_gen2(struct iris_inst *inst, = enum platform_inst_fw_cap =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_U32, &entropy_mode, sizeof(u32)); } @@ -678,32 +670,33 @@ int iris_set_min_qp(struct iris_inst *inst, enum plat= form_inst_fw_cap_type cap_i u32 i_qp_enable =3D 0, p_qp_enable =3D 0, b_qp_enable =3D 0; u32 i_frame_qp =3D 0, p_frame_qp =3D 0, b_frame_qp =3D 0; u32 min_qp_enable =3D 0, client_qp_enable =3D 0; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; u32 hfi_val; =20 if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { - if (inst->fw_caps[MIN_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) + if (inst->fw_caps[MIN_FRAME_QP_H264].client_set) min_qp_enable =3D 1; if (min_qp_enable || - (inst->fw_caps[I_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) + (inst->fw_caps[I_FRAME_MIN_QP_H264].client_set)) i_qp_enable =3D 1; if (min_qp_enable || - (inst->fw_caps[P_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) + (inst->fw_caps[P_FRAME_MIN_QP_H264].client_set)) p_qp_enable =3D 1; if (min_qp_enable || - (inst->fw_caps[B_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) + (inst->fw_caps[B_FRAME_MIN_QP_H264].client_set)) b_qp_enable =3D 1; } else { - if (inst->fw_caps[MIN_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) + if (inst->fw_caps[MIN_FRAME_QP_HEVC].client_set) min_qp_enable =3D 1; if (min_qp_enable || - (inst->fw_caps[I_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) + (inst->fw_caps[I_FRAME_MIN_QP_HEVC].client_set)) i_qp_enable =3D 1; if (min_qp_enable || - (inst->fw_caps[P_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) + (inst->fw_caps[P_FRAME_MIN_QP_HEVC].client_set)) p_qp_enable =3D 1; if (min_qp_enable || - (inst->fw_caps[B_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) + (inst->fw_caps[B_FRAME_MIN_QP_HEVC].client_set)) b_qp_enable =3D 1; } =20 @@ -731,7 +724,7 @@ int iris_set_min_qp(struct iris_inst *inst, enum platfo= rm_inst_fw_cap_type cap_i =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_32_PACKED, &hfi_val, sizeof(u32)); } @@ -742,32 +735,33 @@ int iris_set_max_qp(struct iris_inst *inst, enum plat= form_inst_fw_cap_type cap_i u32 i_qp_enable =3D 0, p_qp_enable =3D 0, b_qp_enable =3D 0; u32 max_qp_enable =3D 0, client_qp_enable; u32 i_frame_qp, p_frame_qp, b_frame_qp; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; u32 hfi_val; =20 if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { - if (inst->fw_caps[MAX_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) + if (inst->fw_caps[MAX_FRAME_QP_H264].client_set) max_qp_enable =3D 1; if (max_qp_enable || - (inst->fw_caps[I_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) + (inst->fw_caps[I_FRAME_MAX_QP_H264].client_set)) i_qp_enable =3D 1; if (max_qp_enable || - (inst->fw_caps[P_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) + (inst->fw_caps[P_FRAME_MAX_QP_H264].client_set)) p_qp_enable =3D 1; if (max_qp_enable || - (inst->fw_caps[B_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) + (inst->fw_caps[B_FRAME_MAX_QP_H264].client_set)) b_qp_enable =3D 1; } else { - if (inst->fw_caps[MAX_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) + if (inst->fw_caps[MAX_FRAME_QP_HEVC].client_set) max_qp_enable =3D 1; if (max_qp_enable || - (inst->fw_caps[I_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) + (inst->fw_caps[I_FRAME_MAX_QP_HEVC].client_set)) i_qp_enable =3D 1; if (max_qp_enable || - (inst->fw_caps[P_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) + (inst->fw_caps[P_FRAME_MAX_QP_HEVC].client_set)) p_qp_enable =3D 1; if (max_qp_enable || - (inst->fw_caps[B_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) + (inst->fw_caps[B_FRAME_MAX_QP_HEVC].client_set)) b_qp_enable =3D 1; } =20 @@ -796,7 +790,7 @@ int iris_set_max_qp(struct iris_inst *inst, enum platfo= rm_inst_fw_cap_type cap_i =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_32_PACKED, &hfi_val, sizeof(u32)); } @@ -806,7 +800,8 @@ int iris_set_frame_qp(struct iris_inst *inst, enum plat= form_inst_fw_cap_type cap const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; u32 i_qp_enable =3D 0, p_qp_enable =3D 0, b_qp_enable =3D 0, client_qp_en= able; u32 i_frame_qp, p_frame_qp, b_frame_qp; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; struct vb2_queue *q; u32 hfi_val; =20 @@ -822,18 +817,18 @@ int iris_set_frame_qp(struct iris_inst *inst, enum pl= atform_inst_fw_cap_type cap b_qp_enable =3D 1; } else { if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { - if (inst->fw_caps[I_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) + if (inst->fw_caps[I_FRAME_QP_H264].client_set) i_qp_enable =3D 1; - if (inst->fw_caps[P_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) + if (inst->fw_caps[P_FRAME_QP_H264].client_set) p_qp_enable =3D 1; - if (inst->fw_caps[B_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) + if (inst->fw_caps[B_FRAME_QP_H264].client_set) b_qp_enable =3D 1; } else { - if (inst->fw_caps[I_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) + if (inst->fw_caps[I_FRAME_QP_HEVC].client_set) i_qp_enable =3D 1; - if (inst->fw_caps[P_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) + if (inst->fw_caps[P_FRAME_QP_HEVC].client_set) p_qp_enable =3D 1; - if (inst->fw_caps[B_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) + if (inst->fw_caps[B_FRAME_QP_HEVC].client_set) b_qp_enable =3D 1; } } @@ -857,7 +852,7 @@ int iris_set_frame_qp(struct iris_inst *inst, enum plat= form_inst_fw_cap_type cap =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_32_PACKED, &hfi_val, sizeof(u32)); } @@ -866,7 +861,8 @@ int iris_set_qp_range(struct iris_inst *inst, enum plat= form_inst_fw_cap_type cap { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; struct hfi_quantization_range_v2 range; - u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + unsigned int cap_idx =3D inst->fw_caps[cap_id].idx; + u32 hfi_id =3D inst->inst_fw_caps[cap_idx].hfi_id; =20 if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) { range.min_qp.qp_packed =3D inst->fw_caps[MIN_FRAME_QP_HEVC].value; @@ -878,7 +874,7 @@ int iris_set_qp_range(struct iris_inst *inst, enum plat= form_inst_fw_cap_type cap =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, - iris_get_port_info(inst, cap_id), + iris_get_port_info(inst, cap_idx), HFI_PAYLOAD_32_PACKED, &range, sizeof(range)); } @@ -886,7 +882,7 @@ int iris_set_qp_range(struct iris_inst *inst, enum plat= form_inst_fw_cap_type cap int iris_set_properties(struct iris_inst *inst, u32 plane) { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; - struct platform_inst_fw_cap *cap; + const struct platform_inst_fw_cap *cap; int ret; u32 i; =20 @@ -895,7 +891,9 @@ int iris_set_properties(struct iris_inst *inst, u32 pla= ne) return ret; =20 for (i =3D 1; i < INST_FW_CAP_MAX; i++) { - cap =3D &inst->fw_caps[i]; + unsigned int cap_idx =3D inst->fw_caps[i].idx; + + cap =3D &inst->inst_fw_caps[cap_idx]; if (!iris_valid_cap_id(cap->cap_id)) continue; =20 diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index 5982d7adefeab80905478b32cddba7bd4651a691..39d74bef4d188abb919c372b752= 9d1d0773bd96a 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -82,7 +82,8 @@ struct iris_inst { struct completion completion; struct completion flush_completion; u32 flush_responses_pending; - struct platform_inst_fw_cap fw_caps[INST_FW_CAP_MAX]; + struct platform_inst_fw_cap_value fw_caps[INST_FW_CAP_MAX]; + const struct platform_inst_fw_cap *inst_fw_caps; struct iris_buffers buffers[BUF_TYPE_MAX]; u32 fw_min_count; enum iris_inst_state state; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 5ffc1874e8c6362b1c650e912c230e9c4e3bd160..104ff38219e30e6d52476d44b54= 338c55ef2ca7b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -148,7 +148,7 @@ enum platform_inst_fw_cap_flags { CAP_FLAG_MENU =3D BIT(1), CAP_FLAG_INPUT_PORT =3D BIT(2), CAP_FLAG_OUTPUT_PORT =3D BIT(3), - CAP_FLAG_CLIENT_SET =3D BIT(4), + // BIT(4) CAP_FLAG_BITMASK =3D BIT(5), CAP_FLAG_VOLATILE =3D BIT(6), }; @@ -165,6 +165,12 @@ struct platform_inst_fw_cap { enum platform_inst_fw_cap_type cap_id); }; =20 +struct platform_inst_fw_cap_value { + unsigned int idx; + s64 value; + bool client_set; +}; + struct bw_info { u32 mbs_per_sec; u32 bw_ddr; diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index ae13c3e1b426bfd81a7b46dc6c3ff5eb5c4860cb..72559497e81c30373711e9b1135= 82039f1fb5153 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -55,8 +55,9 @@ int iris_vdec_inst_init(struct iris_inst *inst) inst->buffers[BUF_OUTPUT].min_count =3D iris_vpu_buf_count(inst, BUF_OUTP= UT); inst->buffers[BUF_OUTPUT].size =3D f->fmt.pix_mp.plane_fmt[0].sizeimage; =20 - memcpy(&inst->fw_caps[0], &core->inst_fw_caps_dec[0], - INST_FW_CAP_MAX * sizeof(struct platform_inst_fw_cap)); + memcpy(inst->fw_caps, core->inst_fw_caps_dec, + sizeof(inst->fw_caps)); + inst->inst_fw_caps =3D core->iris_platform_data->inst_fw_caps_dec; =20 return iris_ctrls_init(inst); } diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index 099bd5ed4ae0294725860305254c4cad1ec88d7e..3d1d481f8048305ef9a9bf0cb43= 5ebca68563105 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -68,8 +68,9 @@ int iris_venc_inst_init(struct iris_inst *inst) inst->operating_rate =3D DEFAULT_FPS; inst->frame_rate =3D DEFAULT_FPS; =20 - memcpy(&inst->fw_caps[0], &core->inst_fw_caps_enc[0], - INST_FW_CAP_MAX * sizeof(struct platform_inst_fw_cap)); + memcpy(inst->fw_caps, core->inst_fw_caps_enc, + sizeof(inst->fw_caps)); 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In order to reduce duplciation, use num_vpp_pipe from the iris_platform_data rather than hardcoding the value into the fw_cap. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/media/platform/qcom/iris/iris_ctrls.c | 6 +++++- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 4 ++-- drivers/media/platform/qcom/iris/iris_platform_qcs8300.h | 4 ++-- drivers/media/platform/qcom/iris/iris_platform_sm8250.c | 4 ++-- 4 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 0e9adb3982a49cfd7cbe5110cfd5f573f0f7bb38..8db3fa222bdb92a7ffff3dfe62d= 33f16c0550757 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -318,7 +318,11 @@ void iris_session_init_caps(struct iris_core *core) continue; =20 core->inst_fw_caps_dec[cap_id].idx =3D i; - core->inst_fw_caps_dec[cap_id].value =3D caps[i].value; + if (cap_id =3D=3D PIPE) + core->inst_fw_caps_dec[cap_id].value =3D + core->iris_platform_data->num_vpp_pipe; + else + core->inst_fw_caps_dec[cap_id].value =3D caps[i].value; } =20 caps =3D core->iris_platform_data->inst_fw_caps_enc; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index b444e816355624bca8248cce9da7adcd7caf6c5b..7ad03a800356ae9fb73bdbd6d09= 928d0b500cb3c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -161,9 +161,9 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm= 8550_dec[] =3D { { .cap_id =3D PIPE, .min =3D PIPE_1, - .max =3D PIPE_4, + /* .max is set via platform data */ .step_or_mask =3D 1, - .value =3D PIPE_4, + /* .value is set via platform data */ .hfi_id =3D HFI_PROP_PIPE, .set =3D iris_set_pipe, }, diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/dri= vers/media/platform/qcom/iris/iris_platform_qcs8300.h index 87517361a1cf4b6fe53b8a1483188670df52c7e7..612526a938eed0554fc0da99e12= c26d22e04bb6e 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h +++ b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h @@ -147,9 +147,9 @@ static const struct platform_inst_fw_cap inst_fw_cap_qc= s8300_dec[] =3D { { .cap_id =3D PIPE, .min =3D PIPE_1, - .max =3D PIPE_2, + /* .max is set via platform data */ .step_or_mask =3D 1, - .value =3D PIPE_2, + /* .value is set via platform data */ .hfi_id =3D HFI_PROP_PIPE, .set =3D iris_set_pipe, }, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 66a5bdd24d8a0e98b0554a019438bf4caa1dc43c..2b3b8bd00a6096acaae928318d9= 231847ec89855 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -21,9 +21,9 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm82= 50_dec[] =3D { { .cap_id =3D PIPE, .min =3D PIPE_1, - .max =3D PIPE_4, + /* .max is set via platform data */ .step_or_mask =3D 1, - .value =3D PIPE_4, + /* .value is set via platform data */ .hfi_id =3D HFI_PROPERTY_PARAM_WORK_ROUTE, .set =3D iris_set_pipe, }, --=20 2.47.3 From nobody Sun Feb 8 07:21:31 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AD102C0294 for ; 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Drop the QCS8300-specific tables and use generic one instead. Signed-off-by: Dmitry Baryshkov --- .../media/platform/qcom/iris/iris_platform_gen2.c | 28 +- .../platform/qcom/iris/iris_platform_qcs8300.h | 550 -----------------= ---- 2 files changed, 18 insertions(+), 560 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 7ad03a800356ae9fb73bdbd6d09928d0b500cb3c..5ddc579a73bbc75e3bfca5881d6= eee4aa40f09c9 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -12,7 +12,6 @@ #include "iris_vpu_buffer.h" #include "iris_vpu_common.h" =20 -#include "iris_platform_qcs8300.h" #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" =20 @@ -993,11 +992,20 @@ const struct iris_platform_data sm8750_data =3D { .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 -/* - * Shares most of SM8550 data except: - * - inst_caps to platform_inst_cap_qcs8300 - * - inst_fw_caps to inst_fw_cap_qcs8300 - */ +static struct platform_inst_caps platform_inst_cap_qcs8300 =3D { + .min_frame_width =3D 96, + .max_frame_width =3D 4096, + .min_frame_height =3D 96, + .max_frame_height =3D 4096, + .max_mbpf =3D (4096 * 2176) / 256, + .mb_cycles_vpp =3D 200, + .mb_cycles_fw =3D 326389, + .mb_cycles_fw_vpp =3D 44156, + .num_comv =3D 0, + .max_frame_rate =3D MAXIMUM_FPS, + .max_operating_rate =3D MAXIMUM_FPS, +}; + const struct iris_platform_data qcs8300_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, @@ -1022,10 +1030,10 @@ const struct iris_platform_data qcs8300_data =3D { .fwname =3D "qcom/vpu/vpu30_p4_s6.mbn", .pas_id =3D IRIS_PAS_ID, .inst_caps =3D &platform_inst_cap_qcs8300, - .inst_fw_caps_dec =3D inst_fw_cap_qcs8300_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_qcs8300_dec), - .inst_fw_caps_enc =3D inst_fw_cap_qcs8300_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_qcs8300_enc), + .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), + .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data =3D &tz_cp_config_sm8550, .core_arch =3D VIDEO_ARCH_LX, .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/dri= vers/media/platform/qcom/iris/iris_platform_qcs8300.h deleted file mode 100644 index 612526a938eed0554fc0da99e12c26d22e04bb6e..000000000000000000000000000= 0000000000000 --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h +++ /dev/null @@ -1,550 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights res= erved. - */ - -#define BITRATE_MAX 245000000 - -static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] =3D { - { - .cap_id =3D PROFILE_H264, - .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, - .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH), - .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, - .hfi_id =3D HFI_PROP_PROFILE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D PROFILE_HEVC, - .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, - .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | - BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), - .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, - .hfi_id =3D HFI_PROP_PROFILE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D PROFILE_VP9, - .min =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, - .max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) | - BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2), - .value =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, - .hfi_id =3D HFI_PROP_PROFILE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D LEVEL_H264, - .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, - .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_2, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_2), - .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_1, - .hfi_id =3D HFI_PROP_LEVEL, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D LEVEL_HEVC, - .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, - .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2), - .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1, - .hfi_id =3D HFI_PROP_LEVEL, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D LEVEL_VP9, - .min =3D V4L2_MPEG_VIDEO_VP9_LEVEL_1_0, - .max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_6_0, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_1) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_2) | - BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_6_0), - .value =3D V4L2_MPEG_VIDEO_VP9_LEVEL_6_0, - .hfi_id =3D HFI_PROP_LEVEL, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D TIER, - .min =3D V4L2_MPEG_VIDEO_HEVC_TIER_MAIN, - .max =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) | - BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH), - .value =3D V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, - .hfi_id =3D HFI_PROP_TIER, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - .set =3D iris_set_u32_enum, - }, - { - .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, - .min =3D DEFAULT_MAX_HOST_BUF_COUNT, - .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, - .step_or_mask =3D 1, - .value =3D DEFAULT_MAX_HOST_BUF_COUNT, - .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, - .flags =3D CAP_FLAG_INPUT_PORT, - .set =3D iris_set_u32, - }, - { - .cap_id =3D STAGE, - .min =3D STAGE_1, - .max =3D STAGE_2, - .step_or_mask =3D 1, - .value =3D STAGE_2, - .hfi_id =3D HFI_PROP_STAGE, - .set =3D iris_set_stage, - }, - { - .cap_id =3D PIPE, - .min =3D PIPE_1, - /* .max is set via platform data */ - .step_or_mask =3D 1, - /* .value is set via platform data */ - .hfi_id =3D HFI_PROP_PIPE, - .set =3D iris_set_pipe, - }, - { - .cap_id =3D POC, - .min =3D 0, - .max =3D 2, - .step_or_mask =3D 1, - .value =3D 1, - .hfi_id =3D HFI_PROP_PIC_ORDER_CNT_TYPE, - }, - { - .cap_id =3D CODED_FRAMES, - .min =3D CODED_FRAMES_PROGRESSIVE, - .max =3D CODED_FRAMES_PROGRESSIVE, - .step_or_mask =3D 0, - .value =3D CODED_FRAMES_PROGRESSIVE, - .hfi_id =3D HFI_PROP_CODED_FRAMES, - }, - { - .cap_id =3D BIT_DEPTH, - .min =3D BIT_DEPTH_8, - .max =3D BIT_DEPTH_8, - .step_or_mask =3D 1, - .value =3D BIT_DEPTH_8, - .hfi_id =3D HFI_PROP_LUMA_CHROMA_BIT_DEPTH, - }, - { - .cap_id =3D RAP_FRAME, - .min =3D 0, - .max =3D 1, - .step_or_mask =3D 1, - .value =3D 1, - .hfi_id =3D HFI_PROP_DEC_START_FROM_RAP_FRAME, - .flags =3D CAP_FLAG_INPUT_PORT, - .set =3D iris_set_u32, - }, -}; - -static const struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] =3D { - { - .cap_id =3D PROFILE_H264, - .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, - .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH), - .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, - .hfi_id =3D HFI_PROP_PROFILE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D PROFILE_HEVC, - .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, - .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | - BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) | - BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10), - .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, - .hfi_id =3D HFI_PROP_PROFILE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D LEVEL_H264, - .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, - .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | - BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0), - .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_0, - .hfi_id =3D HFI_PROP_LEVEL, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D LEVEL_HEVC, - .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, - .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) | - BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2), - .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5, - .hfi_id =3D HFI_PROP_LEVEL, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D STAGE, - .min =3D STAGE_1, - .max =3D STAGE_2, - .step_or_mask =3D 1, - .value =3D STAGE_2, - .hfi_id =3D HFI_PROP_STAGE, - }, - { - .cap_id =3D HEADER_MODE, - .min =3D V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, - .max =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | - BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), - .value =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, - .hfi_id =3D HFI_PROP_SEQ_HEADER_MODE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D PREPEND_SPSPPS_TO_IDR, - .min =3D 0, - .max =3D 1, - .step_or_mask =3D 1, - .value =3D 0, - }, - { - .cap_id =3D BITRATE, - .min =3D 1, - .max =3D BITRATE_MAX, - .step_or_mask =3D 1, - .value =3D BITRATE_DEFAULT, - .hfi_id =3D HFI_PROP_TOTAL_BITRATE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id =3D BITRATE_PEAK, - .min =3D 1, - .max =3D BITRATE_MAX, - .step_or_mask =3D 1, - .value =3D BITRATE_DEFAULT, - .hfi_id =3D HFI_PROP_TOTAL_PEAK_BITRATE, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id =3D BITRATE_MODE, - .min =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, - .max =3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | - BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR), - .value =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, - .hfi_id =3D HFI_PROP_RATE_CONTROL, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D FRAME_SKIP_MODE, - .min =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, - .max =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) | - BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) | - BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT), - .value =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D FRAME_RC_ENABLE, - .min =3D 0, - .max =3D 1, - .step_or_mask =3D 1, - .value =3D 1, - }, - { - .cap_id =3D GOP_SIZE, - .min =3D 0, - .max =3D INT_MAX, - .step_or_mask =3D 1, - .value =3D 2 * DEFAULT_FPS - 1, - .hfi_id =3D HFI_PROP_MAX_GOP_FRAMES, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id =3D ENTROPY_MODE, - .min =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, - .max =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, - .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | - BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), - .value =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, - .hfi_id =3D HFI_PROP_CABAC_SESSION, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, - }, - { - .cap_id =3D MIN_FRAME_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - .hfi_id =3D HFI_PROP_MIN_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT, - }, - { - .cap_id =3D MIN_FRAME_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - .hfi_id =3D HFI_PROP_MIN_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT, - }, - { - .cap_id =3D MAX_FRAME_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - .hfi_id =3D HFI_PROP_MAX_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT, - }, - { - .cap_id =3D MAX_FRAME_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - .hfi_id =3D HFI_PROP_MAX_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT, - }, - { - .cap_id =3D I_FRAME_MIN_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - }, - { - .cap_id =3D I_FRAME_MIN_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - }, - { - .cap_id =3D P_FRAME_MIN_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - }, - { - .cap_id =3D P_FRAME_MIN_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - }, - { - .cap_id =3D B_FRAME_MIN_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - }, - { - .cap_id =3D B_FRAME_MIN_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MIN_QP_8BIT, - }, - { - .cap_id =3D I_FRAME_MAX_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - }, - { - .cap_id =3D I_FRAME_MAX_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - }, - { - .cap_id =3D P_FRAME_MAX_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - }, - { - .cap_id =3D P_FRAME_MAX_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - }, - { - .cap_id =3D B_FRAME_MAX_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - }, - { - .cap_id =3D B_FRAME_MAX_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D MAX_QP, - }, - { - .cap_id =3D I_FRAME_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D DEFAULT_QP, - .hfi_id =3D HFI_PROP_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id =3D I_FRAME_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D DEFAULT_QP, - .hfi_id =3D HFI_PROP_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id =3D P_FRAME_QP_H264, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D DEFAULT_QP, - .hfi_id =3D HFI_PROP_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id =3D P_FRAME_QP_HEVC, - .min =3D MIN_QP_8BIT, - .max =3D MAX_QP, - .step_or_mask =3D 1, - .value =3D DEFAULT_QP, - .hfi_id =3D HFI_PROP_QP_PACKED, - .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | - CAP_FLAG_DYNAMIC_ALLOWED, - }, - { - .cap_id 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Signed-off-by: Dmitry Baryshkov Reviewed-by: Dikshita Agarwal Reviewed-by: Konrad Dybcio --- drivers/media/platform/qcom/iris/Makefile | = 2 +- .../platform/qcom/iris/{iris_platform_sm8250.c =3D> iris_platform_gen1.c} = | 0 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 13270cd6d899852dded675b33d37f5919b81ccba..fad3be044e5fe783db697a592b4= f09de4d42d0d2 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -26,7 +26,7 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_vpu_common.o \ =20 ifeq ($(CONFIG_VIDEO_QCOM_VENUS),) -qcom-iris-objs +=3D iris_platform_sm8250.o +qcom-iris-objs +=3D iris_platform_gen1.o endif =20 obj-$(CONFIG_VIDEO_QCOM_IRIS) +=3D qcom-iris.o diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_gen1.c similarity index 100% rename from drivers/media/platform/qcom/iris/iris_platform_sm8250.c rename to drivers/media/platform/qcom/iris/iris_platform_gen1.c --=20 2.47.3 From nobody Sun Feb 8 07:21:31 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F40A2C0F67 for ; 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Signed-off-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 35 -------------- drivers/media/platform/qcom/iris/iris_vpu_common.c | 43 ----------------- .../platform/qcom/iris/iris_vpu_register_defines.h | 56 ++++++++++++++++++= ++++ 3 files changed, 56 insertions(+), 78 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index 339776a0b4672e246848c3a6a260eb83c7da6a60..78aede9ac497abafc0545647c34= a53c63c595f72 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -11,48 +11,13 @@ #include "iris_vpu_common.h" #include "iris_vpu_register_defines.h" =20 -#define WRAPPER_TZ_BASE_OFFS 0x000C0000 -#define AON_BASE_OFFS 0x000E0000 #define AON_MVP_NOC_RESET 0x0001F000 =20 -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) -#define REQ_POWER_DOWN_PREP BIT(0) -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) -#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is com= plete */ -#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is den= ied */ -#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ -#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) -#define CORE_CLK_RUN 0x0 -/* VPU v3.5 */ -#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) - -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) -#define CTL_AXI_CLK_HALT BIT(0) -#define CTL_CLK_HALT BIT(1) - -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) -#define RESET_HIGH BIT(0) - -#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) -#define CORE_BRIDGE_SW_RESET BIT(0) -#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) - -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) -#define MSK_SIGNAL_FROM_TENSILICA BIT(0) -#define MSK_CORE_POWER_ON BIT(1) - #define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) =20 #define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004) =20 -#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) - -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) - #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18) #define SW_RESET BIT(0) #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index bb98950e018fadf69ac4f41b3037f7fd6ac33c5b..2d6548e47d47967c1c110489cb8= 088130fb625fd 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -11,13 +11,6 @@ #include "iris_vpu_common.h" #include "iris_vpu_register_defines.h" =20 -#define WRAPPER_TZ_BASE_OFFS 0x000C0000 -#define AON_BASE_OFFS 0x000E0000 - -#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS) - -#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C) -#define CLEAR_XTENSA2HOST_INTR BIT(0) =20 #define CTRL_INIT (CPU_CS_BASE_OFFS + 0x48) #define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C) @@ -35,42 +28,6 @@ #define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64) #define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68) =20 -#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148) -#define HOST2XTENSA_INTR_ENABLE BIT(0) - -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) -#define MSK_SIGNAL_FROM_TENSILICA BIT(0) -#define MSK_CORE_POWER_ON BIT(1) - -#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150) -#define CPU_IC_SOFTINT_H2A_SHFT 0x0 - -#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C) -#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) -#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2) - -#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10) -#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3) -#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2) - -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) - -#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10) -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) -#define CTL_AXI_CLK_HALT BIT(0) -#define CTL_CLK_HALT BIT(1) - -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) -#define RESET_HIGH BIT(0) - -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) -#define REQ_POWER_DOWN_PREP BIT(0) - -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) - static void iris_vpu_interrupt_init(struct iris_core *core) { u32 mask_val; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b= /drivers/media/platform/qcom/iris/iris_vpu_register_defines.h index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..9955367a9f8179d2e364c41dcfe= 8ad445a0a13f4 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h @@ -9,9 +9,65 @@ #define VCODEC_BASE_OFFS 0x00000000 #define CPU_BASE_OFFS 0x000A0000 #define WRAPPER_BASE_OFFS 0x000B0000 +#define WRAPPER_TZ_BASE_OFFS 0x000C0000 +#define AON_BASE_OFFS 0x000E0000 + +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) =20 #define CPU_CS_BASE_OFFS (CPU_BASE_OFFS) =20 +#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C) +#define CLEAR_XTENSA2HOST_INTR BIT(0) + +#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148) +#define HOST2XTENSA_INTR_ENABLE BIT(0) + +#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS) +#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150) +#define CPU_IC_SOFTINT_H2A_SHFT 0x0 + +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) +#define CORE_BRIDGE_SW_RESET BIT(0) +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) + +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) +#define MSK_SIGNAL_FROM_TENSILICA BIT(0) +#define MSK_CORE_POWER_ON BIT(1) + +#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C) +#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) +#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2) + +#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10) +#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3) +#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2) + #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80) +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) +#define REQ_POWER_DOWN_PREP BIT(0) + +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is com= plete */ +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is den= ied */ +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ + +#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) + +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) +#define CORE_CLK_RUN 0x0 + +#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10) + +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) +#define CTL_AXI_CLK_HALT BIT(0) +#define CTL_CLK_HALT BIT(1) + +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) +#define RESET_HIGH BIT(0) + +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) =20 #endif --=20 2.47.3 From nobody Sun Feb 8 07:21:31 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 132D32C11E4 for ; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-58b0119f461sm6751107e87.107.2025.10.07.21.33.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Oct 2025 21:33:26 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 08 Oct 2025 07:33:06 +0300 Subject: [PATCH 8/8] media: iris: enable support for SC7280 platform Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251008-iris-sc7280-v1-8-def050ba5e1f@oss.qualcomm.com> References: <20251008-iris-sc7280-v1-0-def050ba5e1f@oss.qualcomm.com> In-Reply-To: <20251008-iris-sc7280-v1-0-def050ba5e1f@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11419; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=SI7znv4ie6w0KvvXmNwGIwdLuWepocC3U404l8kktWA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBo5emDhnpYDY15w/xa+obWYsCjIkZuFkTPXV1Sg xsohCK3HlCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaOXpgwAKCRCLPIo+Aiko 1X5GB/9uL8e9fHr1AE99qTBjCO3NwHOAYRhq4DNT3u4ckXhs6YjJpNEz74KoWqElvwlmTcstPfs 73nzwxx+ke1QzuZ/HvY9EFR6Cb6CP5alREjRyG5s3pxxGejUUhHEYsL7l6g9sadazfjtkxGJoGh oJcRe47hENmasmngupbtXVVWGkgwSg0J8N/0XfH8WJMOaF6wt+LebtZO3Xaejy9zCs9cRkgLoMy EcjOVCQ6s4txD2CZLqkMSZ/8+DASG+e02ZVBYqlnuUcC9ZMRK2+3CYi2sWgnAu92ZOgQRjQYa5r x2UjrlxNlcxpeY4E5cDz7tQNKRRTRKoIulgN0NT3nNW6Ut2Q X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA3MDExNyBTYWx0ZWRfX/42BMbIsNOeJ JT/CRVWv+o8OfCYpHBG+f3xPfA3Bu4pDoHN5ZT9mUrqJF/Hwuq2O91XhSL/4XwLX7CQAP2znlT1 sskODKLmKYBoBavYWp6LH9Z1th0Kzh+xhEoksD+P/xxqoTkjzu9YfuobYJkgLhnWKyG8SQXUZZp AEu8U/bErSN5KbMwggKpdXhDab7xc4Jqq69yParcBJTvqRdTThG/BECuGrD83me13STXtoBzsuX PpvMfQ9XHCgMm1xLrbQElB+iVBOd5HEEK74IjfmTXgCLuEvMNuoyfjSgbXrzQrf/HRDhanVROub hol0wxIBOJQaRBiSnIa3LYIWsMTG+GBwtKq6LG8hlLnVpaXHj+xf0MMqgJmZP5lASxp1/9XexQL Hdf5DVxdLnQNJLoMYjywqPcl+X+EQQ== X-Authority-Analysis: v=2.4 cv=BP2+bVQG c=1 sm=1 tr=0 ts=68e5e99a cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=EUspDBNiAAAA:8 a=pG0Ruh8lDxDpiiRDS04A:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-GUID: HNFIX9yIWfLn97l5eoD4gVaOxEgqvMh2 X-Proofpoint-ORIG-GUID: HNFIX9yIWfLn97l5eoD4gVaOxEgqvMh2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-07_02,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 malwarescore=0 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2510070117 As a part of migrating code from the old Venus driver to the new Iris one, add support for the SC7280 platform. It is very similar to SM8250, but it (currently) uses no reset controls (there is an optional GCC-generated reset, it will be added later) and no AON registers region. The Venus driver names this platform "IRIS2_1", so the ops in the driver are also now called iris_vpu21_ops. Signed-off-by: Dmitry Baryshkov --- .../platform/qcom/iris/iris_platform_common.h | 3 + .../media/platform/qcom/iris/iris_platform_gen1.c | 66 +++++++++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 + drivers/media/platform/qcom/iris/iris_vpu2.c | 130 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + 5 files changed, 204 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 104ff38219e30e6d52476d44b54338c55ef2ca7b..36e33eb05a6918de590feca37b4= 1c07a92e9c434 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -42,6 +42,7 @@ enum pipe_type { }; =20 extern const struct iris_platform_data qcs8300_data; +extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; extern const struct iris_platform_data sm8550_data; extern const struct iris_platform_data sm8650_data; @@ -50,7 +51,9 @@ extern const struct iris_platform_data sm8750_data; enum platform_clk_type { IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ IRIS_CTRL_CLK, + IRIS_AHB_CLK, IRIS_HW_CLK, + IRIS_HW_AXI_CLK, IRIS_AXI1_CLK, IRIS_CTRL_FREERUN_CLK, IRIS_HW_FREERUN_CLK, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_platform_gen1.c index 2b3b8bd00a6096acaae928318d9231847ec89855..d5288a71a6a8289e5ecf69b6f38= 231500f2bf8b4 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -364,3 +364,69 @@ const struct iris_platform_data sm8250_data =3D { .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; + +static const struct bw_info sc7280_bw_table_dec[] =3D { + { ((3840 * 2160) / 256) * 60, 1896000, }, + { ((3840 * 2160) / 256) * 30, 968000, }, + { ((1920 * 1080) / 256) * 60, 618000, }, + { ((1920 * 1080) / 256) * 30, 318000, }, +}; + +static const char * const sc7280_opp_pd_table[] =3D { "cx" }; + +static const struct platform_clk_data sc7280_clk_table[] =3D { + {IRIS_CTRL_CLK, "core" }, + {IRIS_AXI_CLK, "bus" }, + {IRIS_AHB_CLK, "iface" }, + {IRIS_HW_CLK, "vcodec_core" }, + {IRIS_HW_AXI_CLK, "vcodec_bus" }, +}; + +const struct iris_platform_data sc7280_data =3D { + .get_instance =3D iris_hfi_gen1_get_instance, + .init_hfi_command_ops =3D &iris_hfi_gen1_command_ops_init, + .init_hfi_response_ops =3D iris_hfi_gen1_response_ops_init, + .get_vpu_buffer_size =3D iris_vpu_buf_size, + .vpu_ops =3D &iris_vpu21_ops, + .set_preset_registers =3D iris_set_sm8250_preset_registers, + .icc_tbl =3D sm8250_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), + .bw_tbl_dec =3D sc7280_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sc7280_bw_table_dec), + .pmdomain_tbl =3D sm8250_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8250_pmdomain_table), + .opp_pd_tbl =3D sc7280_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sc7280_opp_pd_table), + .clk_tbl =3D sc7280_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sc7280_clk_table), + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu20_p1.mbn", + .pas_id =3D IRIS_PAS_ID, + .inst_caps =3D &platform_inst_cap_sm8250, + .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), + .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), + .tz_cp_config_data =3D &tz_cp_config_sm8250, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, + .dec_input_config_params_default =3D + sm8250_vdec_input_config_param_default, + .dec_input_config_params_default_size =3D + ARRAY_SIZE(sm8250_vdec_input_config_param_default), + .enc_input_config_params =3D sm8250_venc_input_config_param, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8250_venc_input_config_param), + + .dec_ip_int_buf_tbl =3D sm8250_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), +}; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 00e99be16e087c4098f930151fd76cd381d721ce..9bc9b34c2576581635fa8d87eed= 1965657eb3eb3 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -357,6 +357,10 @@ static const struct of_device_id iris_dt_match[] =3D { .data =3D &qcs8300_data, }, #if (!IS_ENABLED(CONFIG_VIDEO_QCOM_VENUS)) + { + .compatible =3D "qcom,sc7280-venus", + .data =3D &sc7280_data, + }, { .compatible =3D "qcom,sm8250-venus", .data =3D &sm8250_data, diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/p= latform/qcom/iris/iris_vpu2.c index de7d142316d2dc9ab0c4ad9cc8161c87ac949b4c..73fae652cfea6b729d4b8f9346a= 345a88b068394 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -3,9 +3,15 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 +#include +#include +#include + #include "iris_instance.h" #include "iris_vpu_common.h" =20 +#include "iris_vpu_register_defines.h" + static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size) { struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; @@ -32,6 +38,122 @@ static u64 iris_vpu2_calc_freq(struct iris_inst *inst, = size_t data_size) return max(vpp_freq, vsp_freq); } =20 +/* iris_vpu_power_off_hw + IRIS_HW_AXI_CLK */ +static void iris_vpu21_power_off_hw(struct iris_core *core) +{ + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]= , false); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_HW_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_CLK); +} + +/* iris_vpu_power_on_hw + IRIS_HW_AXI_CLK */ +static int iris_vpu21_power_on_hw(struct iris_core *core) +{ + int ret; + + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); + if (ret) + goto err_disable_power; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_AXI_CLK); + if (ret) + goto err_disable_hw_clock; + + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], true); + if (ret) + goto err_disable_hw_axi_clock; + + return 0; + +err_disable_hw_axi_clock: + iris_disable_unprepare_clock(core, IRIS_HW_AXI_CLK); +err_disable_hw_clock: + iris_disable_unprepare_clock(core, IRIS_HW_CLK); +err_disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + + return ret; +} + +/* iris_vpu_power_on_controller + IRIS_AHB_CLK */ +static int iris_vpu21_power_on_controller(struct iris_core *core) +{ + int ret; + + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= CTRL_POWER_DOMAIN]); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_AXI_CLK); + if (ret) + goto err_disable_power; + + ret =3D iris_prepare_enable_clock(core, IRIS_CTRL_CLK); + if (ret) + goto err_disable_axi_clock; + + ret =3D iris_prepare_enable_clock(core, IRIS_AHB_CLK); + if (ret) + goto err_disable_ctrl_clock; + + return 0; + +err_disable_ctrl_clock: + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); +err_disable_axi_clock: + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); +err_disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + + return ret; +} + +/* + * This is the same as iris_vpu_power_off_controller except + * AON_WRAPPER_MVP_NOC_LPI_CONTROL / AON_WRAPPER_MVP_NOC_LPI_STATUS progra= mming + * and with added IRIS_AHB_CLK handling + */ +static int iris_vpu21_power_off_controller(struct iris_core *core) +{ + u32 val =3D 0; + int ret; + + writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CP= U_CS_X2RPMH); + + writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CON= TROL); + + ret =3D readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STAT= US, + val, val & BIT(0), 200, 2000); + if (ret) + goto disable_power; + + writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL); + + ret =3D readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STAT= US, + val, val =3D=3D 0, 200, 2000); + if (ret) + goto disable_power; + + writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT, + core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); + writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); + writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); + writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); + +disable_power: + iris_disable_unprepare_clock(core, IRIS_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + + return 0; +} + const struct vpu_ops iris_vpu2_ops =3D { .power_off_hw =3D iris_vpu_power_off_hw, .power_on_hw =3D iris_vpu_power_on_hw, @@ -39,3 +161,11 @@ const struct vpu_ops iris_vpu2_ops =3D { .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu2_calc_freq, }; + +const struct vpu_ops iris_vpu21_ops =3D { + .power_off_hw =3D iris_vpu21_power_off_hw, + .power_on_hw =3D iris_vpu21_power_on_hw, + .power_off_controller =3D iris_vpu21_power_off_controller, + .power_on_controller =3D iris_vpu21_power_on_controller, + .calc_freq =3D iris_vpu2_calc_freq, +}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index d636e287457adf0c44540af5c85cfa69decbca8b..6589fecbfeeec75d21759048afe= ca7fb42e65492 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -9,6 +9,7 @@ struct iris_core; =20 extern const struct vpu_ops iris_vpu2_ops; +extern const struct vpu_ops iris_vpu21_ops; extern const struct vpu_ops iris_vpu3_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; --=20 2.47.3