From nobody Mon Feb 9 03:30:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EA62261B70; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; cv=none; b=jtRdohXplTJBc5QqtpIk75Pj/lUoU9IQ367ksFhy1snRl6xAZGTUXJsGEhaDrcDD7lBzvqiHDLgxTxIROu+muuXmx0HedvZtPMpdV9VJROpDhNttKHw39b87L4ViHCpEZWaaA35bTJuFtXuQOEjHOu0zHrgOfwLqBy7Hwgqh5g8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; c=relaxed/simple; bh=DcwuyX8vW2kqJZ7nlBXFHvGPhvHT+XYW91wlJclysz4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qMeE30onCy8NbTbr+3NaAIAuC56kbEPNSq9r0RHSL9n08GExp7E0uFCArDiDrvh3TmYwvrqpVGMpXW/OheRbh82y9HaY4/lcWKupwGidLP+wmaVsGAWmsDIZIt+chAHaykEpEpE8NPJX7CtxLl/IWIE2lw4TG2NLy8sjpwZQkIU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=obAcn+YP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="obAcn+YP" Received: by smtp.kernel.org (Postfix) with ESMTPS id B2859C4CEF5; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759937626; bh=DcwuyX8vW2kqJZ7nlBXFHvGPhvHT+XYW91wlJclysz4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=obAcn+YPyjQLPRFp9JI9p6flimei3nzeHRTM16PgivBbMKWdOX6xQu780T0yB5ys4 Ltws4SZj2BSaZwGqs4GdoiRmDw8/3KA5zu6lL7z3VGbqTHp/C4Etann83ipXLZ5p4P uVZC/LaaEZjfcsMRZK/mXCt+/EQ4TzpkJUmG92qGWe1Ykr0XrY7EhNCRVf4bTrmoqD O3dAZpOrfiaFYAvTm40VhqK9UchbRfCcE3Z/R32uW9O3+6ox9lbh65HnC0fJX1sSKd 7qHa25jxxUNafANzlYRpIte1gP16D5iRaG2994PxnxFQaPLpqiLwV0XMnUYO3m5XbQ 6TXySABFl6SBA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 958BECAC5BB; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 08 Oct 2025 19:32:53 +0400 Subject: [PATCH v17 1/9] dt-bindings: pwm: add IPQ6018 binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251008-ipq-pwm-v17-1-9bd43edfc7f7@outlook.com> References: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> In-Reply-To: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Krzysztof Kozlowski , Baruch Siach , Bjorn Andersson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759937622; l=1766; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=TIgQXfGvQp7H4uzUZyQsZZpdMSae9nM97ANzvYRj3gc=; b=/vRKCVEyXYSstoHCa60PMTarLCLZUFfaaMqmy9pUtzVcvDqiVIbHpeXbRinTeYm79a9XeT9mW aTwYOI2pestAAQeKr6dmgA8CiMgMuz18dGikEXzx8UYn5+9c6qq27Nc X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya DT binding for the PWM block in Qualcomm IPQ6018 SoC. Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya --- .../devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml | 44 ++++++++++++++++++= ++++ 1 file changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/= Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..1172f0b53fadc140482f9384a36= 020260df372b7 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/qcom,ipq6018-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - Baruch Siach + +properties: + compatible: + const: qcom,ipq6018-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include + + pwm: pwm@1941010 { + compatible =3D "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + }; --=20 2.51.0 From nobody Mon Feb 9 03:30:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EC752F6169; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; cv=none; b=nnB5JJOlXok5yEeptldylujxxxhGlYK2yT/06VTUBKBfSRrLIW3ild9XODv3rfrXBrvkZ//i85CMnE3dojF0K2Qd+I+k5wKRPou9Vqh0an8Y9ywIsZomxpnXwKlMRUCfefgZrIV5m74+j+Q1RmuBxF0u4PRFjI0QOV3f3g73t0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; c=relaxed/simple; bh=s2llcLUI1qnY0o3dLcMwEv1pSMRV1To4R+Ze+EHdylc=; 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Wed, 8 Oct 2025 15:33:46 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 08 Oct 2025 19:32:54 +0400 Subject: [PATCH v17 2/9] pwm: driver for qualcomm ipq6018 pwm block Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251008-ipq-pwm-v17-2-9bd43edfc7f7@outlook.com> References: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> In-Reply-To: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Baruch Siach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759937622; l=9936; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=Roow9Rqqb2wHqPZaEC93x3A3cup5+su0zvJQmUIvI7I=; b=f1tUSjr77+qYPuQv0JFI+MT8m7W1O9RGHzuaRzkylVdkzMDDRUpW4PZvKDYLbiEh0BPMGWWZA JlRd5qLxr9PARbdBDZyBlb7ziD515YUdAZtdKwWwlS8iXKafQgb1swu X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on driver from downstream Codeaurora kernel tree. Removed support for older (V1) variants because I have no access to that hardware. Tested on IPQ5018 and IPQ6010 based hardware. Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Signed-off-by: George Moussalem Reviewed-by: Bjorn Andersson --- v17: Removed unnecessary code comments v16: Simplified code to calculate divs and duty cycle as per Uwe's comments Removed unused pwm_chip struct from ipq_pwm_chip struct Removed unnecessary cast as per Uwe's comment Replaced devm_clk_get & clk_prepare_enable by devm_clk_get_enabled Replaced pwmchip_add by devm_pwmchip_add and removed .remove function Removed .owner from driver struct v15: No change v14: Picked up the R-b tag v13: Updated the file name to match the compatible Sorted the properties and updated the order in the required field Dropped the syscon node from examples v12: Picked up the R-b tag v11: No change v10: No change v9: Add 'ranges' property to example (Rob) Drop label in example (Rob) v8: Add size cell to 'reg' (Rob) v7: Use 'reg' instead of 'offset' (Rob) Drop 'clock-names' and 'assigned-clock*' (Bjorn) Use single cell address/size in example node (Bjorn) Move '#pwm-cells' lower in example node (Bjorn) List 'reg' as required v6: Device node is child of TCSR; remove phandle (Rob Herring) Add assigned-clocks/assigned-clock-rates (Uwe Kleine-K=C3=B6nig) v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn Andersson, Kathiravan T) v4: Update the binding example node as well (Rob Herring's bot) v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) v2: Make #pwm-cells const (Rob Herring) --- drivers/pwm/Kconfig | 12 +++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ipq.c | 212 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 225 insertions(+) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index c2fd3f4b62d9ea422a51a73fa87dc7a73703ebaf..33ac49251b3cc957bc356aa3919= 9b748577d295f 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -337,6 +337,18 @@ config PWM_INTEL_LGM To compile this driver as a module, choose M here: the module will be called pwm-intel-lgm. =20 +config PWM_IPQ + tristate "IPQ PWM support" + depends on ARCH_QCOM || COMPILE_TEST + depends on HAVE_CLK && HAS_IOMEM + help + Generic PWM framework driver for IPQ PWM block which supports + 4 pwm channels. Each of the these channels can be configured + independent of each other. + + To compile this driver as a module, choose M here: the module + will be called pwm-ipq. + config PWM_IQS620A tristate "Azoteq IQS620A PWM support" depends on MFD_IQS62X || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index dfa8b4966ee19af18ea47080db4adf96c326f3d7..74e07f654d43dfee83e7bb3a49e= 41acf8ae011fc 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_PWM_IMX1) +=3D pwm-imx1.o obj-$(CONFIG_PWM_IMX27) +=3D pwm-imx27.o obj-$(CONFIG_PWM_IMX_TPM) +=3D pwm-imx-tpm.o obj-$(CONFIG_PWM_INTEL_LGM) +=3D pwm-intel-lgm.o +obj-$(CONFIG_PWM_IPQ) +=3D pwm-ipq.o obj-$(CONFIG_PWM_IQS620A) +=3D pwm-iqs620a.o obj-$(CONFIG_PWM_JZ4740) +=3D pwm-jz4740.o obj-$(CONFIG_PWM_KEEMBAY) +=3D pwm-keembay.o diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c new file mode 100644 index 0000000000000000000000000000000000000000..bd6b3ad86596e3c5b19f80f97fe= 7913a8ce2d940 --- /dev/null +++ b/drivers/pwm/pwm-ipq.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/* + * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* The frequency range supported is 1 Hz to clock rate */ +#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC) + +/* + * The max value specified for each field is based on the number of bits + * in the pwm control register for that field + */ +#define IPQ_PWM_MAX_DIV 0xFFFF + +/* + * Two 32-bit registers for each PWM: REG0, and REG1. + * Base offset for PWM #i is at 8 * #i. + */ +#define IPQ_PWM_REG0 0 +#define IPQ_PWM_REG0_PWM_DIV GENMASK(15, 0) +#define IPQ_PWM_REG0_HI_DURATION GENMASK(31, 16) + +#define IPQ_PWM_REG1 4 +#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0) +/* + * Enable bit is set to enable output toggling in pwm device. + * Update bit is set to reflect the changed divider and high duration + * values in register. + */ +#define IPQ_PWM_REG1_UPDATE BIT(30) +#define IPQ_PWM_REG1_ENABLE BIT(31) + +struct ipq_pwm_chip { + struct clk *clk; + void __iomem *mem; +}; + +static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static unsigned int ipq_pwm_reg_read(struct pwm_device *pwm, unsigned int = reg) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); + unsigned int off =3D 8 * pwm->hwpwm + reg; + + return readl(ipq_chip->mem + off); +} + +static void ipq_pwm_reg_write(struct pwm_device *pwm, unsigned int reg, + unsigned int val) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); + unsigned int off =3D 8 * pwm->hwpwm + reg; + + writel(val, ipq_chip->mem + off); +} + +static void config_div_and_duty(struct pwm_device *pwm, unsigned int pre_d= iv, + unsigned int pwm_div, unsigned long rate, u64 duty_ns, + bool enable) +{ + unsigned long hi_dur; + unsigned long val =3D 0; + + /* + * high duration =3D pwm duty * (pwm div + 1) + * pwm duty =3D duty_ns / period_ns + */ + hi_dur =3D div64_u64(duty_ns * rate, (pre_div + 1) * NSEC_PER_SEC); + + val =3D FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) | + FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div); + ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val); + + val =3D FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div); + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); + + /* PWM enable toggle needs a separate write to REG1 */ + val |=3D IPQ_PWM_REG1_UPDATE; + if (enable) + val |=3D IPQ_PWM_REG1_ENABLE; + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); +} + +static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); + unsigned long rate =3D clk_get_rate(ipq_chip->clk); + unsigned int pre_div, pwm_div; + u64 period_ns, duty_ns; + + if (state->polarity !=3D PWM_POLARITY_NORMAL) + return -EINVAL; + + if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC, rate)) + return -ERANGE; + + if ((unsigned long long)rate > 16ULL * GIGA) + return -EINVAL; + + period_ns =3D min(state->period, IPQ_PWM_MAX_PERIOD_NS); + duty_ns =3D min(state->duty_cycle, period_ns); + + /* Restrict pwm_div to 0xfffe */ + pwm_div =3D IPQ_PWM_MAX_DIV - 1; + pre_div =3D DIV64_U64_ROUND_UP(period_ns * rate, (u64)NSEC_PER_SEC * (pwm= _div + 1)); + + if (pre_div > IPQ_PWM_MAX_DIV) + return -ERANGE; + + config_div_and_duty(pwm, pre_div, pwm_div, rate, duty_ns, state->enabled); + + return 0; +} + +static int ipq_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); + unsigned long rate =3D clk_get_rate(ipq_chip->clk); + unsigned int pre_div, pwm_div, hi_dur; + u64 effective_div, hi_div; + u32 reg0, reg1; + + reg0 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG0); + reg1 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG1); + + state->polarity =3D PWM_POLARITY_NORMAL; + state->enabled =3D reg1 & IPQ_PWM_REG1_ENABLE; + + pwm_div =3D FIELD_GET(IPQ_PWM_REG0_PWM_DIV, reg0); + hi_dur =3D FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0); + pre_div =3D FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1); + + /* No overflow here, both pre_div and pwm_div <=3D 0xffff */ + effective_div =3D (pre_div + 1) * (pwm_div + 1); + state->period =3D DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, rate); + + hi_div =3D hi_dur * (pre_div + 1); + state->duty_cycle =3D DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, rate); + + return 0; +} + +static const struct pwm_ops ipq_pwm_ops =3D { + .apply =3D ipq_pwm_apply, + .get_state =3D ipq_pwm_get_state, +}; + +static int ipq_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct ipq_pwm_chip *pwm; + struct pwm_chip *chip; + int ret; + + chip =3D devm_pwmchip_alloc(dev, 4, sizeof(*pwm)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + pwm =3D ipq_pwm_from_chip(chip); + + pwm->mem =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->mem)) + return dev_err_probe(dev, PTR_ERR(pwm->mem), + "regs map failed"); + + pwm->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(pwm->clk)) + return dev_err_probe(dev, PTR_ERR(pwm->clk), + "failed to get clock"); + + chip->ops =3D &ipq_pwm_ops; + chip->npwm =3D 4; + + ret =3D devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to add pwm chip\n"); + + return ret; +} + +static const struct of_device_id pwm_ipq_dt_match[] =3D { + { .compatible =3D "qcom,ipq6018-pwm", }, + {} +}; +MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match); + +static struct platform_driver ipq_pwm_driver =3D { + .driver =3D { + .name =3D "ipq-pwm", + .of_match_table =3D pwm_ipq_dt_match, + }, + .probe =3D ipq_pwm_probe, +}; + +module_platform_driver(ipq_pwm_driver); + +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Mon Feb 9 03:30:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EB192F60CD; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251008-ipq-pwm-v17-3-9bd43edfc7f7@outlook.com> References: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> In-Reply-To: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759937623; l=1074; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=pFg/KpdU/D7prJHeba07a6q8ARK/xYrCZn9mJ+brTMI=; b=B9UjCLsvwGsiCRbH1bk3dRtzIfw6NogaWyqQb6a4MQMJOvq2c+pOM9dt5lblx8UOHQ+wZ7BMg ERmUKqUonifDEZ+t+VnwmN/UYuFMuGDUOugxYEs1irLC09wzff/yqXO X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ5018 SoC contains a PWM block which is exactly the same as the one found in IPQ6018. So let's add a compatible for IPQ5018 and use IPQ6018 as the fallback. Acked-by: Rob Herring (Arm) Signed-off-by: George Moussalem --- Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/= Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml index 1172f0b53fadc140482f9384a36020260df372b7..acbdd952fcca53368e3b594544d= f8d3dae8a06b3 100644 --- a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -11,7 +11,12 @@ maintainers: =20 properties: compatible: - const: qcom,ipq6018-pwm + oneOf: + - items: + - enum: + - qcom,ipq5018-pwm + - const: qcom,ipq6018-pwm + - const: qcom,ipq6018-pwm =20 reg: maxItems: 1 --=20 2.51.0 From nobody Mon Feb 9 03:30:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EB922F6164; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; cv=none; b=NiZjF2m8aDY4j/1WoBzi4mKpYDNqLHoUUBztD1U/Ezw/Df+XZzGLWbnaKs2teuPmzK4mZd4mQcnFKkaDbDEkltKQVXifr4pIa4+ZxtobCN9LBnTAJoaj7AsQRiS+IzRX2gyCpco9+yRKTK2wWnaf3MLIywuIDcEoUnqYsHAAunc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; c=relaxed/simple; bh=cbJmJOj7a5VPuylskDlyoxqjrd9eNcb2HD/mgl51pKI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bfWYuXtdlMGYzqCpxcM5rYY8eYTlzSJ957bHRo/R0Z+2F65jzlr6YgPoYBRiupOFx7qQGr5gAkBJu6wQ7yqaOChFhjVaVgGbpD2jKvRU1J9FhT3sLyABDn2lBNDklFkYh7w6f4yVNCsQutrHJcSPd+zdGHlwNtFh0EqcB2IjaTs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gd5pC8Uq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gd5pC8Uq" Received: by smtp.kernel.org (Postfix) with ESMTPS id CBDBBC116C6; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759937626; bh=cbJmJOj7a5VPuylskDlyoxqjrd9eNcb2HD/mgl51pKI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gd5pC8UqfrQCZQTnkIzsb6a1ciLUB/ViB+OSLYS4viUbIVd8z53kV0jRrzTBmW/2G qU+cVjTYrQSr6ZHbFmXPbQpA3cnK7b4ui1U9LWxeOGSZrQbWYQZjqgG0ocsxKLLV8p f3BtDAoubz+MKaiWxjeT5Tt0qXAU+8zLtU2AsI+IJ5vP+uCVhh9AHDokxdwHlQReZ0 EHc9Cg2vzxCw+qT2GsjnZskVN/mh1f+CRWObgqnYWPrwPTOvqlrV+U+izMTLpSWii7 83WmRfEEK2hKBtS5sQ5WamQZMA5mIBGivHlxg0W+wxnM4AVsHDFIWsv90ZkPXadsmO 0fEN4dKTRmapQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEB0DCCD187; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 08 Oct 2025 19:32:56 +0400 Subject: [PATCH v17 4/9] dt-bindings: pwm: qcom,ipq6018-pwm: Add compatible for ipq5332 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251008-ipq-pwm-v17-4-9bd43edfc7f7@outlook.com> References: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> In-Reply-To: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759937623; l=982; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=5aT5CBw2lSNROJYp7Bx6jXZM5n5xJ6CFyAT7LoR2TWw=; b=WGy2w6ICUgZFZ5r4cwcTsCL5VdD1zKaEYHOfsrpXLh3FeMwPTKL5VuhuLjCpLeklREn0K2B90 pzLU6KGGePjB/LhfadkfXTr4cH02yf3QUHfk7wDyl/OuZ39pTeTFlIx X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ5332 SoC contains a PWM block which is exactly the same as the one found in IPQ6018. So let's add a compatible for IPQ5332 and use IPQ6018 as the fallback. Acked-by: Rob Herring (Arm) Signed-off-by: George Moussalem --- Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/= Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml index acbdd952fcca53368e3b594544df8d3dae8a06b3..e00b9e01f4f89dd0d08610772c9= 84a0e2725d154 100644 --- a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -15,6 +15,7 @@ properties: - items: - enum: - qcom,ipq5018-pwm + - qcom,ipq5332-pwm - const: qcom,ipq6018-pwm - const: qcom,ipq6018-pwm =20 --=20 2.51.0 From nobody Mon Feb 9 03:30:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 548222F999A; Wed, 8 Oct 2025 15:33:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; cv=none; b=gagU65eBEZ2DRF08qklGdVi4uNBqgbAI3Am3kChilXjdal8QKWoVZPDJo7GEqpiujb+snlv5/BfTramX0vwHw0ukde28/zY1KatPLoDy2gk3DVJiKzSEw7A2VIFPE9G7UY4Hkmc7y1q1i2I9bLqtLYJqw2AMrrRWJRHOOrVfe60= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; c=relaxed/simple; bh=e2ugSOI2UTAErCdXtASkJNADsZs45cfO9nbqKrgUZzA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k7zD8YRPHWSp4pyWj9fiSbBX99u+HzWxsoQhDJVjKVx2k6Q5lXtf5ze2WT1Jhgz7Dxs3ooN0jjBQE7uCRbVEQoY+MiSAgmx+yH4rd+VutVpwzRjBC9N8avQ72CsHJQA5UipLlnpQRm/3uHbJuUuol5fyIWbnz0gPhjje/9OG5iQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ICZsUVwF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ICZsUVwF" Received: by smtp.kernel.org (Postfix) with ESMTPS id D4D4FC19421; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759937626; bh=e2ugSOI2UTAErCdXtASkJNADsZs45cfO9nbqKrgUZzA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ICZsUVwF0BwJMxJQpmWW5OqNoOYUeDZdjmM8CeQEQ4YsDjrWbtH3mLXF64+DnMkqd ZaUXwdUsYZnpT1cOWrYhC02Q3P3GiNYJ4Gd9dr+vOBsyDqvgMKl9R8qK4Pln125uMK 3JqAMblVmocsdYG4oyvrK0f9tKo4QT6t7v0sEw9odKF8gC/kApHVS3hpH7CXDHMwXQ aYh+ms22sqdGUq0aNT657qQa8FwrIVgvHtMrSFLudjIgoKfQ77xbT4pO0MTMdEkfCc 4VHJfSn6+uRNzznJgmBhamxqLpUSAKMcy0QOHkhi3ZfuP2H1UxQrc5tv/zBJ2tNPtP 9cCCa9ihkNJqg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBE57CCD188; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 08 Oct 2025 19:32:57 +0400 Subject: [PATCH v17 5/9] dt-bindings: pwm: qcom,ipq6018-pwm: Add compatible for ipq9574 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251008-ipq-pwm-v17-5-9bd43edfc7f7@outlook.com> References: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> In-Reply-To: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759937623; l=1000; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=hrkECPGJIlhb4smP284sXv3tC5v7hT/ab5fvLg2W1dU=; b=36g7JgZ2r2cBC71ovyzzWLy1PdMUxHvB9NOgJRIBxR3UjaNYQ9HfsrwJY8Xl67WlSXM6Hdyaj XKuQmkVmiORAh27hDo0ap1Y92DwqWyHvgWauVndQzX69gFRSuP45uiT X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ9574 SoC contains a PWM block which is exactly the same as the one found in IPQ6018. So let's add a compatible for IPQ9574 and use IPQ6018 as the fallback. Acked-by: Rob Herring (Arm) Signed-off-by: George Moussalem --- Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/= Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml index e00b9e01f4f89dd0d08610772c984a0e2725d154..48dd7d1b8f511b0dd2cbebc07f3= 3cafc3655ce50 100644 --- a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -16,6 +16,7 @@ properties: - enum: - qcom,ipq5018-pwm - qcom,ipq5332-pwm + - qcom,ipq9574-pwm - const: qcom,ipq6018-pwm - const: qcom,ipq6018-pwm =20 --=20 2.51.0 From nobody Mon Feb 9 03:30:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5464B2F998D; Wed, 8 Oct 2025 15:33:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; cv=none; b=TXL0VtQJ1jgb9HhytWapLoZsvwDY0iV7qKWIY2UpJKcGw+KpuWLbgzunNqAtYg/Yp76+HaoPvb0/IzBGNA48MJFjMyqA4nb9+GCtAuRbm5aE4SEltFjhTCKEKZeZ/qJSgjwASAxwAEgAdk3aDwDjhp8I5cShUdVwaMpcd2RuBRs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; c=relaxed/simple; bh=BH9RyEUffqjPp+Gnltyt4X5dVubCxy25UZTDkRJK8ss=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tnNN153gWz3SVEofPMsP2uypVkraEgQSI2az1NM+yiWh0/VTZHJpwupiYQ1c1zhqWxOr9n+kP80aJsXIPfbvFqU4mH1/4aRNaHb19VE6aGlPiM2x+Z6ZK21KSzESa1lIHjCuZvyQKZLFOA0BmasvlCJ7tAHCRUYwaCv7hdBnpmg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nLRi1kZj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nLRi1kZj" Received: by smtp.kernel.org (Postfix) with ESMTPS id E450BC116B1; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759937626; bh=BH9RyEUffqjPp+Gnltyt4X5dVubCxy25UZTDkRJK8ss=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=nLRi1kZj4xvK+iTdiR+NKkvqCSrgLaj+GxGISYWtepgzGDmFoIrdthb7uGWs6zRmq 2AtUOWampKKqHB+dgpjth23pJ1pkHHnVwyzuDfIuXWJ7GmF3nfBfHpkE/v2GAL9vJI dBB692aLBz1mW2BtoBuhtn+JFgRpGpS4Xh+MdrOc5g24+CFgn/6ZOPytKP2Gm1AuWy pfN4XmLFY+i1mUhyAAbHQGGAVQg3FRziUZYontfQn/UVzUbt57nzlhhPDoYtae02K8 ybsfNaWCLVUmQGJqRCjdR/DTiAN2kYPrR1+SN9tC6MzA6qrSxAJxJRxrKmasi9TYgH an9KOLBZTtIkA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBD82CCA472; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 08 Oct 2025 19:32:58 +0400 Subject: [PATCH v17 6/9] arm64: dts: qcom: ipq6018: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251008-ipq-pwm-v17-6-9bd43edfc7f7@outlook.com> References: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> In-Reply-To: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Devi Priya , Krzysztof Kozlowski , Baruch Siach X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759937623; l=1391; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=O41HNKdswyFzcZl8XVjha1wsITAQCaBZJ3Hx8/DgYw4=; b=+N86pOedhWoXNzBaY4DZ0LAbr2QHng2kRT/nWvhCFuf/05h2KftoaKvPrqJ9cgmYkXvIZ6Ed0 JOjXQMurxL9B3kNfSQh6wTNa3QyktpE8hbHbpdvm+7ASpr9UE2j+G4i X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: Devi Priya Describe the PWM block on IPQ6018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qc= om/ipq6018.dtsi index 40f1c262126eff3761430a47472b52d27f961040..7925c9a6b0dcff9e3157dd9de01= fbc2d240486a4 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -413,6 +413,16 @@ tcsr: syscon@1937000 { reg =3D <0x0 0x01937000 0x0 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq6018-pwm"; + reg =3D <0x0 0x01941010 0x0 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + usb2: usb@70f8800 { compatible =3D "qcom,ipq6018-dwc3", "qcom,dwc3"; reg =3D <0x0 0x070f8800 0x0 0x400>; --=20 2.51.0 From nobody Mon Feb 9 03:30:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 708912F9D83; Wed, 8 Oct 2025 15:33:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; cv=none; b=j5e7BN5Hw7dhKsk7XgUvtTA3U1d86F3dEzeZnDVsFjaRzweS2J/8+euNl6UlBKRQEB2ewRD5Tlad4zf8DU+7IUy9zTGqo8Rl70YwQ4g2899TbJlyiXcuqkOrJRtZawO/puRfcXiZSwCN3APvB0zwFZrhp73aCu4hTJPG2ye4FKs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; c=relaxed/simple; bh=eQHtovZz3J+7gu7HBlntuaYEQB1cnKnkmep03Dbkmg0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=l1v59/4nvUmylziN0fsokr45zhCcrkY1+qAnviULgt7XS/47KR8in9oUkcUz7BIJEYo0Wp873NoMo7jGMNbTh3iyIrgXh+lcjSjPHj5dzxRrgF47FR0+5fOhN+crlT+zxNU0TBIQxGrwES+IAlYdr4240z/qBgwj4ZZFwilcskc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UuBkelXj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UuBkelXj" Received: by smtp.kernel.org (Postfix) with ESMTPS id F1BD4C2BCAF; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759937627; bh=eQHtovZz3J+7gu7HBlntuaYEQB1cnKnkmep03Dbkmg0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=UuBkelXjEah3Ya4q0G2yUX1P+zOdMgaa3WIpPKwz6+k9UMi/558/isO0LPZDzVIT0 +mg0Z1h0Ped3qmeGjkjdVBki4aclM9u7NcRX5JAOF2zKoY8dE/tJPx/U2fxhsi5ld0 j6CqcZ4vmxVCxe7uqWpT8aS7XX98q+LqzT33bdMULmz3Y094THm//9Wo9P9pVlaZvt Yu7yKmnRsPniRWcm8XSByANsUpgF8WRrzCfdMeP3yiWk5ZxKXhLYTprsIYNoCfigz0 kf2Lj4FXAnlnYgGXpsoyCHR3e6Hk+HX2qu7iC//PdPQUeG2GZtxcNxGYLfW+3+BncH 99Y7KuaOfIAnw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E92E6CAC5BB; Wed, 8 Oct 2025 15:33:46 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 08 Oct 2025 19:32:59 +0400 Subject: [PATCH v17 7/9] arm64: dts: qcom: ipq5018: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251008-ipq-pwm-v17-7-9bd43edfc7f7@outlook.com> References: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> In-Reply-To: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759937623; l=1233; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=cPA8fq8v3fox0e7wzkxLxHKITff0qaTwjV7zqQLPPLc=; b=MnC5ttIB1kPiD72LlS4Js1HP1sbfZx5WSHY18v4U2PfTowdEzXlt/LNjDO22vnvwRqUk1JRVE 0VBTbswMQH7BwkkDCN6jlg5IHzIg6+4CipGT8zyjgWrc0shZNB+L3Fm X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ5018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index f024b3cba33f6100ac3f4d45598ff2356e026dcf..d4bdf2884aa7f73711cf8a37b7a= 4c4e7e54c503c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -453,6 +453,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq5018-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x7804000 0x1000>; --=20 2.51.0 From nobody Mon Feb 9 03:30:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7260A2FA0C6; Wed, 8 Oct 2025 15:33:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; cv=none; b=nq9aqvT7lDM5mGGg7+SqhfXUN20KYGgZdxtbmL8hoRIyVSYSl6Wk9/1Km0eoIWE3LnyB68rvkSlThHHKS8wV438zuVBedRlDvZ3odZ68DR+Kp5briqBeQ1xYg/mvufuvZMRuDD0pA1vCZ8kkPj6VQinpH1QROs0BjiyEUCcczlk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; c=relaxed/simple; bh=17jHRnynMi8fb/tCT5jWG4U5l21xzqOHR0+glWmEBMM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FlKA0UQqHQ3at2I5DAZ49QSHsb4fz5IP4hrV7jiElEJ7CIjzhui/dMZrgnlhRC8FBwHOfiR5bxD/+MlZlqJrq6XG7IbTGyLWA7quR1YIj4H3D4ms2huG38Z6Kf5mc5cVf1oHI7Zwl9/iGX2ZD3OcGOmzVG8AkMdmnFtL3Rfq2/k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WqOxRcfa; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WqOxRcfa" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0CB43C19422; Wed, 8 Oct 2025 15:33:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759937627; bh=17jHRnynMi8fb/tCT5jWG4U5l21xzqOHR0+glWmEBMM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WqOxRcfaIk4WYLB8XWdY7u8ePBast8t8HTlXMT2qjjdatAEnfWM14QNjQdyJ3QAVm I9b8ZQadZ+A2oOT+dFXvgTRktXOQfabeyEA/LvWkRdUfYWJv9k8/PJ1ypGK8XKiCYm ZZwedHqaGe7r158+EdlptQw8on+KGqAxUmZ2Od1RJYDIb/Y7bN1vChOsojbEBQNf5N 8ZARxD++9bcjmyNECXcM3nP0UacAcmwjn0xzJaKQVHjM/rJIp6iNUburB2BtfEZ1h4 8x4DwdwB77Vfxt1EZlii6CR1X9o/mga4Cvi0BpfTikhHbdBjdRSLkvkHfH7nHFv/QO 5pBITMunfLaYw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03825CCD183; Wed, 8 Oct 2025 15:33:47 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 08 Oct 2025 19:33:00 +0400 Subject: [PATCH v17 8/9] arm64: dts: qcom: ipq5332: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251008-ipq-pwm-v17-8-9bd43edfc7f7@outlook.com> References: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> In-Reply-To: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759937623; l=1253; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=e3rNVi2zON87okZlfd1mnPPujU2uXXwCmlIqEOFb5CY=; b=fYPZ95JzsPZMYOOb124LNlFTu7TbrfUF7vppu3WzXVTi6VknWvLdUVZWkmUl9CBztwaP4GpCY SROtHqXbWoGBgdMrREXu81hrTOFILb1kAT76FZgYeZX3yCiXjTuRvcZ X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ5332. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qc= om/ipq5332.dtsi index 45fc512a3bab221c0d99f819294abf63369987da..4ff6e38521ed94fac0f4caac5c5= b0d9be3704d7e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -334,6 +334,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq5332-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + sdhc: mmc@7804000 { compatible =3D "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, <0x07805000 0x1000>; --=20 2.51.0 From nobody Mon Feb 9 03:30:34 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5458E2F998A; Wed, 8 Oct 2025 15:33:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; cv=none; b=tmV7Q6ZbQ78NwM+RhHREPgJ9GolIwaJcUTXG6sznqopFogA8d9/Vu0In+cx6aLf8010+7vcoy2ZC0UJDgcdoJXJ/+RCKqJgMRfDw7deUMG3C6HJO+H+bewkM7laBvKse1vuHV6iAO3oeDD7rD1KN0Ldqy+dmXjBS+GqGOb4vtR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759937627; c=relaxed/simple; bh=eVOsFH8osOeZ8GHSlQlqi0o9HHh6RBAnnXxTD6MchR0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XhmN5IfDYuZh1kJJTsv42kUDqXcmHE6QESphXDJ5ogSzgHRY6W/fATWhxB6b8nEeUACREsdpkM7W2QO0QC8vHRS4uw+4joe0GaObY/2CFqhige+KJzpBTAw+Si6N6KET8X6o6yCqRHkPPLqzUL0eiQeUgHcKtJGxi25lJHybJQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JOvkIdvK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JOvkIdvK" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1C4EEC116D0; Wed, 8 Oct 2025 15:33:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759937627; bh=eVOsFH8osOeZ8GHSlQlqi0o9HHh6RBAnnXxTD6MchR0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=JOvkIdvKAasO3xCoq/L5vJozz+ODbzwBc0z5L17uzeoK2L+bffNxUdtXm8sBNiFxs 4Ta5uLvWKrFBIzDWyDaJHHy3ENMR0l7Ebavm8rk2IP//Sn4LKIdG/L9a1H1Erelq5m XrZDzAMYXsB3ZrCRhTLN1eF0d251rWveB1gdA0+iXaJEtGtvIKDcQmLz0zKoFmIlZE OLdjrpMPQhU0GXpxl61+qcCs3poHTTha50DDMU9eT0gJqMrMxhA+7DZKWHaQKVfFda XHu8OUmigZPw/KrrLFJhmzKV3DiWTAkao0YWs4caur94kOlBOve/eH5tNB3OJVRR0a k1eJPQp6d939A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 117B4CCA470; Wed, 8 Oct 2025 15:33:47 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 08 Oct 2025 19:33:01 +0400 Subject: [PATCH v17 9/9] arm64: dts: qcom: ipq9574: add pwm node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251008-ipq-pwm-v17-9-9bd43edfc7f7@outlook.com> References: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> In-Reply-To: <20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Baruch Siach , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, George Moussalem , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759937623; l=1234; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=qc4VIzmfGZ/Xd+TOMpfJif2wj3plsSY0LnXsUU/Cm6A=; b=kdV2vbA1Dga3vyES71ONOlSMDOa1obqQ9fBP2whZgu3oe3HCJspmEAOggz5qK9ydJxnCXqMgD 3z1S8ogGsRuCv9c2BeNpVoRQ2k13z4v7IvAoO6q5cIhZ0fyXRIZZfWz X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Describe the PWM block on IPQ9574. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qc= om/ipq9574.dtsi index 86c9cb9fffc98fdd1b0b08e81428ce5e7bb87e17..8dba80d76d609a317a66f514c64= ab8f5612e6938 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -449,6 +449,16 @@ tcsr: syscon@1937000 { reg =3D <0x01937000 0x21000>; }; =20 + pwm: pwm@1941010 { + compatible =3D "qcom,ipq9574-pwm", "qcom,ipq6018-pwm"; + reg =3D <0x01941010 0x20>; + clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks =3D <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates =3D <100000000>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + sdhc_1: mmc@7804000 { compatible =3D "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, --=20 2.51.0