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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2025 15:35:52.8534 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 99597c52-457f-47ef-7aba-08de05b73337 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B9C.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB10242 Content-Type: text/plain; charset="utf-8" Some system register field encodings change based on the available and in-use architecture features. In order to support these different field encodings, introduce the Feat descriptor (Feat, ElseFeat, EndFeat) for describing such sysregs. The Feat descriptor can be used in the following way (Feat acts as both an if and an else-if): Sysreg EXAMPLE 0 1 2 3 4 Feat FEAT_A Field 63:0 Foo Feat FEAT_B Field 63:1 Bar Res0 0 ElseFeat Field 63:0 Baz EndFeat EndSysreg This will generate a single set of system register encodings (REG_, SYS_, ...), and then generate three sets of field definitions for the system register called EXAMPLE. The first set is prefixed by FEAT_A, e.g. FEAT_A_EXAMPLE_Foo. The second set is prefixed by FEAT_B, e.g., FEAT_B_EXAMPLE_Bar. The third set is not given a prefix at all, e.g. EXAMPLE_BAZ. For each set, a corresponding set of defines for Res0, Res1, and Unkn is generated. The intent for the final prefix-less ElseFeat is for describing default or legacy field encodings. This ensure that new feature-conditional encodings can be added to already-present sysregs without affecting existing legacy code. The Feat descriptor can be used within Sysreg or SysregFields blocks. Field, Res0, Res1, Unkn, Rax, SignedEnum, Enum can all be used within a Feat block. Fields and Mapping can not. Fields that vary with features must be described as part of a SysregFields block, instead. Mappings, which are just a code comment, make little sense in this context, and have hence not been included. There are no changes to the generated system register definitions as part of this change. Signed-off-by: Sascha Bischoff --- arch/arm64/tools/gen-sysreg.awk | 148 ++++++++++++++++++++++---------- 1 file changed, 104 insertions(+), 44 deletions(-) diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.= awk index f2a1732cb1f63..c1bb6d5087a99 100755 --- a/arch/arm64/tools/gen-sysreg.awk +++ b/arch/arm64/tools/gen-sysreg.awk @@ -44,23 +44,35 @@ function expect_fields(nf) { =20 # Print a CPP macro definition, padded with spaces so that the macro bodies # line up in a column -function define(name, val) { - printf "%-56s%s\n", "#define " name, val +function define(feat, name, val) { + printf "%-56s%s\n", "#define " feat name, val } =20 # Print standard BITMASK/SHIFT/WIDTH CPP definitions for a field -function define_field(reg, field, msb, lsb) { - define(reg "_" field, "GENMASK(" msb ", " lsb ")") - define(reg "_" field "_MASK", "GENMASK(" msb ", " lsb ")") - define(reg "_" field "_SHIFT", lsb) - define(reg "_" field "_WIDTH", msb - lsb + 1) +function define_field(feat, reg, field, msb, lsb) { + define(feat, reg "_" field, "GENMASK(" msb ", " lsb ")") + define(feat, reg "_" field "_MASK", "GENMASK(" msb ", " lsb ")") + define(feat, reg "_" field "_SHIFT", lsb) + define(feat, reg "_" field "_WIDTH", msb - lsb + 1) } =20 # Print a field _SIGNED definition for a field -function define_field_sign(reg, field, sign) { - define(reg "_" field "_SIGNED", sign) +function define_field_sign(feat, reg, field, sign) { + define(feat, reg "_" field "_SIGNED", sign) } =20 +# Print the Res0, Res1, Unkn masks +function define_resx_unkn(feat, reg, res0, res1, unkn) { + if (res0 !=3D null) + define(feat, reg "_RES0", "(" res0 ")") + if (res1 !=3D null) + define(feat, reg "_RES1", "(" res1 ")") + if (unkn !=3D null) + define(feat, reg "_UNKN", "(" unkn ")") + if (res0 !=3D null || res1 !=3D null || unkn !=3D null) + print "" + } + # Parse a "[:]" string into the global variables @msb and @lsb function parse_bitdef(reg, field, bitdef, _bits) { @@ -132,10 +144,7 @@ $1 =3D=3D "EndSysregFields" && block_current() =3D=3D = "SysregFields" { if (next_bit > 0) fatal("Unspecified bits in " reg) =20 - define(reg "_RES0", "(" res0 ")") - define(reg "_RES1", "(" res1 ")") - define(reg "_UNKN", "(" unkn ")") - print "" + define_resx_unkn(feat, reg, res0, res1, unkn) =20 reg =3D null res0 =3D null @@ -162,14 +171,16 @@ $1 =3D=3D "Sysreg" && block_current() =3D=3D "Root" { res1 =3D "UL(0)" unkn =3D "UL(0)" =20 - define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2) - define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")") + feat =3D null + + define(feat, "REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2) + define(feat, "SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " o= p2 ")") =20 - define("SYS_" reg "_Op0", op0) - define("SYS_" reg "_Op1", op1) - define("SYS_" reg "_CRn", crn) - define("SYS_" reg "_CRm", crm) - define("SYS_" reg "_Op2", op2) + define(feat, "SYS_" reg "_Op0", op0) + define(feat, "SYS_" reg "_Op1", op1) + define(feat, "SYS_" reg "_CRn", crn) + define(feat, "SYS_" reg "_CRm", crm) + define(feat, "SYS_" reg "_Op2", op2) =20 print "" =20 @@ -183,14 +194,7 @@ $1 =3D=3D "EndSysreg" && block_current() =3D=3D "Sysre= g" { if (next_bit > 0) fatal("Unspecified bits in " reg) =20 - if (res0 !=3D null) - define(reg "_RES0", "(" res0 ")") - if (res1 !=3D null) - define(reg "_RES1", "(" res1 ")") - if (unkn !=3D null) - define(reg "_UNKN", "(" unkn ")") - if (res0 !=3D null || res1 !=3D null || unkn !=3D null) - print "" + define_resx_unkn(feat, reg, res0, res1, unkn) =20 reg =3D null op0 =3D null @@ -201,6 +205,7 @@ $1 =3D=3D "EndSysreg" && block_current() =3D=3D "Sysreg= " { res0 =3D null res1 =3D null unkn =3D null + feat =3D null =20 block_pop() next @@ -225,8 +230,7 @@ $1 =3D=3D "EndSysreg" && block_current() =3D=3D "Sysreg= " { next } =20 - -$1 =3D=3D "Res0" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields") { +$1 =3D=3D "Res0" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields" || block_current() =3D=3D "Feat") { expect_fields(2) parse_bitdef(reg, "RES0", $2) field =3D "RES0_" msb "_" lsb @@ -236,7 +240,7 @@ $1 =3D=3D "Res0" && (block_current() =3D=3D "Sysreg" ||= block_current() =3D=3D "SysregFields next } =20 -$1 =3D=3D "Res1" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields") { +$1 =3D=3D "Res1" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields" || block_current() =3D=3D "Feat") { expect_fields(2) parse_bitdef(reg, "RES1", $2) field =3D "RES1_" msb "_" lsb @@ -246,7 +250,7 @@ $1 =3D=3D "Res1" && (block_current() =3D=3D "Sysreg" ||= block_current() =3D=3D "SysregFields next } =20 -$1 =3D=3D "Unkn" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields") { +$1 =3D=3D "Unkn" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields" || block_current() =3D=3D "Feat") { expect_fields(2) parse_bitdef(reg, "UNKN", $2) field =3D "UNKN_" msb "_" lsb @@ -256,58 +260,58 @@ $1 =3D=3D "Unkn" && (block_current() =3D=3D "Sysreg" = || block_current() =3D=3D "SysregFields next } =20 -$1 =3D=3D "Field" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields") { +$1 =3D=3D "Field" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields" || block_current() =3D=3D "Feat") { expect_fields(3) field =3D $3 parse_bitdef(reg, field, $2) =20 - define_field(reg, field, msb, lsb) + define_field(feat, reg, field, msb, lsb) print "" =20 next } =20 -$1 =3D=3D "Raz" && (block_current() =3D=3D "Sysreg" || block_current() =3D= =3D "SysregFields") { +$1 =3D=3D "Raz" && (block_current() =3D=3D "Sysreg" || block_current() =3D= =3D "SysregFields" || block_current() =3D=3D "Feat") { expect_fields(2) parse_bitdef(reg, field, $2) =20 next } =20 -$1 =3D=3D "SignedEnum" && (block_current() =3D=3D "Sysreg" || block_curren= t() =3D=3D "SysregFields") { +$1 =3D=3D "SignedEnum" && (block_current() =3D=3D "Sysreg" || block_curren= t() =3D=3D "SysregFields" || block_current() =3D=3D "Feat") { block_push("Enum") =20 expect_fields(3) field =3D $3 parse_bitdef(reg, field, $2) =20 - define_field(reg, field, msb, lsb) - define_field_sign(reg, field, "true") + define_field(feat, reg, field, msb, lsb) + define_field_sign(feat, reg, field, "true") =20 next } =20 -$1 =3D=3D "UnsignedEnum" && (block_current() =3D=3D "Sysreg" || block_curr= ent() =3D=3D "SysregFields") { +$1 =3D=3D "UnsignedEnum" && (block_current() =3D=3D "Sysreg" || block_curr= ent() =3D=3D "SysregFields" || block_current() =3D=3D "Feat") { block_push("Enum") =20 expect_fields(3) field =3D $3 parse_bitdef(reg, field, $2) =20 - define_field(reg, field, msb, lsb) - define_field_sign(reg, field, "false") + define_field(feat, reg, field, msb, lsb) + define_field_sign(feat, reg, field, "false") =20 next } =20 -$1 =3D=3D "Enum" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields") { +$1 =3D=3D "Enum" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields" || block_current() =3D=3D "Feat") { block_push("Enum") =20 expect_fields(3) field =3D $3 parse_bitdef(reg, field, $2) =20 - define_field(reg, field, msb, lsb) + define_field(feat, reg, field, msb, lsb) =20 next } @@ -329,7 +333,63 @@ $1 =3D=3D "EndEnum" && block_current() =3D=3D "Enum" { val =3D $1 name =3D $2 =20 - define(reg "_" field "_" name, "UL(" val ")") + define(feat, reg "_" field "_" name, "UL(" val ")") + next +} + +$1 =3D=3D "Feat" && (block_current() =3D=3D "Sysreg" || block_current() = =3D=3D "SysregFields" || block_current() =3D=3D "Feat") { + # Don't push a new block if we're already in a Feat + # block. This is to support constructs such as: + # Feat FEAT_A + # ... + # Feat FEAT_B + # ... + # ElseFeat + # ... + # EndFeat + if (block_current() !=3D "Feat") + block_push("Feat") + else + define_resx_unkn(feat, reg, res0, res1, unkn) + + expect_fields(2) + feat =3D $2 "_" + + next_bit =3D 63 + + res0 =3D "UL(0)" + res1 =3D "UL(0)" + unkn =3D "UL(0)" + + next +} + +$1 =3D=3D "ElseFeat" && block_current() =3D=3D "Feat" { + expect_fields(1) + + define_resx_unkn(feat, reg, res0, res1, unkn) + + res0 =3D "UL(0)" + res1 =3D "UL(0)" + unkn =3D "UL(0)" + feat =3D null + next_bit =3D 63 + + next +} + +$1 =3D=3D "EndFeat" && block_current() =3D=3D "Feat" { + expect_fields(1) + + define_resx_unkn(feat, reg, res0, res1, unkn) + + res0 =3D null + res1 =3D null + unkn =3D null + feat =3D null + + block_pop() + next } =20 --=20 2.34.1