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[144.49.247.126]) by smtp-relay.gmail.com with ESMTPS id ada2fe7eead31-5d5d39db9ccsm331891137.5.2025.10.07.07.05.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Oct 2025 07:05:19 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qv1-f72.google.com with SMTP id 6a1803df08f44-803339f345bso92134156d6.2 for ; Tue, 07 Oct 2025 07:05:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1759845919; x=1760450719; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nQDseboPoN7tnrpn/frcsPgqqEsYL+e4oPXMaYNhgu8=; b=f4pyrBXCq3KVWz+W4F3TmU/i/2yO7t1WapWnmpP2DbNsHc4dFczTu3AyMKO3VdU9we Y/HJrn4nBEclBHJwPBfonuKAj938o/myXYp1OV2gNL+NjzsuVytxnqZvCsonjk7zIclW fP492tnFc2dy5+4rl6tL9VWxx5GtjIQ5JzUAY= X-Forwarded-Encrypted: i=1; AJvYcCXbe1Nd358EdhbU3//rMinmm8R9sj7OrlXLSjccaY+8nL2yoWHAATikKCquQrCx0Tt3PJSiJyHyIl9qn+M=@vger.kernel.org X-Received: by 2002:a05:6214:2682:b0:874:3018:f958 with SMTP id 6a1803df08f44-879dc77b8e8mr209784056d6.5.1759845918369; Tue, 07 Oct 2025 07:05:18 -0700 (PDT) X-Received: by 2002:a05:6214:2682:b0:874:3018:f958 with SMTP id 6a1803df08f44-879dc77b8e8mr209783356d6.5.1759845917674; Tue, 07 Oct 2025 07:05:17 -0700 (PDT) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-878bae60b67sm142718956d6.9.2025.10.07.07.05.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Oct 2025 07:05:17 -0700 (PDT) From: Kamal Dasu To: andersson@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Kamal Dasu Subject: [PATCH v2 5/5] mmc: sdhci-brcmstb: save and restore registers during PM Date: Tue, 7 Oct 2025 10:04:34 -0400 Message-Id: <20251007140434.606051-7-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251007140434.606051-1-kamal.dasu@broadcom.com> References: <20251007140434.606051-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Added support to save and restore registers that are critical during PM. Signed-off-by: Kamal Dasu Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-brcmstb.c | 112 +++++++++++++++++++++++++++++-- 1 file changed, 107 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcm= stb.c index 42709ca8111d..7de395c86f2f 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -38,28 +38,109 @@ #define SDIO_CFG_OP_DLY_DEFAULT 0x80000003 #define SDIO_CFG_CQ_CAPABILITY 0x4c #define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) +#define SDIO_CFG_SD_PIN_SEL 0x44 +#define SDIO_CFG_V1_SD_PIN_SEL 0x54 +#define SDIO_CFG_PHY_SW_MODE_0_RX_CTRL 0x7C #define SDIO_CFG_MAX_50MHZ_MODE 0x1ac #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) =20 +#define SDIO_BOOT_MAIN_CTL 0x0 + #define MMC_CAP_HSE_MASK (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V) /* Select all SD UHS type I SDR speed above 50MB/s */ #define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) =20 -struct sdhci_brcmstb_priv { - void __iomem *cfg_regs; - unsigned int flags; - struct clk *base_clk; - u32 base_freq_hz; +enum cfg_core_ver { + SDIO_CFG_CORE_V1 =3D 1, + SDIO_CFG_CORE_V2, +}; + +struct sdhci_brcmstb_saved_regs { + u32 sd_pin_sel; + u32 phy_sw_mode0_rxctrl; + u32 max_50mhz_mode; + u32 boot_main_ctl; }; =20 struct brcmstb_match_priv { void (*cfginit)(struct sdhci_host *host); void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); + void (*save_restore_regs)(struct mmc_host *mmc, int save); struct sdhci_ops *ops; const unsigned int flags; }; =20 +struct sdhci_brcmstb_priv { + void __iomem *cfg_regs; + void __iomem *boot_regs; + struct sdhci_brcmstb_saved_regs saved_regs; + unsigned int flags; + struct clk *base_clk; + u32 base_freq_hz; + const struct brcmstb_match_priv *match_priv; +}; + +static void sdhci_brcmstb_save_regs(struct mmc_host *mmc, enum cfg_core_ve= r ver) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + struct sdhci_brcmstb_saved_regs *sr =3D &priv->saved_regs; + void __iomem *cr =3D priv->cfg_regs; + bool is_emmc =3D mmc->caps & MMC_CAP_NONREMOVABLE; + + if (is_emmc && priv->boot_regs) + sr->boot_main_ctl =3D readl(priv->boot_regs + SDIO_BOOT_MAIN_CTL); + + if (ver =3D=3D SDIO_CFG_CORE_V1) { + sr->sd_pin_sel =3D readl(cr + SDIO_CFG_V1_SD_PIN_SEL); + return; + } + + sr->sd_pin_sel =3D readl(cr + SDIO_CFG_SD_PIN_SEL); + sr->phy_sw_mode0_rxctrl =3D readl(cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL); + sr->max_50mhz_mode =3D readl(cr + SDIO_CFG_MAX_50MHZ_MODE); +} + +static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, enum cfg_core= _ver ver) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + struct sdhci_brcmstb_saved_regs *sr =3D &priv->saved_regs; + void __iomem *cr =3D priv->cfg_regs; + bool is_emmc =3D mmc->caps & MMC_CAP_NONREMOVABLE; + + if (is_emmc && priv->boot_regs) + writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL); + + if (ver =3D=3D SDIO_CFG_CORE_V1) { + writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL); + return; + } + + writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL); + writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL); + writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE); +} + +static void sdhci_brcmstb_save_restore_regs_v1(struct mmc_host *mmc, int s= ave) +{ + if (save) + sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V1); + else + sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V1); +} + +static void sdhci_brcmstb_save_restore_regs_v2(struct mmc_host *mmc, int s= ave) +{ + if (save) + sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V2); + else + sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V2); +} + static inline void enable_clock_gating(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); @@ -306,22 +387,26 @@ static struct brcmstb_match_priv match_priv_74371 =3D= { =20 static struct brcmstb_match_priv match_priv_7445 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, + .save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v1, .ops =3D &sdhci_brcmstb_ops, }; =20 static struct brcmstb_match_priv match_priv_72116 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, + .save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v1, .ops =3D &sdhci_brcmstb_ops_72116, }; =20 static const struct brcmstb_match_priv match_priv_7216 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, + .save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v2, .hs400es =3D sdhci_brcmstb_hs400es, .ops =3D &sdhci_brcmstb_ops_7216, }; =20 static struct brcmstb_match_priv match_priv_74165b0 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, + .save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v2, .hs400es =3D sdhci_brcmstb_hs400es, .ops =3D &sdhci_brcmstb_ops_74165b0, }; @@ -429,6 +514,7 @@ static int sdhci_brcmstb_probe(struct platform_device *= pdev) =20 pltfm_host =3D sdhci_priv(host); priv =3D sdhci_pltfm_priv(pltfm_host); + priv->match_priv =3D match->data; if (device_property_read_bool(&pdev->dev, "supports-cqe")) { priv->flags |=3D BRCMSTB_PRIV_FLAGS_HAS_CQE; match_priv->ops->irq =3D sdhci_brcmstb_cqhci_irq; @@ -446,6 +532,13 @@ static int sdhci_brcmstb_probe(struct platform_device = *pdev) if (res) goto err; =20 + /* map non-standard BOOT registers if present */ + if (host->mmc->caps & MMC_CAP_NONREMOVABLE) { + priv->boot_regs =3D devm_platform_get_and_ioremap_resource(pdev, 2, NULL= ); + if (IS_ERR(priv->boot_regs)) + priv->boot_regs =3D NULL; + } + /* * Automatic clock gating does not work for SD cards that may * voltage switch so only enable it for non-removable devices. @@ -536,8 +629,13 @@ static int sdhci_brcmstb_suspend(struct device *dev) struct sdhci_host *host =3D dev_get_drvdata(dev); struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + const struct brcmstb_match_priv *match_priv =3D priv->match_priv; + int ret; =20 + if (match_priv->save_restore_regs) + match_priv->save_restore_regs(host->mmc, 1); + clk_disable_unprepare(priv->base_clk); if (host->mmc->caps2 & MMC_CAP2_CQE) { ret =3D cqhci_suspend(host->mmc); @@ -553,6 +651,7 @@ static int sdhci_brcmstb_resume(struct device *dev) struct sdhci_host *host =3D dev_get_drvdata(dev); struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + const struct brcmstb_match_priv *match_priv =3D priv->match_priv; int ret; =20 ret =3D sdhci_pltfm_resume(dev); @@ -569,6 +668,9 @@ static int sdhci_brcmstb_resume(struct device *dev) ret =3D clk_set_rate(priv->base_clk, priv->base_freq_hz); } =20 + if (match_priv->save_restore_regs) + match_priv->save_restore_regs(host->mmc, 0); + if (host->mmc->caps2 & MMC_CAP2_CQE) ret =3D cqhci_resume(host->mmc); =20 --=20 2.34.1