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[144.49.247.19]) by smtp-relay.gmail.com with ESMTPS id 98e67ed59e1d1-339b4f2291esm1284059a91.5.2025.10.07.07.04.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Oct 2025 07:04:52 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qv1-f69.google.com with SMTP id 6a1803df08f44-7946137e7c2so185607276d6.0 for ; Tue, 07 Oct 2025 07:04:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1759845891; x=1760450691; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Px5PBDWoNSxvQicSvlQGDgd/7ifZnaEp1y0M1jncvfs=; b=KwvfG/PR0ngd3PbHlS61WAjVgazkNsaKQHwp63pzFb30dB4aJMBCvcxcf15UYTrC8G NonoFNs8YUSPK4zDQrG2F3u4nlWOWTPF2vYwQNmAy/OWNT+w8ZMWWZHNTDv0wmY7WrIH yJDzxtN4eNH/kcDzw2U7edapQO9HTw2D1CG+U= X-Forwarded-Encrypted: i=1; AJvYcCUGJU/12nq7Kp9BoXlMjtb9sEHCTZ6hwtUdCoVddZnvfBsPGhXyOVXGRPqBe9IGLxTwWxnpnDQkD8UzHrU=@vger.kernel.org X-Received: by 2002:a05:6214:f6d:b0:792:61c0:beb0 with SMTP id 6a1803df08f44-879dc87f7c2mr226139086d6.67.1759845891176; Tue, 07 Oct 2025 07:04:51 -0700 (PDT) X-Received: by 2002:a05:6214:f6d:b0:792:61c0:beb0 with SMTP id 6a1803df08f44-879dc87f7c2mr226137866d6.67.1759845890256; Tue, 07 Oct 2025 07:04:50 -0700 (PDT) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-878bae60b67sm142718956d6.9.2025.10.07.07.04.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Oct 2025 07:04:49 -0700 (PDT) From: Kamal Dasu To: andersson@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Kamal Dasu , Conor Dooley Subject: [PATCH v2 1/5] dt-bindings: mmc: Add support for BCM72116 and BCM74371 SD host controller Date: Tue, 7 Oct 2025 10:04:29 -0400 Message-Id: <20251007140434.606051-2-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251007140434.606051-1-kamal.dasu@broadcom.com> References: <20251007140434.606051-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Updating compatibility to support BCM72116 and BCM74371 SD host controller similar to other settop SoCs. Signed-off-by: Kamal Dasu Reviewed-by: Florian Fainelli Acked-by: Conor Dooley --- Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml = b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index eee6be7a7867..720d0762078f 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -21,9 +21,11 @@ properties: - items: - enum: - brcm,bcm2712-sdhci + - brcm,bcm72116-sdhci - brcm,bcm74165b0-sdhci - brcm,bcm7445-sdhci - brcm,bcm7425-sdhci + - brcm,bcm74371-sdhci - const: brcm,sdhci-brcmstb =20 reg: --=20 2.34.1 From nobody Sun Feb 8 02:56:15 2026 Received: from mail-yx1-f97.google.com (mail-yx1-f97.google.com [74.125.224.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B9252E1C7B for ; Tue, 7 Oct 2025 14:04:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.224.97 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759845900; cv=none; b=tNDL0D6DPGulr4tDNCfBj+9q9aIOcsLZB6cjRZpDgs6X/wnskjwq9wP64+VuChfITfDIdpLOCu8zV6RP84JIW86bVseg2djhweRdggjWuHxMv5hUJ8FJeUwH6f+dY/jgXivZKB/NcebJDZfzecgsULv8rAZWKjvKyhidFavl4wQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759845900; c=relaxed/simple; bh=vUUmEvlmkeV1irok1/nIhqLFK/Atv2L+zIdkEFj6r50=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kk+vYE2dsSkuKoVyx8u/hpRlqKndd8QpH00mL17cnSAnZoshteGG9tlpxXwnTrmZP7Gz7l7+vi2Yw1CqL9pvEIGbQRQSt3aT8O8GgQrsiNeYvrIuVG6VdSj2T8vbJFTSeVv4C3WQFweLUQIqp/IlHimivpAEMZ0jm4pwficIDYQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=NuoqihyM; arc=none smtp.client-ip=74.125.224.97 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="NuoqihyM" Received: by mail-yx1-f97.google.com with SMTP id 956f58d0204a3-63bcdf5f241so4790208d50.0 for ; Tue, 07 Oct 2025 07:04:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759845898; x=1760450698; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=SzHMYfimzskmCvhQZFOQq3Y8wAS1gFZFKB5XWvB1gEs=; b=pI2BN5m71RULZ8bT4AtOUr6+WsK0PXGrZRc6a7TYCDQ/0ohuUuLdWIwda0WpbWfqw+ KRZZWpDQbA0rvY86QjH+Jv+XrSCP1ipNfTjuJaHHy0iLzuovTWWvylDEMlvjUobwret3 u43FTedRVi+yvZv150nsHya2Xj+550wu9SfWZ2aC+27cCnDCSgJ4HKW33idmbQT5nKcA foihKVTTmFHv0uZTW0z5uPD+iMJeHRL+NjSNZW5uhucrY3eJT/BlGZSUTtRIaj89jUYh N75GNJ06RSv5WOinHYiBdVgPt6Zam3vINbdQn0sua8Fg0oXSl9Cc388YBjrZJXLqAuCR RIfg== X-Forwarded-Encrypted: i=1; AJvYcCW81z8G1HIn+zRHG7IPNwDYDHN8KjaUKkdpaZli996sHCahfI0JXiLksQmHtyBInCrWgPjYjd0KN1J1WFM=@vger.kernel.org X-Gm-Message-State: AOJu0YypMiafSAgLF9GsWjE3cFxkdose1+NnLUdFg9qk5FyKEIad8Dwo nsb9LX9OlaTPREdDFpNhGFWOUCri7AByVfHX0JA0RpAHsLPpaiZsrK62yv0LOtrspO904tSes3Y qGcHoYVjoNMIN0Lleg7ox5tW/O7viyKevqM7ekH73iYf4KRxWjahvrh+1c4AoDxafOecg3NM3b5 +G1mDHvx5NBR/sTIlapw6czeZhqFMHoFtquE0GJsPSa32iAQG1/WG1HAesP3+ZXGtBOji5vwpbh 5opYfiU/MpdQJaZ X-Gm-Gg: ASbGncsicsVdgLP+jITif4ECoS/OA4qq1/J1uTUm5MawluM0+18HGSW2msv41sJ/a3W HP+j49lBz5NbWw9Bm/6CifAn5LEZmOv/MvS/21diPHmcppeDiCMlhc18cBONIKyogZej6uQs+Br fBzjCo55pA6o9KllNB9pF/ltOHtwUIhd6DlLjEb8ZD8mWZ5liKxKqk/bxEvguebnwVZuzdEi5Ea ZTa/JN72yDnyruvXIvZSYSUa6ffXHiown4/VZ8JIi80Ms0RJzzDGizvoAZk3RJWuD8N3WDgmLAt tw3LIGM16xhzABkIUL9AdiJNCC+w44uhmWwGyyYzg5giF6Jyg/Oy7FY/nVTqSz2imN2+qk3j3dT m6Z+60Nitp+y0+LVIst+ch6gnTGTZ+zClbR0stepC7IXbmp23+AGWW91bshqkbyi50YeRy42dfj W/KTEs X-Google-Smtp-Source: AGHT+IEk52MJRiKrgXLhdgDjJfb4X1mQwpb9umLnbPvpKmgAVPR4ndWlrP1zBg2fo5bU+ehTTYesxFeq4R17 X-Received: by 2002:a53:dd03:0:b0:63b:822c:449a with SMTP id 956f58d0204a3-63cbe0d3a50mr2963475d50.16.1759845897713; Tue, 07 Oct 2025 07:04:57 -0700 (PDT) Received: from smtp-us-east1-p01-i01-si01.dlp.protect.broadcom.com (address-144-49-247-126.dlp.protect.broadcom.com. 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Signed-off-by: Kamal Dasu Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-brcmstb.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcm= stb.c index efc2f3bdc631..f81cc1889ac9 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -31,13 +31,11 @@ =20 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 =20 -#define SDIO_CFG_CQ_CAPABILITY 0x4c -#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) - #define SDIO_CFG_CTRL 0x0 #define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) #define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) - +#define SDIO_CFG_CQ_CAPABILITY 0x4c +#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) #define SDIO_CFG_MAX_50MHZ_MODE 0x1ac #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) --=20 2.34.1 From nobody Sun Feb 8 02:56:15 2026 Received: from mail-oa1-f97.google.com (mail-oa1-f97.google.com [209.85.160.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E62CE2E1C7B for ; Tue, 7 Oct 2025 14:05:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.97 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759845907; cv=none; b=N8nMBRveylgjsZJbf09qQEPPH9wXW1BsTG20nuhl+aFAKH4fZ6dr3AN9xCvJTaa0lOR2cCe/y46Ya0/6WALKAEDRk+4HhY+KfQWQxvENCsnvz2YlPDUohcmmjKw1RiFEjCGt00qGTk6PnuKaPMGKrB1+D+8t7mKJwR7T/nrcRSk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759845907; c=relaxed/simple; bh=1i3B2dKT5sbTWo1nJf5tI4NTlUOkK2mEIdt9GtsoDag=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pvX5mY1ZHoJXX2NhQA2NUj6VK5K2SyMa4kQfFvX1NYO0SAX6m39DZbKOABi+HlekHj7REuAn3ejiFkaIu/S+uj3/fo9IwiP0dfrCGDEyHuMFkaGNjKkXjyVb/9JEgLjuVhU4i4T6Cy9ybYDVHELa0E7iGNnjrs8/JcgQA8Issio= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=GUvzSFsz; arc=none smtp.client-ip=209.85.160.97 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="GUvzSFsz" Received: by mail-oa1-f97.google.com with SMTP id 586e51a60fabf-394587df7c4so3135376fac.2 for ; Tue, 07 Oct 2025 07:05:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759845905; x=1760450705; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=rEmNG5dHeCrJHUC2bFy2N+BBQV+BhaaczeWYkzApDTU=; b=mgUKdmmJX7qLH0DCuHfELxww8nZh/51HNIzUTXG3GHspXjRDdnvhqtsVmi97MHnlad s30zVAgJeJ3fgcTm1ewlyWGwtUII3VAgGu+7dE24vH8zqWRPBP1pVU1PLzuj5NeR58/K uctc53QI5FziXMy3Hlo3ILkNqegTi5DStK1JBPTKifnTCKOCPDyYJA7/aD1rBH+NcbHU erRflOfmBvjPRe5bOE3zuL3y9qg2f3z1y4ActeipDYcb1PmmOjPXjoz0tEwzPOOqdK1f v27re65fk9ajghHL4VqnBHr/HxufgWgPVokaMg8YEkEOVf018LNbN/4UreEbtt20JbRH zQWw== X-Forwarded-Encrypted: i=1; AJvYcCV5q6Di3waREllOLhELM4OzkK+c6IS+ZFX4aWjCMF+h20lvMZ3SK03WuFDK2wzDahcjp5Rob8pt37U5iLs=@vger.kernel.org X-Gm-Message-State: AOJu0YzbUxAtdEWDUV+RM/5xfJ6B2l8JG1UtYkDrljBt3Z9Giq3AOO/D 3tUkWvaGfvtpCEI4d7TocDpC7kjAnPaIb7xlUNJXqz07l6TwfCFf1UAao4fjZDl5PMxBlZpJHHR Ta3z6OYJSI27ql1S0ZzJLzHVvwUxcok2X58nu4+6IvzrwnytlIDXpbLRArc+u8a4qY+3sVBFGBS p14+lqFDvc/3eSWnWSSL4PL79iYZb1ULLHyvLRa5BNpGSVaqTd7gQ7S1Ibtg0wRd/qEgmVrReer k9vRhjgajBdAZR6 X-Gm-Gg: ASbGncureVpvDZZbsstR/fOyvpXQ6++rE9KEYyvCT5FX+zOX8jTPbUecm5Lp4usiEek rseH0m7zGDS8bCnVf7Z4aj8wu7MNiqg84y/FManHYtNwTUGhnKihfX0rNtcMGgZBDXjSWpgxW4L wWTEkJIUdRCGrAxSqXBm389m95NkRGGXwNNxl4CKiFS/j4F+6OzronNK+2D0pf6nS/4oMq9wT6O 1azavrJ0QU3401wmfytxv9Ty88BovsCH+0wxQnOGZlUMuCpxwX7/zG3mPsRe0nXJUKWLbXbevf4 HQJpr564BEi9UN1ZRkTgqQtqxQg9y61A52c22LOq8yK4KI7pLlNHMJ/Ur+dAlsoIsN6JYD3IClO /PEdY89vbcbnce2tQ1DQmSK6KglbfLRZCRPQZvA7xSUJyXl+UvDQ3jZZb6CFejwxafwhlj7jSe3 HIU6jz X-Google-Smtp-Source: AGHT+IHa5OGWgTynauHp7mleJAzHKoDAPckClzpKnNfUyUl9SnPofYbFoyb2bKUla3Wv4tk9okOkCY7gEdqu X-Received: by 2002:a05:6870:e254:b0:380:527e:50b2 with SMTP id 586e51a60fabf-3b0fd1ceaf6mr6898213fac.18.1759845904502; Tue, 07 Oct 2025 07:05:04 -0700 (PDT) Received: from smtp-us-east1-p01-i01-si01.dlp.protect.broadcom.com (address-144-49-247-117.dlp.protect.broadcom.com. [144.49.247.117]) by smtp-relay.gmail.com with ESMTPS id 586e51a60fabf-3ab94d987e1sm1346179fac.18.2025.10.07.07.05.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Oct 2025 07:05:04 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qv1-f69.google.com with SMTP id 6a1803df08f44-87a0e9be970so12606716d6.3 for ; Tue, 07 Oct 2025 07:05:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1759845903; x=1760450703; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rEmNG5dHeCrJHUC2bFy2N+BBQV+BhaaczeWYkzApDTU=; b=GUvzSFsz3t7AFWVp10npn4zrQGybHAYgVQVwGHdChjeDs6I/3Ex+i/iW+M+BZLnHmn DiAulHzbq7gj/FYSHJKD2QTCs3Q4T10wNIL+nX8YIXR1BgRDs0iO3L+Emk6T15svIwmn 9nySPWIWAkOONec6Gf5YStrksf9AY5++zLZyE= X-Forwarded-Encrypted: i=1; AJvYcCUpppi3CpFDqWmTHanhiYoosNWL5+Bap2TDMdyqjBKlnTXbZJV/Rpl09zXl7t35v22EaLa1zedk7RXh99c=@vger.kernel.org X-Received: by 2002:a05:6214:4113:b0:818:f4ef:daab with SMTP id 6a1803df08f44-879dc7c243bmr192632026d6.26.1759845902167; Tue, 07 Oct 2025 07:05:02 -0700 (PDT) X-Received: by 2002:a05:6214:4113:b0:818:f4ef:daab with SMTP id 6a1803df08f44-879dc7c243bmr192630956d6.26.1759845901002; Tue, 07 Oct 2025 07:05:01 -0700 (PDT) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-878bae60b67sm142718956d6.9.2025.10.07.07.04.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Oct 2025 07:05:00 -0700 (PDT) From: Kamal Dasu To: andersson@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Kamal Dasu Subject: [PATCH v2 3/5] mmc: sdhci-brcmstb: clear CFG_OP_DLY when using HS200 Date: Tue, 7 Oct 2025 10:04:31 -0400 Message-Id: <20251007140434.606051-4-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251007140434.606051-1-kamal.dasu@broadcom.com> References: <20251007140434.606051-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Clear SDIO_1_CFG_OP_DLY register when using HS200 mode to be compliant with timing spec. We only need this for on BCM72116 SoCs. Signed-off-by: Kamal Dasu Reviewed-by: Florian Fainelli Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-brcmstb.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcm= stb.c index f81cc1889ac9..d25bf71d79f4 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -34,6 +34,8 @@ #define SDIO_CFG_CTRL 0x0 #define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) #define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) +#define SDIO_CFG_OP_DLY 0x34 +#define SDIO_CFG_OP_DLY_DEFAULT 0x80000003 #define SDIO_CFG_CQ_CAPABILITY 0x4c #define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) #define SDIO_CFG_MAX_50MHZ_MODE 0x1ac @@ -210,6 +212,21 @@ static void sdhci_brcmstb_cfginit_2712(struct sdhci_ho= st *host) } } =20 +static void sdhci_brcmstb_set_72116_uhs_signaling(struct sdhci_host *host,= unsigned int timing) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + u32 reg; + + /* no change to SDIO_CFG_OP_DLY_DEFAULT when using preset clk rate */ + if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) + return; + + reg =3D (timing =3D=3D MMC_TIMING_MMC_HS200) ? 0 : SDIO_CFG_OP_DLY_DEFAUL= T; + writel(reg, priv->cfg_regs + SDIO_CFG_OP_DLY); + sdhci_set_uhs_signaling(host, timing); +} + static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) { sdhci_dumpregs(mmc_priv(mmc)); @@ -250,6 +267,13 @@ static struct sdhci_ops sdhci_brcmstb_ops_2712 =3D { .set_uhs_signaling =3D sdhci_set_uhs_signaling, }; =20 +static struct sdhci_ops sdhci_brcmstb_ops_72116 =3D { + .set_clock =3D sdhci_set_clock, + .set_bus_width =3D sdhci_set_bus_width, + .reset =3D sdhci_reset, + .set_uhs_signaling =3D sdhci_brcmstb_set_72116_uhs_signaling, +}; + static struct sdhci_ops sdhci_brcmstb_ops_7216 =3D { .set_clock =3D sdhci_brcmstb_set_clock, .set_bus_width =3D sdhci_set_bus_width, @@ -280,6 +304,11 @@ static struct brcmstb_match_priv match_priv_7445 =3D { .ops =3D &sdhci_brcmstb_ops, }; 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Signed-off-by: Kamal Dasu Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-brcmstb.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcm= stb.c index d25bf71d79f4..42709ca8111d 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -299,6 +299,11 @@ static struct brcmstb_match_priv match_priv_7425 =3D { .ops =3D &sdhci_brcmstb_ops, }; =20 +static struct brcmstb_match_priv match_priv_74371 =3D { + .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, + .ops =3D &sdhci_brcmstb_ops, +}; + static struct brcmstb_match_priv match_priv_7445 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, .ops =3D &sdhci_brcmstb_ops, @@ -324,6 +329,7 @@ static struct brcmstb_match_priv match_priv_74165b0 =3D= { static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] =3D { { .compatible =3D "brcm,bcm2712-sdhci", .data =3D &match_priv_2712 }, { .compatible =3D "brcm,bcm7425-sdhci", .data =3D &match_priv_7425 }, + { .compatible =3D "brcm,bcm74371-sdhci", .data =3D &match_priv_74371 }, { .compatible =3D "brcm,bcm7445-sdhci", .data =3D &match_priv_7445 }, { .compatible =3D "brcm,bcm72116-sdhci", .data =3D &match_priv_72116 }, { .compatible =3D "brcm,bcm7216-sdhci", .data =3D &match_priv_7216 }, --=20 2.34.1 From nobody Sun Feb 8 02:56:15 2026 Received: from mail-vs1-f98.google.com (mail-vs1-f98.google.com [209.85.217.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62B252E11A6 for ; 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[144.49.247.126]) by smtp-relay.gmail.com with ESMTPS id ada2fe7eead31-5d5d39db9ccsm331891137.5.2025.10.07.07.05.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Oct 2025 07:05:19 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-qv1-f72.google.com with SMTP id 6a1803df08f44-803339f345bso92134156d6.2 for ; Tue, 07 Oct 2025 07:05:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1759845919; x=1760450719; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nQDseboPoN7tnrpn/frcsPgqqEsYL+e4oPXMaYNhgu8=; b=f4pyrBXCq3KVWz+W4F3TmU/i/2yO7t1WapWnmpP2DbNsHc4dFczTu3AyMKO3VdU9we Y/HJrn4nBEclBHJwPBfonuKAj938o/myXYp1OV2gNL+NjzsuVytxnqZvCsonjk7zIclW fP492tnFc2dy5+4rl6tL9VWxx5GtjIQ5JzUAY= X-Forwarded-Encrypted: i=1; AJvYcCXbe1Nd358EdhbU3//rMinmm8R9sj7OrlXLSjccaY+8nL2yoWHAATikKCquQrCx0Tt3PJSiJyHyIl9qn+M=@vger.kernel.org X-Received: by 2002:a05:6214:2682:b0:874:3018:f958 with SMTP id 6a1803df08f44-879dc77b8e8mr209784056d6.5.1759845918369; Tue, 07 Oct 2025 07:05:18 -0700 (PDT) X-Received: by 2002:a05:6214:2682:b0:874:3018:f958 with SMTP id 6a1803df08f44-879dc77b8e8mr209783356d6.5.1759845917674; Tue, 07 Oct 2025 07:05:17 -0700 (PDT) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-878bae60b67sm142718956d6.9.2025.10.07.07.05.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Oct 2025 07:05:17 -0700 (PDT) From: Kamal Dasu To: andersson@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Kamal Dasu Subject: [PATCH v2 5/5] mmc: sdhci-brcmstb: save and restore registers during PM Date: Tue, 7 Oct 2025 10:04:34 -0400 Message-Id: <20251007140434.606051-7-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251007140434.606051-1-kamal.dasu@broadcom.com> References: <20251007140434.606051-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Added support to save and restore registers that are critical during PM. Signed-off-by: Kamal Dasu Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-brcmstb.c | 112 +++++++++++++++++++++++++++++-- 1 file changed, 107 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcm= stb.c index 42709ca8111d..7de395c86f2f 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -38,28 +38,109 @@ #define SDIO_CFG_OP_DLY_DEFAULT 0x80000003 #define SDIO_CFG_CQ_CAPABILITY 0x4c #define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) +#define SDIO_CFG_SD_PIN_SEL 0x44 +#define SDIO_CFG_V1_SD_PIN_SEL 0x54 +#define SDIO_CFG_PHY_SW_MODE_0_RX_CTRL 0x7C #define SDIO_CFG_MAX_50MHZ_MODE 0x1ac #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) =20 +#define SDIO_BOOT_MAIN_CTL 0x0 + #define MMC_CAP_HSE_MASK (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V) /* Select all SD UHS type I SDR speed above 50MB/s */ #define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) =20 -struct sdhci_brcmstb_priv { - void __iomem *cfg_regs; - unsigned int flags; - struct clk *base_clk; - u32 base_freq_hz; +enum cfg_core_ver { + SDIO_CFG_CORE_V1 =3D 1, + SDIO_CFG_CORE_V2, +}; + +struct sdhci_brcmstb_saved_regs { + u32 sd_pin_sel; + u32 phy_sw_mode0_rxctrl; + u32 max_50mhz_mode; + u32 boot_main_ctl; }; =20 struct brcmstb_match_priv { void (*cfginit)(struct sdhci_host *host); void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); + void (*save_restore_regs)(struct mmc_host *mmc, int save); struct sdhci_ops *ops; const unsigned int flags; }; =20 +struct sdhci_brcmstb_priv { + void __iomem *cfg_regs; + void __iomem *boot_regs; + struct sdhci_brcmstb_saved_regs saved_regs; + unsigned int flags; + struct clk *base_clk; + u32 base_freq_hz; + const struct brcmstb_match_priv *match_priv; +}; + +static void sdhci_brcmstb_save_regs(struct mmc_host *mmc, enum cfg_core_ve= r ver) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + struct sdhci_brcmstb_saved_regs *sr =3D &priv->saved_regs; + void __iomem *cr =3D priv->cfg_regs; + bool is_emmc =3D mmc->caps & MMC_CAP_NONREMOVABLE; + + if (is_emmc && priv->boot_regs) + sr->boot_main_ctl =3D readl(priv->boot_regs + SDIO_BOOT_MAIN_CTL); + + if (ver =3D=3D SDIO_CFG_CORE_V1) { + sr->sd_pin_sel =3D readl(cr + SDIO_CFG_V1_SD_PIN_SEL); + return; + } + + sr->sd_pin_sel =3D readl(cr + SDIO_CFG_SD_PIN_SEL); + sr->phy_sw_mode0_rxctrl =3D readl(cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL); + sr->max_50mhz_mode =3D readl(cr + SDIO_CFG_MAX_50MHZ_MODE); +} + +static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, enum cfg_core= _ver ver) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + struct sdhci_brcmstb_saved_regs *sr =3D &priv->saved_regs; + void __iomem *cr =3D priv->cfg_regs; + bool is_emmc =3D mmc->caps & MMC_CAP_NONREMOVABLE; + + if (is_emmc && priv->boot_regs) + writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL); + + if (ver =3D=3D SDIO_CFG_CORE_V1) { + writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL); + return; + } + + writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL); + writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL); + writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE); +} + +static void sdhci_brcmstb_save_restore_regs_v1(struct mmc_host *mmc, int s= ave) +{ + if (save) + sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V1); + else + sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V1); +} + +static void sdhci_brcmstb_save_restore_regs_v2(struct mmc_host *mmc, int s= ave) +{ + if (save) + sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V2); + else + sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V2); +} + static inline void enable_clock_gating(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); @@ -306,22 +387,26 @@ static struct brcmstb_match_priv match_priv_74371 =3D= { =20 static struct brcmstb_match_priv match_priv_7445 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, + .save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v1, .ops =3D &sdhci_brcmstb_ops, }; =20 static struct brcmstb_match_priv match_priv_72116 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, + .save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v1, .ops =3D &sdhci_brcmstb_ops_72116, }; =20 static const struct brcmstb_match_priv match_priv_7216 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, + .save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v2, .hs400es =3D sdhci_brcmstb_hs400es, .ops =3D &sdhci_brcmstb_ops_7216, }; =20 static struct brcmstb_match_priv match_priv_74165b0 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, + .save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v2, .hs400es =3D sdhci_brcmstb_hs400es, .ops =3D &sdhci_brcmstb_ops_74165b0, }; @@ -429,6 +514,7 @@ static int sdhci_brcmstb_probe(struct platform_device *= pdev) =20 pltfm_host =3D sdhci_priv(host); priv =3D sdhci_pltfm_priv(pltfm_host); + priv->match_priv =3D match->data; if (device_property_read_bool(&pdev->dev, "supports-cqe")) { priv->flags |=3D BRCMSTB_PRIV_FLAGS_HAS_CQE; match_priv->ops->irq =3D sdhci_brcmstb_cqhci_irq; @@ -446,6 +532,13 @@ static int sdhci_brcmstb_probe(struct platform_device = *pdev) if (res) goto err; =20 + /* map non-standard BOOT registers if present */ + if (host->mmc->caps & MMC_CAP_NONREMOVABLE) { + priv->boot_regs =3D devm_platform_get_and_ioremap_resource(pdev, 2, NULL= ); + if (IS_ERR(priv->boot_regs)) + priv->boot_regs =3D NULL; + } + /* * Automatic clock gating does not work for SD cards that may * voltage switch so only enable it for non-removable devices. @@ -536,8 +629,13 @@ static int sdhci_brcmstb_suspend(struct device *dev) struct sdhci_host *host =3D dev_get_drvdata(dev); struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + const struct brcmstb_match_priv *match_priv =3D priv->match_priv; + int ret; =20 + if (match_priv->save_restore_regs) + match_priv->save_restore_regs(host->mmc, 1); + clk_disable_unprepare(priv->base_clk); if (host->mmc->caps2 & MMC_CAP2_CQE) { ret =3D cqhci_suspend(host->mmc); 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Signed-off-by: Kamal Dasu --- drivers/mmc/host/sdhci-brcmstb.c | 112 +++++++++++++++++++++++++++++-- 1 file changed, 107 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcm= stb.c index 42709ca8111d..7de395c86f2f 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -38,28 +38,109 @@ #define SDIO_CFG_OP_DLY_DEFAULT 0x80000003 #define SDIO_CFG_CQ_CAPABILITY 0x4c #define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) +#define SDIO_CFG_SD_PIN_SEL 0x44 +#define SDIO_CFG_V1_SD_PIN_SEL 0x54 +#define SDIO_CFG_PHY_SW_MODE_0_RX_CTRL 0x7C #define SDIO_CFG_MAX_50MHZ_MODE 0x1ac #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) =20 +#define SDIO_BOOT_MAIN_CTL 0x0 + #define MMC_CAP_HSE_MASK (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V) /* Select all SD UHS type I SDR speed above 50MB/s */ #define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) =20 -struct sdhci_brcmstb_priv { - void __iomem *cfg_regs; - unsigned int flags; - struct clk *base_clk; - u32 base_freq_hz; +enum cfg_core_ver { + SDIO_CFG_CORE_V1 =3D 1, + SDIO_CFG_CORE_V2, +}; + +struct sdhci_brcmstb_saved_regs { + u32 sd_pin_sel; + u32 phy_sw_mode0_rxctrl; + u32 max_50mhz_mode; + u32 boot_main_ctl; }; =20 struct brcmstb_match_priv { void (*cfginit)(struct sdhci_host *host); void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); + void (*save_restore_regs)(struct mmc_host *mmc, int save); struct sdhci_ops *ops; const unsigned int flags; }; =20 +struct sdhci_brcmstb_priv { + void __iomem *cfg_regs; + void __iomem *boot_regs; + struct sdhci_brcmstb_saved_regs saved_regs; + unsigned int flags; + struct clk *base_clk; + u32 base_freq_hz; + const struct brcmstb_match_priv *match_priv; +}; + +static void sdhci_brcmstb_save_regs(struct mmc_host *mmc, enum cfg_core_ve= r ver) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + struct sdhci_brcmstb_saved_regs *sr =3D &priv->saved_regs; + void __iomem *cr =3D priv->cfg_regs; + bool is_emmc =3D mmc->caps & MMC_CAP_NONREMOVABLE; + + if (is_emmc && priv->boot_regs) + sr->boot_main_ctl =3D readl(priv->boot_regs + SDIO_BOOT_MAIN_CTL); + + if (ver =3D=3D SDIO_CFG_CORE_V1) { + sr->sd_pin_sel =3D readl(cr + SDIO_CFG_V1_SD_PIN_SEL); + return; + } + + sr->sd_pin_sel =3D readl(cr + SDIO_CFG_SD_PIN_SEL); + sr->phy_sw_mode0_rxctrl =3D readl(cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL); + sr->max_50mhz_mode =3D readl(cr + SDIO_CFG_MAX_50MHZ_MODE); +} + +static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, enum cfg_core= _ver ver) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + struct sdhci_brcmstb_saved_regs *sr =3D &priv->saved_regs; + void __iomem *cr =3D priv->cfg_regs; + bool is_emmc =3D mmc->caps & MMC_CAP_NONREMOVABLE; + + if (is_emmc && priv->boot_regs) + writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL); + + if (ver =3D=3D SDIO_CFG_CORE_V1) { + writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL); + return; + } + + writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL); + writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL); + writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE); +} + +static void sdhci_brcmstb_save_restore_regs_v1(struct mmc_host *mmc, int s= ave) +{ + if (save) + sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V1); + else + sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V1); +} + +static void sdhci_brcmstb_save_restore_regs_v2(struct mmc_host *mmc, int s= ave) +{ + if (save) + sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V2); + else + sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V2); +} + static inline void enable_clock_gating(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); @@ -306,22 +387,26 @@ static struct brcmstb_match_priv match_priv_74371 =3D= { =20 static struct brcmstb_match_priv match_priv_7445 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, + .save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v1, .ops =3D &sdhci_brcmstb_ops, }; =20 static struct brcmstb_match_priv match_priv_72116 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, + .save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v1, .ops =3D &sdhci_brcmstb_ops_72116, }; =20 static const struct brcmstb_match_priv match_priv_7216 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, + .save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v2, .hs400es =3D sdhci_brcmstb_hs400es, .ops =3D &sdhci_brcmstb_ops_7216, }; =20 static struct brcmstb_match_priv match_priv_74165b0 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, + .save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v2, .hs400es =3D sdhci_brcmstb_hs400es, .ops =3D &sdhci_brcmstb_ops_74165b0, }; @@ -429,6 +514,7 @@ static int sdhci_brcmstb_probe(struct platform_device *= pdev) =20 pltfm_host =3D sdhci_priv(host); priv =3D sdhci_pltfm_priv(pltfm_host); + priv->match_priv =3D match->data; if (device_property_read_bool(&pdev->dev, "supports-cqe")) { priv->flags |=3D BRCMSTB_PRIV_FLAGS_HAS_CQE; match_priv->ops->irq =3D sdhci_brcmstb_cqhci_irq; @@ -446,6 +532,13 @@ static int sdhci_brcmstb_probe(struct platform_device = *pdev) if (res) goto err; =20 + /* map non-standard BOOT registers if present */ + if (host->mmc->caps & MMC_CAP_NONREMOVABLE) { + priv->boot_regs =3D devm_platform_get_and_ioremap_resource(pdev, 2, NULL= ); + if (IS_ERR(priv->boot_regs)) + priv->boot_regs =3D NULL; + } + /* * Automatic clock gating does not work for SD cards that may * voltage switch so only enable it for non-removable devices. @@ -536,8 +629,13 @@ static int sdhci_brcmstb_suspend(struct device *dev) struct sdhci_host *host =3D dev_get_drvdata(dev); struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + const struct brcmstb_match_priv *match_priv =3D priv->match_priv; + int ret; =20 + if (match_priv->save_restore_regs) + match_priv->save_restore_regs(host->mmc, 1); + clk_disable_unprepare(priv->base_clk); if (host->mmc->caps2 & MMC_CAP2_CQE) { ret =3D cqhci_suspend(host->mmc); @@ -553,6 +651,7 @@ static int sdhci_brcmstb_resume(struct device *dev) struct sdhci_host *host =3D dev_get_drvdata(dev); struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + const struct brcmstb_match_priv *match_priv =3D priv->match_priv; int ret; =20 ret =3D sdhci_pltfm_resume(dev); @@ -569,6 +668,9 @@ static int sdhci_brcmstb_resume(struct device *dev) ret =3D clk_set_rate(priv->base_clk, priv->base_freq_hz); } =20 + if (match_priv->save_restore_regs) + match_priv->save_restore_regs(host->mmc, 0); + if (host->mmc->caps2 & MMC_CAP2_CQE) ret =3D cqhci_resume(host->mmc); =20 --=20 2.34.1