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([82.78.167.59]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e674b6591sm272189625e9.4.2025.10.07.06.37.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Oct 2025 06:37:19 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu , Wolfram Sang Subject: [PATCH v5 3/6] arm64: dts: renesas: r9a08g045: Add PCIe node Date: Tue, 7 Oct 2025 16:36:54 +0300 Message-ID: <20251007133657.390523-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251007133657.390523-1-claudiu.beznea.uj@bp.renesas.com> References: <20251007133657.390523-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The RZ/G3S SoC has a variant (R9A08G045S33) which supports PCIe. Add the PCIe node. Tested-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v5: - updated the last part of ranges and dma-ranges - collected tags Changes in v4: - moved the node to r9a08g045.dtsi - dropped the "s33" from the compatible string - added port node - re-ordered properties to have them grouped together Changes in v3: - collected tags - changed the ranges flags Changes in v2: - updated the dma-ranges to reflect the SoC capability; added a comment about it. - updated clock-names, interrupt names - dropped legacy-interrupt-controller node - added interrupt-controller property - moved renesas,sysc at the end of the node to comply with DT coding style arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 16e6ac614417..00b43377877e 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -717,6 +717,72 @@ eth1: ethernet@11c40000 { status =3D "disabled"; }; =20 + pcie: pcie@11e40000 { + compatible =3D "renesas,r9a08g045-pcie"; + reg =3D <0 0x11e40000 0 0x10000>; + ranges =3D <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; + /* Map all possible DRAM ranges (4 GB). */ + dma-ranges =3D <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>; + bus-range =3D <0x0 0xff>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all"; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ + clocks =3D <&cpg CPG_MOD R9A08G045_PCI_ACLK>, + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; + clock-names =3D "aclk", "pm"; + resets =3D <&cpg R9A08G045_PCI_ARESETN>, + <&cpg R9A08G045_PCI_RST_B>, + <&cpg R9A08G045_PCI_RST_GP_B>, + <&cpg R9A08G045_PCI_RST_PS_B>, + <&cpg R9A08G045_PCI_RST_RSM_B>, + <&cpg R9A08G045_PCI_RST_CFG_B>, + <&cpg R9A08G045_PCI_RST_LOAD_B>; + reset-names =3D "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", + "rst_rsm_b", "rst_cfg_b", "rst_load_b"; + power-domains =3D <&cpg>; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + max-link-speed =3D <2>; + renesas,sysc =3D <&sysc>; + status =3D "disabled"; + + pcie_port0: pcie@0,0 { + reg =3D <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type =3D "pci"; + vendor-id =3D <0x1912>; + device-id =3D <0x0033>; + #address-cells =3D <3>; + #size-cells =3D <2>; + }; + }; + gic: interrupt-controller@12400000 { compatible =3D "arm,gic-v3"; #interrupt-cells =3D <3>; --=20 2.43.0