From nobody Wed Oct 8 00:29:52 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F1F02E0910 for ; Tue, 7 Oct 2025 13:37:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759844241; cv=none; b=eh2SY263O1SqwbZ0LcwlczlGy8FcRLe5LKJPfgFS5BZRebqFXXWTpZqS5uFsG7Tqw+1gxyHGbNUwTb4OMVovCi1SjjkC6MuKDshWdW1z/INUtkvbHqkoJELm3HQ1ay93vsPOEzVUp6+av4eWEREwdsDGFzfB7ubITXt1BZw6Gs0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759844241; c=relaxed/simple; bh=mYf1sBuj5tpiBM5j8R9kjmiFpvxtUDf+9Nw/gxI48HQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UayU8aIqDkHiisL1L+Q1dDayBAqYQlKm+RTZGndyFCgcwArpYTioCsIwC3QEOVcbN/GnUCUJYRkhKlq5RntsDr0uO8pjkl+8zE3yZYfBnW82wEt2SDeYx5BKCeIa/zPc6yVGtTwRx4AQ/8VwQSfe5l2Np5s9eUGFjyYt4EwiGi0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=RMz1b+fh; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="RMz1b+fh" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-46f53f88e0bso18196435e9.1 for ; Tue, 07 Oct 2025 06:37:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1759844237; x=1760449037; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eQLp04gFsJMZRCynh+s7cEZz15X09TZ9idlvFdtrO+Q=; b=RMz1b+fhuuakxiuEc/hT05atC1qhcf5b7x7ctfXA8fjJNdPlJT4arJCbETuHR/8kcj aqT9rBgY4zyUyJbhFsPuYgQNTVPa6abMV++3K4/mHDRbv4IflN57qvTLlbkO5Ks+bjvY KlDoN9GeGVbGI+rTTTqr+eJCbqQlrx6eSLZPBfiOHrXz5S5ja6TPHmjcVG7aGRw7PEFF YTvBUqo40GdPeGhu95u72wlHDpD4mrKRvHzOi27XhmnaKeO5AuqpO/TerEpGyd85YjMf MjIHXe6eUQ7B6y9s4oUZV2453pXPIxxvx8NiWzvMwkGD6eSFppWcezQXBP3HO6Y3aBGl kRMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759844237; x=1760449037; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eQLp04gFsJMZRCynh+s7cEZz15X09TZ9idlvFdtrO+Q=; b=wWf42oky/34EmP7359tnuXkg5TjXGMJhNZ6kIAJrn2OjLjRveBHZN6xmqnNGg3fKIX kXL9l+MCLE8SGW1TryZt/p6TYUalfpJp7VxR983NyjICsZZomMIAsnwEt9RYzOz+INN+ EDUv2iUPocFtZLE7Q20Ca5MsMVI+0cvRzqZwnUvqGd3bU3MJtasEZr8s0HR6QpCgMd7a PEq115C9XjfpG1wED2tXUssg5OpsYT0doorW6eIIJhXbQBuFJ62KIcyKWapz7uLwoBS/ sFgABkWry0BAy8N9yCDG6T3nA96Q5WPXCc3MIw+1540gJLwYWIkmaiHZKYo6Xgjb3jCq UACw== X-Forwarded-Encrypted: i=1; AJvYcCW3W+vLZbxS8D9Xgk7aH/9NXu7r8VS0trngJLn5/WpQnIo6S/bKqNomv+nen2xvlT18opl7J9IwKhfzOXw=@vger.kernel.org X-Gm-Message-State: AOJu0YyUncNY8+mqTWsbQ6tNbgndSj4NjDLViSVaXfGMbsBTa8KLYkNN Ih2Xdy5vhNbOYq6f57MXK/N+qF54qB0w63a5E3PqmcqbhJlglGHz4q2Ctf7GDubi5UA= X-Gm-Gg: ASbGncvNmtqOP8u9/6cKT2CVEZyd4kxKiLj4I1JOsUYAxNne/1q6WTaEI3v1K4XqSb2 2FNgn2pTsxdWmun/RAkCLmunFbe8h5N0/xE3AMYA+v8FwcaMx4OlpASsNrv7dTFeRbdIlfNCXlM Bg+1RziTydMrnAb6dmAGywPlSkpxrYViu6q+x5v9hdOR1ktv058qeFgeccCF5rWWCI3UMncC8Ad qndv5jg1wbWmpbiJkRCHQveHZ8FpVf5HtIGFTaqZz1zep7CnpbFVQotB2uVzDZsI24Ct9dP37j5 VlZM7wrJBYGsIwRDb/hNgbIsVMFmaS4lGf27CgUgnUxKK+LrQgeGfa3xLD/IDUOD7MEUKfEnuQT MOLwdBPKFUpNiwoPJsxEZ76R9vMKhgjSs7pi4zt8JSKI= X-Google-Smtp-Source: AGHT+IHuPTLj5uLSPdpG1nZMC6jrYcURKjFpDBAde9s0YKBBPSAJjg/o0OpdbzC7j7XeAYsTHnmrvg== X-Received: by 2002:a05:600c:1e1f:b0:45f:2805:91df with SMTP id 5b1f17b1804b1-46e714ca355mr101752075e9.20.1759844236658; Tue, 07 Oct 2025 06:37:16 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.59]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e674b6591sm272189625e9.4.2025.10.07.06.37.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Oct 2025 06:37:16 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu Subject: [PATCH v5 1/6] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add documentation for the PCIe IP on Renesas RZ/G3S Date: Tue, 7 Oct 2025 16:36:52 +0300 Message-ID: <20251007133657.390523-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251007133657.390523-1-claudiu.beznea.uj@bp.renesas.com> References: <20251007133657.390523-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express Base Specification 4.0. It is designed for root complex applications and features a single-lane (x1) implementation. Add documentation for it. Signed-off-by: Claudiu Beznea --- Changes in v5: - dropped Tb tag - style updates to the dma-ranges and ranges properties from examples section - re-enabled the node from examples section Changes in v4: - dropped "s33" string from compatible name - added port node documentation; due to this dropped Rob's Rb tag - reorderded properties - dropped spaces b/w "INT" and "A", "B", "C", "D" in comments Changes in v3: - collected tags - updated the flags of ranges property from example Changes in v2: - update the interrupt names by dropping "int" and "rc" string; due to this the patch description was adjusted - added "interrupt-controller" and made it mandatory - s/clkl1pm/pm/g - dropped the legacy-interrupt-controller node; with this the gic interrupt controller node was dropped as well as it is not needed anymore - updated interrupt-map in example and added interrupt-controller - added clock-names as required property as the pm clock is not handled though PM domains; this will allow the driver to have the option to request the pm clock by its name when implementation will be adjusted to used the pm clock - adjusted the size of dma-ranges to reflect the usage on SMARC module board - moved "renesas,sysc" at the end of the node in example to align with dts coding style .../bindings/pci/renesas,r9a08g045-pcie.yaml | 239 ++++++++++++++++++ 1 file changed, 239 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/renesas,r9a08g045= -pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.y= aml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml new file mode 100644 index 000000000000..d21d16b4e28d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml @@ -0,0 +1,239 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/renesas,r9a08g045-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3S PCIe host controller + +maintainers: + - Claudiu Beznea + +description: + Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification + 4.0 and supports up to 5 GT/s (Gen2). + +properties: + compatible: + const: renesas,r9a08g045-pcie # RZ/G3S + + reg: + maxItems: 1 + + interrupts: + items: + - description: System error interrupt + - description: System error on correctable error interrupt + - description: System error on non-fatal error interrupt + - description: System error on fatal error interrupt + - description: AXI error interrupt + - description: INTA interrupt + - description: INTB interrupt + - description: INTC interrupt + - description: INTD interrupt + - description: MSI interrupt + - description: Link bandwidth interrupt + - description: PME interrupt + - description: DMA interrupt + - description: PCIe event interrupt + - description: Message interrupt + - description: All interrupts + + interrupt-names: + items: + - description: serr + - description: ser_cor + - description: serr_nonfatal + - description: serr_fatal + - description: axi_err + - description: inta + - description: intb + - description: intc + - description: intd + - description: msi + - description: link_bandwidth + - description: pm_pme + - description: dma + - description: pcie_evt + - description: msg + - description: all + + interrupt-controller: true + + clocks: + items: + - description: System clock + - description: PM control clock + + clock-names: + items: + - description: aclk + - description: pm + + resets: + items: + - description: AXI2PCIe Bridge reset + - description: Data link layer/transaction layer reset + - description: Transaction layer (ACLK domain) reset + - description: Transaction layer (PCLK domain) reset + - description: Physical layer reset + - description: Configuration register reset + - description: Configuration register reset + + reset-names: + items: + - description: aresetn + - description: rst_b + - description: rst_gp_b + - description: rst_ps_b + - description: rst_rsm_b + - description: rst_cfg_b + - description: rst_load_b + + power-domains: + maxItems: 1 + + dma-ranges: + description: + A single range for the inbound memory region. + maxItems: 1 + + renesas,sysc: + description: System controller phandle + $ref: /schemas/types.yaml#/definitions/phandle + +patternProperties: + "^pcie@0,[0-0]$": + type: object + allOf: + - $ref: /schemas/pci/pci-device.yaml# + - $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + vendor-id: + const: 0x1912 + + device-id: + const: 0x0033 + + clocks: + items: + - description: Reference clock + + clock-names: + items: + - const: ref + + required: + - device_type + - vendor-id + - device-id + - clocks + - clock-names + + unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - interrupts + - interrupt-names + - interrupt-map + - interrupt-map-mask + - interrupt-controller + - power-domains + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + - renesas,sysc + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@11e40000 { + compatible =3D "renesas,r9a08g045-pcie"; + reg =3D <0 0x11e40000 0 0x10000>; + ranges =3D <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; + /* Map all possible DRAM ranges (4 GB). */ + dma-ranges =3D <0x42000000 0 0x40000000 0 0x40000000 1 0x00000= 000>; + bus-range =3D <0x0 0xff>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all"; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ + clocks =3D <&cpg CPG_MOD R9A08G045_PCI_ACLK>, + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; + clock-names =3D "aclk", "pm"; + resets =3D <&cpg R9A08G045_PCI_ARESETN>, + <&cpg R9A08G045_PCI_RST_B>, + <&cpg R9A08G045_PCI_RST_GP_B>, + <&cpg R9A08G045_PCI_RST_PS_B>, + <&cpg R9A08G045_PCI_RST_RSM_B>, + <&cpg R9A08G045_PCI_RST_CFG_B>, + <&cpg R9A08G045_PCI_RST_LOAD_B>; + reset-names =3D "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", + "rst_rsm_b", "rst_cfg_b", "rst_load_b"; + power-domains =3D <&cpg>; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + max-link-speed =3D <2>; + renesas,sysc =3D <&sysc>; + + pcie_port0: pcie@0,0 { + reg =3D <0x0 0x0 0x0 0x0 0x0>; + ranges; + clocks =3D <&versa3 5>; + clock-names =3D "ref"; + device_type =3D "pci"; + vendor-id =3D <0x1912>; + device-id =3D <0x0033>; + #address-cells =3D <3>; + #size-cells =3D <2>; + }; + }; + }; + +... --=20 2.43.0