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Tue, 07 Oct 2025 04:58:54 -0700 (PDT) Received: from curiosity ([5.188.167.4]) by smtp.googlemail.com with ESMTPSA id 2adb3069b0e04-58b011a8941sm6043339e87.114.2025.10.07.04.58.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Oct 2025 04:58:53 -0700 (PDT) From: Sergey Matyukevich To: linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Oleg Nesterov , Shuah Khan , Jisheng Zhang , Thomas Gleixner , Thomas Huth , Charlie Jenkins , Andy Chiu , Han Gao , Samuel Holland , Nam Cao , Joel Granados , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Conor Dooley , Sergey Matyukevich Subject: [PATCH v2 6/6] riscv: vector: initialize vlenb on the first context switch Date: Tue, 7 Oct 2025 14:58:22 +0300 Message-ID: <20251007115840.2320557-7-geomatsi@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251007115840.2320557-1-geomatsi@gmail.com> References: <20251007115840.2320557-1-geomatsi@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The vstate in thread_struct is zeroed when the vector context is initialized. That includes read-only register vlenb, which holds the vector register length in bytes. This zeroed state persists until mstatus.VS becomes 'dirty' and a context switch saves the actual hardware values. This can expose the zero vlenb value to the user-space in early debug scenarios, e.g. when ptrace attaches to a traced process early, before any vector instruction except the first one was executed. Fix this by forcing the vector context save on the first context switch. Signed-off-by: Sergey Matyukevich --- arch/riscv/kernel/vector.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 901e67adf576..3dd22a71aa18 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -120,6 +120,7 @@ static int riscv_v_thread_zalloc(struct kmem_cache *cac= he, =20 ctx->datap =3D datap; memset(ctx, 0, offsetof(struct __riscv_v_ext_state, datap)); + return 0; } =20 @@ -216,8 +217,11 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) force_sig(SIGBUS); return true; } + riscv_v_vstate_on(regs); riscv_v_vstate_set_restore(current, regs); + set_tsk_thread_flag(current, TIF_RISCV_V_FORCE_SAVE); + return true; } =20 --=20 2.51.0