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Tue, 7 Oct 2025 07:15:51 -0400 From: Antoniu Miclaus To: , , , , , CC: Antoniu Miclaus , =?UTF-8?q?Nuno=20S=C3=A1?= Subject: [PATCH v3 2/6] iio: adc: ad4080: prepare driver for multi-part support Date: Tue, 7 Oct 2025 11:15:21 +0000 Message-ID: <20251007111525.25711-3-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251007111525.25711-1-antoniu.miclaus@analog.com> References: <20251007111525.25711-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Authority-Analysis: v=2.4 cv=Y7n1cxeN c=1 sm=1 tr=0 ts=68e4f66d cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=gAnH3GRIAAAA:8 a=RVsaI-Iikop_xu5dod0A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-GUID: BUORRWIGXh_nNL2FJ7XJ2ZHnxzJOGYpm X-Proofpoint-ORIG-GUID: BUORRWIGXh_nNL2FJ7XJ2ZHnxzJOGYpm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA0MDA0MyBTYWx0ZWRfX2ftiDiBpeDqC bXX9ntcFdJQvfBD69+wShIbFE7WTFVEpICatrQYz/AO+Zhp5h/tQyC1B7ewh1f4idH5HfNYKI76 VTs28bq07EUCLJUHP812g4KS5kspZSQUnP45ssylCBbmzn48l77LluKCZw6TLVg3atYVKHTS5bq /fileSv3NaDYyn8TxzyitE7FLhLloKDYsCMpBY0dpavF43TdImcokpo4Fs99zZ/5hDjZq+i/2eo 0JraWp4l/hEsGalNhfzlu8c6CQLLsasf/UlIw/yR99IcWquNC7KRbeT+x96sMqbB6pAmPoFsDtF RaBhRBfA5PtxclKnSL4eC9Kjf7+a42Dvbas5JReu/CwHqMbX45BzJ+C0DYMbenlW2ZzckpYbbxK dYf8BG0jH9A1soU/YtysRg6+X9LIOg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-06_07,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2510040043 Refactor the ad4080 driver to support multiple ADC variants with different resolution bits and LVDS CNV clock count maximums. Changes: - Add lvds_cnv_clk_cnt_max field to chip_info structure - Create AD4080_CHANNEL_DEFINE macro for variable resolution/storage bits - Make LVDS CNV clock count configurable per chip variant - Use chip_info->product_id for chip identification comparison This prepares the infrastructure for adding support for additional ADC parts with different specifications while maintaining backward compatibility with existing AD4080 functionality. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- drivers/iio/adc/ad4080.c | 42 ++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c index ae5a975a47a5..7231b93821cd 100644 --- a/drivers/iio/adc/ad4080.c +++ b/drivers/iio/adc/ad4080.c @@ -167,6 +167,7 @@ struct ad4080_chip_info { const unsigned int (*scale_table)[2]; const struct iio_chan_spec *channels; unsigned int num_channels; + unsigned int lvds_cnv_clk_cnt_max; }; =20 struct ad4080_state { @@ -414,23 +415,25 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[= ] =3D { { } }; =20 -static const struct iio_chan_spec ad4080_channel =3D { - .type =3D IIO_VOLTAGE, - .indexed =3D 1, - .channel =3D 0, - .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE), - .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) | - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), - .info_mask_shared_by_all_available =3D - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), - .ext_info =3D ad4080_ext_info, - .scan_index =3D 0, - .scan_type =3D { - .sign =3D 's', - .realbits =3D 20, - .storagebits =3D 32, - }, -}; +#define AD4080_CHANNEL_DEFINE(bits, storage) { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .channel =3D 0, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available =3D \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .ext_info =3D ad4080_ext_info, \ + .scan_index =3D 0, \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D (bits), \ + .storagebits =3D (storage), \ + }, \ +} + +static const struct iio_chan_spec ad4080_channel =3D AD4080_CHANNEL_DEFINE= (20, 32); =20 static const struct ad4080_chip_info ad4080_chip_info =3D { .name =3D "ad4080", @@ -439,6 +442,7 @@ static const struct ad4080_chip_info ad4080_chip_info = =3D { .num_scales =3D ARRAY_SIZE(ad4080_scale_table), .num_channels =3D 1, .channels =3D &ad4080_channel, + .lvds_cnv_clk_cnt_max =3D AD4080_LVDS_CNV_CLK_CNT_MAX, }; =20 static int ad4080_setup(struct iio_dev *indio_dev) @@ -464,7 +468,7 @@ static int ad4080_setup(struct iio_dev *indio_dev) return ret; =20 id =3D le16_to_cpu(id_le); - if (id !=3D AD4080_CHIP_ID) + if (id !=3D st->info->product_id) dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id); =20 ret =3D regmap_set_bits(st->regmap, AD4080_REG_GPIO_CONFIG_A, @@ -490,7 +494,7 @@ static int ad4080_setup(struct iio_dev *indio_dev) AD4080_REG_ADC_DATA_INTF_CONFIG_B, AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, - AD4080_LVDS_CNV_CLK_CNT_MAX)); + st->info->lvds_cnv_clk_cnt_max)); if (ret) return ret; =20 --=20 2.43.0