From nobody Tue Oct 7 21:38:32 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5C8F235341; Tue, 7 Oct 2025 06:54:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759820042; cv=none; b=sDLfQRBCQvmy8lrqcDz5cRqMSBE6HOZGllm5ZbtVPKnYsf5qO+IPPn3l2VjcVf3ioi0pVMJOtwvzlDK9Dd+MNDIyA0yL5PpU5oVVM65z/hjNmUr4mBYyfvEoQVqyBrHqLz0jIP0meRJTByy+QDrbKJvk2WI/8xBU74KunJgw9jI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759820042; c=relaxed/simple; bh=r46GE5fcmXJUOsOhFrhC0/yII78h6bGgbcDsW3hMsiY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dkVQnYWJauVGIFCvz1FMW7ZoN2sf8Plym/r+z0hhqvP2YWNRYo3xVDqyC0temFrqX3tGcjepVcCWAH6v3llHBXDsuWiqEmZRt5A6Cp2oBECdUWUs7q5jElXxRCt6u0uaLbuDepsEJSjaTkozNwfqgoMFKmfni9KlNKvtsPsxPvU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jFdMTPzv; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jFdMTPzv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1759820040; x=1791356040; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=r46GE5fcmXJUOsOhFrhC0/yII78h6bGgbcDsW3hMsiY=; b=jFdMTPzvz+o79YP//gZyUCb6O5uEA+s44a5nI7cO9qoMZ15xom8WHgJa ZyqMTheMmx02OtFjbQtadtgQV4JWevy6+JJluwyBkZyoVIgx8iV5I8Uy4 a0DlINYy4aFNrlBWNhEX8rQnMtTVT6slQvXiz9gBHyTqCxI5jttdlHEZ8 oH172HNGqmOAFy311HO2AD3XvkJeu35s7I9QqRVrEBRRzhJ3iml2cfh+8 qniCqYmKoLmwPJrt5h72kD3duNDJkDY5D8LjYzYseKkb+G8XCrhy7poLW PwSY78WQ3Zv2eFp8Zr9RySJ6jh0mlNMX03Nqb3vHadKMQE1cnqouo1h5O w==; X-CSE-ConnectionGUID: WyHY2xdlROq+XsVXDEj68Q== X-CSE-MsgGUID: v/znFtYJTqKcsXf7ecxRYw== X-IronPort-AV: E=McAfee;i="6800,10657,11574"; a="72254433" X-IronPort-AV: E=Sophos;i="6.18,321,1751266800"; d="scan'208";a="72254433" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2025 23:53:58 -0700 X-CSE-ConnectionGUID: l+d5GK6NQFWXa+3JX2RqmA== X-CSE-MsgGUID: BO7q1UogQ9u/zWbcfFux0g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,321,1751266800"; d="scan'208";a="184354474" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa004.jf.intel.com with ESMTP; 06 Oct 2025 23:53:58 -0700 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov Cc: Jonathan Corbet , "H . Peter Anvin" , Andy Lutomirski , Josh Poimboeuf , Peter Zijlstra , Ard Biesheuvel , "Kirill A . Shutemov" , Sohil Mehta , Xin Li , David Woodhouse , Sean Christopherson , Rick Edgecombe , Vegard Nossum , Andrew Cooper , David Laight , Randy Dunlap , Geert Uytterhoeven , Kees Cook , Tony Luck , Alexander Shishkin , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org Subject: [PATCH v10 04/15] x86/cpu: Set LASS CR4 bit as pinning sensitive Date: Mon, 6 Oct 2025 23:51:08 -0700 Message-ID: <20251007065119.148605-5-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251007065119.148605-1-sohil.mehta@intel.com> References: <20251007065119.148605-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Yian Chen Security features such as LASS are not expected to be disabled once initialized. Add LASS to the CR4 pinned mask. Signed-off-by: Yian Chen Signed-off-by: Sohil Mehta --- v10: - No change. --- arch/x86/kernel/cpu/common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index c7d3512914ca..61ab332eaf73 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -403,7 +403,8 @@ static __always_inline void setup_umip(struct cpuinfo_x= 86 *c) =20 /* These bits should not change their value after CPU init is finished. */ static const unsigned long cr4_pinned_mask =3D X86_CR4_SMEP | X86_CR4_SMAP= | X86_CR4_UMIP | - X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED; + X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED | + X86_CR4_LASS; static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); static unsigned long cr4_pinned_bits __ro_after_init; =20 --=20 2.43.0