From nobody Mon Feb 9 14:03:19 2026 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2164D2253EE for ; Tue, 7 Oct 2025 05:55:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759816546; cv=none; b=mdivB9WqrEkCI9MOXQB0XBMMo5clppvIg+gd2fpIDOODKigXipmRHwkyByaxwGNMnp+jB4pkR0mHjdjRrtDZWW1hIWIt7+lJrGBSiB/udYEByiLAzF8o+1aVShsOX0CHEg1UlMnqzm9Phmbt0zxuQbqR/fOq/Wcxsau7bVHd6Ws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759816546; c=relaxed/simple; bh=Hsm386edsEgo2dKwST7fj8bp3dCE8dDU900XM/na56Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sS3Ms9bpV0FqDohMfKkRbchmbkoaDpiC6wt/A5x1uL/TwZHTPrfaFHUlVnMapX5zP4iPugwglrbJzLQ6lq8P4JRRFAmS8X8k2DJi+ogUDpRfnGiQN5TB6LoKWXek79zqlfnCyuVsN4AM3vcEKrjTEKfX2mQwoiFSpx1AAIiuGhs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YCOOXfhc; arc=none smtp.client-ip=209.85.216.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YCOOXfhc" Received: by mail-pj1-f43.google.com with SMTP id 98e67ed59e1d1-3352018e051so6876252a91.0 for ; Mon, 06 Oct 2025 22:55:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1759816544; x=1760421344; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X4w/nd5rmbgVq820HXsBhd3BuutmUjq9o+AodC2L7+g=; b=YCOOXfhcydVWmXB4bmq6Id/SXSdvLtRre55JTKwAKSEfVg8T6IhuUkVFCiMfs2nyno AX3+1lJPRnCfkts3Cao6z3+80ogYbGlw+x5+zAiPf2Lpyz9bqmtk5gib3tkI/cRt42Gw 59eFzid6JiSbBDt97jh76SaORwF9EvV0nq1VjGDDFerEnyk3EkXW9Bptt7hv4M8+Qaib Tm6eOmL+20LqCdp28aVLy7Xyd15pfS19G87x05veNfcu/Adflpj3SvErA3T7LdARzhUr wVtGTaYLvULo3jv46Gsrnq6jRAbKY4CcGjenTt7vpKLf/bBg8gHT/IPKJxurvk5trAmf 23Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759816544; x=1760421344; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X4w/nd5rmbgVq820HXsBhd3BuutmUjq9o+AodC2L7+g=; b=WtZB+5SwgLwiGCeQ1pPUD57ilXAMIQB6DAhgrikwT5E3ZeGTiFXwiFPqNP8AgBTgbY Boar8ci8F0A1o8W/m/9UaGQrWSy5ejJbWUtpJzSDZCRetlXFlZoe+eYP3qtfa+yYsTJe 9LQ9VJ5be7SldAQD/3SaXVL1BxthDwPa7Xke1iAE8xUObVn2cjQ091/bU/jb2JprBdkF dUOeEfFBKxELVxC2pITsrAcQlH8hVbJGeoZTBEt0U3qz+3nE/uyhTQ/YIzuHSKn4g7r/ Wzbh6KBWfWx9H26KFcrMhRA8eBieqQEZmYmBtkeq3gySGBnjOdSK4DfU9LNCTUaHsNJj Qadw== X-Forwarded-Encrypted: i=1; AJvYcCUoSw0MA6Nfpp7NCKV+CWw34ws5ZRjjG8D08RhwAz3ig34NG367CiPgGPUfBILf51/vvSFc3ncz90LTHYQ=@vger.kernel.org X-Gm-Message-State: AOJu0YxcNsb7GgX/9RmJWDPq/JU/5bJHiMT393hwo1ePjLgLnt2kQhqK RGJjS9VlJ85G0skC2aB1LBngxCQtCLsWG0v53w1vAqrDmNfdaz+NMIKo X-Gm-Gg: ASbGncvNCM6sV5gHGw3EQ2nEefZUGykiV3y2GVtR/WJD1QNHdfg4NMXMA/7+fhAQFAy 5H5LMZ4hvG3CF5iFsdND0IhH3vVogRolRzRgfatr0GYyNJI3bw5ff/bENY18m3nhkYpS+poVwh7 W8F/0vWVBbOfnvAZq967DMjvk8zNR5Uu/bkzvN9abSNrMb3zuR2PWXhFEQd1CyEc615zweAy793 GDZrKKFj04K39ZUw1VMzwkTCtv3MtWNwYmdJtGZBj6aF97hrxH4n1+NZvSOR/lQcRrmJW02aQSv HcL3yrHyu5jNB/U98oT1KTx2lbYi4i6XnRkCJnE7XFcQ86x0rhSA2KlGwqM+T2afZ2da9+mnU3Y x0IBYSg7cePt7TSLs/UILz18CGELPjB4UhPpuRQ6zR90K1CxXfU4qWP0YRt3UGSvcFu8= X-Google-Smtp-Source: AGHT+IHGq5lnEao3EPpA/kkYQkTWiqahXKnLIaznnb1YAy69hlrybXkT66SGtfHrZHLstajCPK/4qA== X-Received: by 2002:a17:90a:e7c2:b0:32e:9a24:2df9 with SMTP id 98e67ed59e1d1-339c2720c8amr21600122a91.14.1759816544072; Mon, 06 Oct 2025 22:55:44 -0700 (PDT) Received: from akshayaj-lenovo.. ([223.233.78.22]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-339c4a1a9e8sm12983829a91.11.2025.10.06.22.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Oct 2025 22:55:43 -0700 (PDT) From: Akshay Jindal To: dan@dlrobertson.com, jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org Cc: Akshay Jindal , shuah@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/6] iio: accel: bma400: Replace bit shifts with FIELD_PREP and FIELD_GET Date: Tue, 7 Oct 2025 11:25:04 +0530 Message-ID: <20251007055511.108984-5-akshayaj.lkd@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251007055511.108984-1-akshayaj.lkd@gmail.com> References: <20251007055511.108984-1-akshayaj.lkd@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" set_* functions involve left shift of param values into respective register fields before writing to register. Similarly get_* functions involve right shift to extract values from the respective bit fields. Replace these explicit shifting statements with standard kernel style macros FIELD_GET and FIELD_PREP. Signed-off-by: Akshay Jindal --- drivers/iio/accel/bma400.h | 3 --- drivers/iio/accel/bma400_core.c | 12 ++++++------ 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/iio/accel/bma400.h b/drivers/iio/accel/bma400.h index 12836111710e..d0e91481c799 100644 --- a/drivers/iio/accel/bma400.h +++ b/drivers/iio/accel/bma400.h @@ -68,7 +68,6 @@ */ #define BMA400_ACC_CONFIG0_REG 0x19 #define BMA400_ACC_CONFIG0_LP_OSR_MASK GENMASK(6, 5) -#define BMA400_LP_OSR_SHIFT 5 =20 #define BMA400_ACC_CONFIG1_REG 0x1a #define BMA400_ACC_CONFIG1_ODR_MASK GENMASK(3, 0) @@ -79,9 +78,7 @@ #define BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ 25 #define BMA400_ACC_CONFIG1_ODR_MIN_HZ 12 #define BMA400_ACC_CONFIG1_NP_OSR_MASK GENMASK(5, 4) -#define BMA400_NP_OSR_SHIFT 4 #define BMA400_ACC_CONFIG1_ACC_RANGE_MASK GENMASK(7, 6) -#define BMA400_ACC_RANGE_SHIFT 6 =20 #define BMA400_ACC_CONFIG2_REG 0x1b =20 diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_cor= e.c index a0e994f9882b..665c8df93008 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -627,7 +627,7 @@ static int bma400_get_accel_oversampling_ratio(struct b= ma400_data *data) return ret; } =20 - osr =3D (val & BMA400_ACC_CONFIG0_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT; + osr =3D FIELD_GET(BMA400_ACC_CONFIG0_LP_OSR_MASK, val); =20 data->oversampling_ratio =3D osr; return 0; @@ -638,7 +638,7 @@ static int bma400_get_accel_oversampling_ratio(struct b= ma400_data *data) return ret; } =20 - osr =3D (val & BMA400_ACC_CONFIG1_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT; + osr =3D FIELD_GET(BMA400_ACC_CONFIG1_NP_OSR_MASK, val); =20 data->oversampling_ratio =3D osr; return 0; @@ -673,7 +673,7 @@ static int bma400_set_accel_oversampling_ratio(struct b= ma400_data *data, =20 ret =3D regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG, (acc_config & ~BMA400_ACC_CONFIG0_LP_OSR_MASK) | - (val << BMA400_LP_OSR_SHIFT)); + FIELD_PREP(BMA400_ACC_CONFIG0_LP_OSR_MASK, val)); if (ret) { dev_err(data->dev, "Failed to write out OSR\n"); return ret; @@ -689,7 +689,7 @@ static int bma400_set_accel_oversampling_ratio(struct b= ma400_data *data, =20 ret =3D regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, (acc_config & ~BMA400_ACC_CONFIG1_NP_OSR_MASK) | - (val << BMA400_NP_OSR_SHIFT)); + FIELD_PREP(BMA400_ACC_CONFIG1_NP_OSR_MASK, val)); if (ret) { dev_err(data->dev, "Failed to write out OSR\n"); return ret; @@ -730,7 +730,7 @@ static int bma400_get_accel_scale(struct bma400_data *d= ata) if (ret) return ret; =20 - raw_scale =3D (val & BMA400_ACC_CONFIG1_ACC_RANGE_MASK) >> BMA400_ACC_RAN= GE_SHIFT; + raw_scale =3D FIELD_GET(BMA400_ACC_CONFIG1_ACC_RANGE_MASK, val); if (raw_scale > BMA400_TWO_BITS_MASK) return -EINVAL; =20 @@ -755,7 +755,7 @@ static int bma400_set_accel_scale(struct bma400_data *d= ata, unsigned int val) =20 ret =3D regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, (acc_config & ~BMA400_ACC_CONFIG1_ACC_RANGE_MASK) | - (raw << BMA400_ACC_RANGE_SHIFT)); + FIELD_PREP(BMA400_ACC_CONFIG1_ACC_RANGE_MASK, raw)); if (ret) return ret; =20 --=20 2.43.0