From nobody Thu Dec 18 22:40:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A1522EA736; Wed, 8 Oct 2025 06:21:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759904486; cv=none; b=Wf+C6ACcJjbOmG6YWGOTjStK6GKzXfXYyI8znNS+F4nBI1eGDN68QeeJGKskrAwaGgvoC/hLM/XWvNBm5Lw6YeKtEMvtvNCTObNFjtKynQ4wDBBdSgZ2xW/aMG4NEd6+sTGcgzuvFogGZ/8Ketq8emxxMpEs7nNDcmMDB7RCRCg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759904486; c=relaxed/simple; bh=0jBzPJ20ox2L4NDnb6CgxMPtci7OTtqgWhCqZ9C57bo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MX8HzRSxZRWYGlfsgEcLKDClMGjmjmafAvZ8r+MnWE/qf96g+GTH9t1WukUNRyn3QQGf6+ubgnkZjHe9RU5h2iRHxO2Tti6fh1PBB3EqH10QJncZGMv2uJYJv1k42IoGrSE12bb2IzVgQcKv2er82XiP//lQDYuIIpvHglOhSmk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HC8sLZQT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HC8sLZQT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C73ACC116C6; Wed, 8 Oct 2025 06:21:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759904485; bh=0jBzPJ20ox2L4NDnb6CgxMPtci7OTtqgWhCqZ9C57bo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HC8sLZQTLnzQfCDsyHuGuFJtQf58OFqz//wqdjh/+AiMSRpYx/eAf6gtZ6BY4QDLN D7TqQnt+BovSZTB29sEtZ5vHtN55zDA4CHmorQYXGkHU+KsAmWT+LSFgHYMM8bjfRc 2/gOiP+Niz1N6Jj2LZfsMvWXePI2Rfk84DEzhdMW6tousSk487AnyE+vEaIrkGu8tL FK0ZZcOzpM+2NUIJlHcU4+TItYRF4KECltZjK0JUjU5l6PGJxjq7RxUtuXVE48fhwk 4I+iR+aq2Rgflec1oU2GVq+IUTU6+rpp5T8GWcycOyKFdBmTVOPlzxouXo58cchY/G TVz4g04HoXHPw== From: Drew Fustini Date: Tue, 07 Oct 2025 23:21:12 -0700 Subject: [PATCH v4 3/3] RISC-V: Add support for srmcfg CSR from Ssqosid ext Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251007-ssqosid-v4-3-e8b57e59d812@kernel.org> References: <20251007-ssqosid-v4-0-e8b57e59d812@kernel.org> In-Reply-To: <20251007-ssqosid-v4-0-e8b57e59d812@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: =?utf-8?q?Kornel_Dul=C4=99ba?= , Adrien Ricciardi , James Morse , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , Conor Dooley , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Drew Fustini X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8328; i=fustini@kernel.org; h=from:subject:message-id; bh=0jBzPJ20ox2L4NDnb6CgxMPtci7OTtqgWhCqZ9C57bo=; b=owGbwMvMwCF2+43O4ZsaG3kYT6slMWQ8Y3q8Qs2J9UyHMYcwN6vfjvSL/LZC0ezb6rfFlD12W bRtdm9hRykLgxgHg6yYIsumD3kXlniFfl0w/8U2mDmsTCBDGLg4BWAiPxwY/konnUjNWPdEdtKX jruPr9vO37tE8K1hxZEbKvJO6x6XzWJn+GeQdHITa8brd+3Hyo8t1VTfcEKRKfWthXXRRqtlF55 3fGMBAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add support for the srmcfg CSR defined in the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). The CSR contains two fields: - Resource Control ID (RCID) used determine resource allocation - Monitoring Counter ID (MCID) used to track resource usage Requests from a hart to shared resources like cache will be tagged with these IDs. This allows the usage of shared resources to be associated with the task currently running on the hart. A srmcfg field is added to thread_struct and has the same format as the srmcfg CSR. This allows the scheduler to set the hart's srmcfg CSR to contain the RCID and MCID for the task that is being scheduled in. The srmcfg CSR is only written to if the thread_struct.srmcfg is different than the current value of the CSR. A per-cpu variable cpu_srmcfg is used to mirror that state of the CSR. This is because access to L1D hot memory should be several times faster than a CSR read. Also, in the case of virtualization, accesses to this CSR are trapped in the hypervisor. Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0 Co-developed-by: Kornel Dul=C4=99ba Signed-off-by: Kornel Dul=C4=99ba [fustini: rename csr, refactor switch_to, rebase on riscv/for-next] Signed-off-by: Drew Fustini --- MAINTAINERS | 7 +++++++ arch/riscv/Kconfig | 17 ++++++++++++++++ arch/riscv/include/asm/csr.h | 8 ++++++++ arch/riscv/include/asm/processor.h | 3 +++ arch/riscv/include/asm/qos.h | 41 ++++++++++++++++++++++++++++++++++= ++++ arch/riscv/include/asm/switch_to.h | 3 +++ arch/riscv/kernel/Makefile | 2 ++ arch/riscv/kernel/qos/Makefile | 2 ++ arch/riscv/kernel/qos/qos.c | 5 +++++ 9 files changed, 88 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 858de646632acf2ba900b799882f6aa79a1df6fa..315feed291e5b7417633f0ffdf8= b5abb50b6c831 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21700,6 +21700,13 @@ F: drivers/perf/riscv_pmu.c F: drivers/perf/riscv_pmu_legacy.c F: drivers/perf/riscv_pmu_sbi.c =20 +RISC-V QOS RESCTRL SUPPORT +M: Drew Fustini +L: linux-riscv@lists.infradead.org +S: Supported +F: arch/riscv/include/asm/qos.h +F: arch/riscv/kernel/qos/ + RISC-V RPMI AND MPXY DRIVERS M: Rahul Pathak M: Anup Patel diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 715e59f1e287dcdbbf3ae0dd8dac2a80e3fe9143..e41abf303794cf5d23633730414= 8c80ee98a359c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -606,6 +606,23 @@ config RISCV_ISA_SVNAPOT =20 If you don't know what to do here, say Y. =20 +config RISCV_ISA_SSQOSID + bool "Ssqosid extension support for supervisor mode Quality of Service ID" + default y + help + Adds support for the Ssqosid ISA extension (Supervisor-mode + Quality of Service ID). + + Ssqosid defines the srmcfg CSR which allows the system to tag the + running process with an RCID (Resource Control ID) and MCID + (Monitoring Counter ID). The RCID is used to determine resource + allocation. The MCID is used to track resource usage in event + counters. + + For example, a cache controller may use the RCID to apply a + cache partitioning scheme and use the MCID to track how much + cache a process, or a group of processes, is using. + config RISCV_ISA_SVPBMT bool "Svpbmt extension support for supervisor mode page-based memory type= s" depends on 64BIT && MMU diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 4a37a98398ad3b527c280c1e1260d0b53a4ac8d9..2590b89b8f721a4f98a850d4640= aa571a7ec80d1 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -75,6 +75,13 @@ #define SATP_ASID_MASK _AC(0xFFFF, UL) #endif =20 +/* SRMCFG fields */ +#define SRMCFG_RCID_MASK _AC(0x00000FFF, UL) +#define SRMCFG_MCID_MASK SRMCFG_RCID_MASK +#define SRMCFG_MCID_SHIFT 16 +#define SRMCFG_MASK ((SRMCFG_MCID_MASK << SRMCFG_MCID_SHIFT) | \ + SRMCFG_RCID_MASK) + /* Exception cause high bit - is an interrupt if set */ #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) =20 @@ -317,6 +324,7 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SATP 0x180 +#define CSR_SRMCFG 0x181 =20 #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index da5426122d280b53b8ba8f764ea6f1b9f93ca994..183c55e32b9656d34fb60cdf9bc= 61162fa25d165 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -122,6 +122,9 @@ struct thread_struct { /* A forced icache flush is not needed if migrating to the previous cpu. = */ unsigned int prev_cpu; #endif +#ifdef CONFIG_RISCV_ISA_SSQOSID + u32 srmcfg; +#endif }; =20 /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h new file mode 100644 index 0000000000000000000000000000000000000000..84830d7c6dc4a1fce86d514ed5a= f97be32a26630 --- /dev/null +++ b/arch/riscv/include/asm/qos.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_QOS_H +#define _ASM_RISCV_QOS_H + +#ifdef CONFIG_RISCV_ISA_SSQOSID + +#include +#include + +#include +#include +#include + +/* cached value of srmcfg csr for each cpu */ +DECLARE_PER_CPU(u32, cpu_srmcfg); + +static inline void __switch_to_srmcfg(struct task_struct *next) +{ + u32 *cpu_srmcfg_ptr =3D this_cpu_ptr(&cpu_srmcfg); + u32 thread_srmcfg; + + thread_srmcfg =3D READ_ONCE(next->thread.srmcfg); + + if (thread_srmcfg !=3D *cpu_srmcfg_ptr) { + *cpu_srmcfg_ptr =3D thread_srmcfg; + csr_write(CSR_SRMCFG, thread_srmcfg); + } +} + +static __always_inline bool has_srmcfg(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SSQOSID); +} + +#else /* ! CONFIG_RISCV_ISA_SSQOSID */ + +static __always_inline bool has_srmcfg(void) { return false; } +#define __switch_to_srmcfg(__next) do { } while (0) + +#endif /* CONFIG_RISCV_ISA_SSQOSID */ +#endif /* _ASM_RISCV_QOS_H */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 0e71eb82f920cac2f14bb626879bb219a2f247cc..a684a3795d3d7f5e027ec0a83c3= 0afd1a18d7228 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -14,6 +14,7 @@ #include #include #include +#include =20 #ifdef CONFIG_FPU extern void __fstate_save(struct task_struct *save_to); @@ -119,6 +120,8 @@ do { \ __switch_to_fpu(__prev, __next); \ if (has_vector() || has_xtheadvector()) \ __switch_to_vector(__prev, __next); \ + if (has_srmcfg()) \ + __switch_to_srmcfg(__next); \ if (switch_to_should_flush_icache(__next)) \ local_flush_icache_all(); \ __switch_to_envcfg(__next); \ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index c7b542573407c813a4a45fe9bf78a676599c0503..0108a4e6338a7972b6805ef1404= 8d4e5e8833d82 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -125,3 +125,5 @@ obj-$(CONFIG_ACPI) +=3D acpi.o obj-$(CONFIG_ACPI_NUMA) +=3D acpi_numa.o =20 obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) +=3D bugs.o + +obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos/ diff --git a/arch/riscv/kernel/qos/Makefile b/arch/riscv/kernel/qos/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..9f996263a86d7e2e410890d2425= e74b2277a57ad --- /dev/null +++ b/arch/riscv/kernel/qos/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos.o diff --git a/arch/riscv/kernel/qos/qos.c b/arch/riscv/kernel/qos/qos.c new file mode 100644 index 0000000000000000000000000000000000000000..7b06f7ae9056b8f2eb53a0eecf5= a6512edc29fbe --- /dev/null +++ b/arch/riscv/kernel/qos/qos.c @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include + +/* cached value of sqoscfg csr for each cpu */ +DEFINE_PER_CPU(u32, cpu_srmcfg); --=20 2.34.1