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Hence, add iommus property as optional property for PAS supported devices. Acked-by: Rob Herring (Arm) Reviewed-by: Bryan O'Donoghue Signed-off-by: Mukesh Ojha --- Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.y= aml b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml index 63a82e7a8bf8..8bd7d718be57 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml @@ -44,6 +44,9 @@ properties: - const: stop-ack - const: shutdown-ack =20 + iommus: + minItems: 1 + power-domains: minItems: 1 maxItems: 3 --=20 2.50.1 From nobody Mon Feb 9 10:39:31 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6660A2E8B96 for ; Tue, 7 Oct 2025 16:49:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Lets rename peripheral to pas_id to reflect closer to its meaning. Reviewed-by: Bryan O'Donoghue Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 30 +++++++++++++++--------------- include/linux/firmware/qcom/qcom_scm.h | 10 +++++----- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index e777b7cb9b12..3379607eaf94 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -562,7 +562,7 @@ static void qcom_scm_set_download_mode(u32 dload_mode) * qcom_scm_pas_init_image() - Initialize peripheral authentication service * state machine for a given peripheral, using the * metadata - * @peripheral: peripheral id + * @pas_id: peripheral authentication service id * @metadata: pointer to memory containing ELF header, program header table * and optional blob of data used for authenticating the metadata * and the rest of the firmware @@ -575,7 +575,7 @@ static void qcom_scm_set_download_mode(u32 dload_mode) * track the metadata allocation, this needs to be released by invoking * qcom_scm_pas_metadata_release() by the caller. */ -int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t s= ize, +int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size, struct qcom_scm_pas_metadata *ctx) { dma_addr_t mdata_phys; @@ -585,7 +585,7 @@ int qcom_scm_pas_init_image(u32 peripheral, const void = *metadata, size_t size, .svc =3D QCOM_SCM_SVC_PIL, .cmd =3D QCOM_SCM_PIL_PAS_INIT_IMAGE, .arginfo =3D QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW), - .args[0] =3D peripheral, + .args[0] =3D pas_id, .owner =3D ARM_SMCCC_OWNER_SIP, }; struct qcom_scm_res res; @@ -658,20 +658,20 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release); /** * qcom_scm_pas_mem_setup() - Prepare the memory related to a given periph= eral * for firmware loading - * @peripheral: peripheral id + * @pas_id: peripheral authentication service id * @addr: start address of memory area to prepare * @size: size of the memory area to prepare * * Returns 0 on success. */ -int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t s= ize) +int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size) { int ret; struct qcom_scm_desc desc =3D { .svc =3D QCOM_SCM_SVC_PIL, .cmd =3D QCOM_SCM_PIL_PAS_MEM_SETUP, .arginfo =3D QCOM_SCM_ARGS(3), - .args[0] =3D peripheral, + .args[0] =3D pas_id, .args[1] =3D addr, .args[2] =3D size, .owner =3D ARM_SMCCC_OWNER_SIP, @@ -699,18 +699,18 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup); /** * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmw= are * and reset the remote processor - * @peripheral: peripheral id + * @pas_id: peripheral authentication service id * * Return 0 on success. */ -int qcom_scm_pas_auth_and_reset(u32 peripheral) +int qcom_scm_pas_auth_and_reset(u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { .svc =3D QCOM_SCM_SVC_PIL, .cmd =3D QCOM_SCM_PIL_PAS_AUTH_AND_RESET, .arginfo =3D QCOM_SCM_ARGS(1), - .args[0] =3D peripheral, + .args[0] =3D pas_id, .owner =3D ARM_SMCCC_OWNER_SIP, }; struct qcom_scm_res res; @@ -735,18 +735,18 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset); =20 /** * qcom_scm_pas_shutdown() - Shut down the remote processor - * @peripheral: peripheral id + * @pas_id: peripheral authentication service id * * Returns 0 on success. */ -int qcom_scm_pas_shutdown(u32 peripheral) +int qcom_scm_pas_shutdown(u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { .svc =3D QCOM_SCM_SVC_PIL, .cmd =3D QCOM_SCM_PIL_PAS_SHUTDOWN, .arginfo =3D QCOM_SCM_ARGS(1), - .args[0] =3D peripheral, + .args[0] =3D pas_id, .owner =3D ARM_SMCCC_OWNER_SIP, }; struct qcom_scm_res res; @@ -772,18 +772,18 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown); /** * qcom_scm_pas_supported() - Check if the peripheral authentication servi= ce is * available for the given peripherial - * @peripheral: peripheral id + * @pas_id: peripheral authentication service id * * Returns true if PAS is supported for this peripheral, otherwise false. */ -bool qcom_scm_pas_supported(u32 peripheral) +bool qcom_scm_pas_supported(u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { .svc =3D QCOM_SCM_SVC_PIL, .cmd =3D QCOM_SCM_PIL_PAS_IS_SUPPORTED, .arginfo =3D QCOM_SCM_ARGS(1), - .args[0] =3D peripheral, + .args[0] =3D pas_id, .owner =3D ARM_SMCCC_OWNER_SIP, }; struct qcom_scm_res res; diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index a55ca771286b..a13f703b16cd 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -72,13 +72,13 @@ struct qcom_scm_pas_metadata { ssize_t size; }; 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a=ed25519-sha256; t=1759855751; l=4540; i=mukesh.ojha@oss.qualcomm.com; s=20250708; h=from:subject:message-id; bh=DuE7Kv7QoXg4yMkqF0Nqit8g8P9JPMJqyoG4dmGRg68=; b=OzYrVBTuRvqiviPCxW5zFBaao6FEOlOeHLWkwFqRizDeD8rkXfu78xUqflIUQZC+Lo5hHs3V5 szZEhCJSUoiCkD3LhzW9XLHYFDXtfQKC0lStzvgb4SUMAt6Qv9u9Qz5 X-Developer-Key: i=mukesh.ojha@oss.qualcomm.com; a=ed25519; pk=eX8dr/7d4HJz/HEXZIpe3c+Ukopa/wZmxH+5YV3gdNc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA0MDAxOSBTYWx0ZWRfX6/P4KrJwQH9S fYF6XV+ciJfgIRhjqPoqz0FG0OL60Rip2H24zOUx/mXxdApJ3J+x0nLmr80PHwIVXbAqf+deF4R lhlRMAuGqMujrdWwv4avsgE1zi55FipqGUebbD0pYzwat1Xygtm5Iug4urq/94CzzbVl0XLHu1/ F/ikWhUbR2JTLnY4zQuneozor1TMEfFWWRx1+apG+wHMElpqNOdqiVgjx15/Vbg+iEsZmw/Iu76 vi/gfVi7bTTwfbzbzKAlJE4jqe1JFovzE6TMHcAFvXFJjNcuqnJaOiq4yDqgQcvV3dFi2kAMhNS twyKoP00+MazJDpvXwfsHiw3C/i0Vy4nb2XEkD85QK0lPbb1w0vj1ZxXa+1gC8b8woxCC6VJgaM wonbZonqa5FDdOfoTxpjZcMo+V+i/g== X-Authority-Analysis: v=2.4 cv=B6O0EetM c=1 sm=1 tr=0 ts=68e54498 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=-i9yLzQnIfY35_RK680A:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: t83osR5Ac7OJp4CStwHAWjjGGvq0wI_G X-Proofpoint-ORIG-GUID: t83osR5Ac7OJp4CStwHAWjjGGvq0wI_G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-07_02,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 adultscore=0 impostorscore=0 spamscore=0 bulkscore=0 phishscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2510040019 When the Peripheral Authentication Service (PAS) method runs on a SoC where Linux operates at EL2 (i.e., without the Gunyah hypervisor), the reset sequences are handled by TrustZone. In such cases, Linux must perform additional steps before invoking PAS SMC calls, such as creating a SHM bridge. Therefore, PAS SMC calls require awareness and handling of these additional steps when Linux runs at EL2. To support this, there is a need for a data structure that can be initialized prior to invoking any SMC or MDT functions. This structure allows those functions to determine whether they are operating in the presence or absence of the Gunyah hypervisor and behave accordingly. Currently, remoteproc and non-remoteproc subsystems use different variants of the MDT loader helper API, primarily due to differences in metadata context handling. Remoteproc subsystems retain the metadata context until authentication and reset are completed, while non-remoteproc subsystems (e.g., video, graphics, IPA, etc.) do not retain the metadata context and can free it within the qcom_scm_pas_init() call by passing a NULL context parameter and due to these differences, it is not possible to extend metadata context handling to support remoteproc and non remoteproc subsystem use PAS operations, when Linux operates at EL2. Add PAS context data structure and helper functions to initialize and destroy it. Reviewed-by: Bryan O'Donoghue Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 54 ++++++++++++++++++++++++++++++= ++++ include/linux/firmware/qcom/qcom_scm.h | 11 +++++++ 2 files changed, 65 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 3379607eaf94..b8ce4fc34dbe 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -558,6 +558,60 @@ static void qcom_scm_set_download_mode(u32 dload_mode) dev_err(__scm->dev, "failed to set download mode: %d\n", ret); } =20 +/** + * qcom_scm_pas_context_init() - Initialize peripheral authentication serv= ice + * context for a given peripheral and it can be + * destroyed with qcom_scm_pas_context_destroy() + * to release the context + * + * @dev: PAS firmware device + * @pas_id: peripheral authentication service id + * @mem_phys: Subsystem reserve memory start address + * @mem_size: Subsystem reserve memory size + * + * Upon successful, returns the PAS context or ERR_PTR() of the error othe= rwise. + */ +void *qcom_scm_pas_context_init(struct device *dev, u32 pas_id, phys_addr_= t mem_phys, + size_t mem_size) +{ + struct qcom_scm_pas_context *ctx; + + ctx =3D kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); + + ctx->dev =3D dev; + ctx->pas_id =3D pas_id; + ctx->mem_phys =3D mem_phys; + ctx->mem_size =3D mem_size; + + ctx->metadata =3D kzalloc(sizeof(*ctx->metadata), GFP_KERNEL); + if (!ctx->metadata) { + kfree(ctx); + return ERR_PTR(-ENOMEM); + } + + return ctx; +} +EXPORT_SYMBOL_GPL(qcom_scm_pas_context_init); + +/** + * qcom_scm_pas_context_destroy() - release PAS context + * + * @ctx: PAS context + */ +void qcom_scm_pas_context_destroy(struct qcom_scm_pas_context *ctx) +{ + kfree(ctx->metadata); + ctx->metadata =3D NULL; + ctx->dev =3D NULL; + ctx->pas_id =3D 0; + ctx->mem_phys =3D 0; + ctx->mem_size =3D 0; + kfree(ctx); +} +EXPORT_SYMBOL_GPL(qcom_scm_pas_context_destroy); + /** * qcom_scm_pas_init_image() - Initialize peripheral authentication service * state machine for a given peripheral, using the diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index a13f703b16cd..e82fdc200df7 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -72,6 +72,17 @@ struct qcom_scm_pas_metadata { ssize_t size; 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The qcom_mdt_pas_load() and qcom_mdt_load() functions are almost similar. Clients using the PAS context-based data structure can adopt qcom_mdt_pas_load(), and in the future, all users of qcom_mdt_load() could be migrated to use qcom_mdt_pas_load() instead. Signed-off-by: Mukesh Ojha --- drivers/soc/qcom/mdt_loader.c | 29 +++++++++++++++++++++++++++++ include/linux/soc/qcom/mdt_loader.h | 11 +++++++++++ 2 files changed, 40 insertions(+) diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index a5c80d4fcc36..31855836b251 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -486,5 +486,34 @@ int qcom_mdt_load_no_init(struct device *dev, const st= ruct firmware *fw, } EXPORT_SYMBOL_GPL(qcom_mdt_load_no_init); =20 +/** + * qcom_mdt_pas_load() - load the firmware which header is loaded as fw + * + * Client should initialize the PAS context with qcom_scm_pas_context_init= () + * before calling this function. + * + * @ctx: PAS context pointer + * @fw: firmware object for the mdt file + * @firmware: name of the firmware, for construction of segment file names + * @mem_region: allocated memory region to load firmware into + * @reloc_base: adjusted physical address after relocation + * + * Returns 0 on success, negative errno otherwise. + */ +int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmw= are *fw, + const char *firmware, void *mem_region, phys_addr_t *reloc_base) +{ + int ret; + + ret =3D qcom_mdt_pas_init(ctx->dev, fw, firmware, ctx->pas_id, ctx->mem_p= hys, + ctx->metadata); + if (ret) + return ret; + + return __qcom_mdt_load(ctx->dev, fw, firmware, mem_region, ctx->mem_phys, + ctx->mem_size, reloc_base); +} +EXPORT_SYMBOL_GPL(qcom_mdt_pas_load); + MODULE_DESCRIPTION("Firmware parser for Qualcomm MDT format"); MODULE_LICENSE("GPL v2"); diff --git a/include/linux/soc/qcom/mdt_loader.h b/include/linux/soc/qcom/m= dt_loader.h index 8ea8230579a2..2832e0717729 100644 --- a/include/linux/soc/qcom/mdt_loader.h +++ b/include/linux/soc/qcom/mdt_loader.h @@ -11,6 +11,7 @@ struct device; struct firmware; struct qcom_scm_pas_metadata; +struct qcom_scm_pas_context; =20 #if IS_ENABLED(CONFIG_QCOM_MDT_LOADER) =20 @@ -23,6 +24,9 @@ int qcom_mdt_load(struct device *dev, const struct firmwa= re *fw, phys_addr_t mem_phys, size_t mem_size, phys_addr_t *reloc_base); =20 +int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmw= are *fw, + const char *firmware, void *mem_region, phys_addr_t *reloc_base); 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To reflect this, relevant SMC and metadata functions are updated to incorporate PAS context awareness. Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 32 +++++++++-------- drivers/remoteproc/qcom_q6v5_pas.c | 66 +++++++++++++++++++-----------= ---- drivers/soc/qcom/mdt_loader.c | 7 ++-- include/linux/firmware/qcom/qcom_scm.h | 4 +-- include/linux/soc/qcom/mdt_loader.h | 5 ++- 5 files changed, 62 insertions(+), 52 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index b8ce4fc34dbe..7b4ff3cb26ed 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -621,7 +621,7 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_context_destroy); * and optional blob of data used for authenticating the metadata * and the rest of the firmware * @size: size of the metadata - * @ctx: optional metadata context + * @ctx: optional pas context * * Return: 0 on success. * @@ -630,8 +630,9 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_context_destroy); * qcom_scm_pas_metadata_release() by the caller. */ int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size, - struct qcom_scm_pas_metadata *ctx) + struct qcom_scm_pas_context *ctx) { + struct qcom_scm_pas_metadata *mdt_ctx; dma_addr_t mdata_phys; void *mdata_buf; int ret; @@ -682,10 +683,11 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *m= etadata, size_t size, out: if (ret < 0 || !ctx) { dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys); - } else if (ctx) { - ctx->ptr =3D mdata_buf; - ctx->phys =3D mdata_phys; - ctx->size =3D size; + } else if (ctx && ctx->metadata) { + mdt_ctx =3D ctx->metadata; + mdt_ctx->ptr =3D mdata_buf; + mdt_ctx->phys =3D mdata_phys; + mdt_ctx->size =3D size; } =20 return ret ? : res.result[0]; @@ -694,18 +696,20 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image); =20 /** * qcom_scm_pas_metadata_release() - release metadata context - * @ctx: metadata context + * @ctx: pas context */ -void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx) +void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx) { - if (!ctx->ptr) - return; + struct qcom_scm_pas_metadata *mdt_ctx; =20 - dma_free_coherent(__scm->dev, ctx->size, ctx->ptr, ctx->phys); + mdt_ctx =3D ctx->metadata; + if (!mdt_ctx->ptr) + return; =20 - ctx->ptr =3D NULL; - ctx->phys =3D 0; - ctx->size =3D 0; + dma_free_coherent(__scm->dev, mdt_ctx->size, mdt_ctx->ptr, mdt_ctx->phys); + mdt_ctx->ptr =3D NULL; + mdt_ctx->phys =3D 0; + mdt_ctx->size =3D 0; } EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release); =20 diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q= 6v5_pas.c index 158bcd6cc85c..46a23fdefd48 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -117,8 +117,8 @@ struct qcom_pas { struct qcom_rproc_ssr ssr_subdev; struct qcom_sysmon *sysmon; =20 - struct qcom_scm_pas_metadata pas_metadata; - struct qcom_scm_pas_metadata dtb_pas_metadata; + struct qcom_scm_pas_context *pas_ctx; + struct qcom_scm_pas_context *dtb_pas_ctx; }; =20 static void qcom_pas_segment_dump(struct rproc *rproc, @@ -211,9 +211,9 @@ static int qcom_pas_unprepare(struct rproc *rproc) * auth_and_reset() was successful, but in other cases clean it up * here. */ - qcom_scm_pas_metadata_release(&pas->pas_metadata); + qcom_scm_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(&pas->dtb_pas_metadata); + qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); =20 return 0; } @@ -239,15 +239,8 @@ static int qcom_pas_load(struct rproc *rproc, const st= ruct firmware *fw) return ret; } =20 - ret =3D qcom_mdt_pas_init(pas->dev, pas->dtb_firmware, pas->dtb_firmware= _name, - pas->dtb_pas_id, pas->dtb_mem_phys, - &pas->dtb_pas_metadata); - if (ret) - goto release_dtb_firmware; - - ret =3D qcom_mdt_load_no_init(pas->dev, pas->dtb_firmware, pas->dtb_firm= ware_name, - pas->dtb_mem_region, pas->dtb_mem_phys, - pas->dtb_mem_size, &pas->dtb_mem_reloc); + ret =3D qcom_mdt_pas_load(pas->dtb_pas_ctx, pas->dtb_firmware, pas->dtb_= firmware_name, + pas->dtb_mem_region, &pas->dtb_mem_reloc); if (ret) goto release_dtb_metadata; } @@ -255,9 +248,7 @@ static int qcom_pas_load(struct rproc *rproc, const str= uct firmware *fw) return 0; =20 release_dtb_metadata: - qcom_scm_pas_metadata_release(&pas->dtb_pas_metadata); - -release_dtb_firmware: + qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); release_firmware(pas->dtb_firmware); =20 return ret; @@ -305,14 +296,8 @@ static int qcom_pas_start(struct rproc *rproc) } } =20 - ret =3D qcom_mdt_pas_init(pas->dev, pas->firmware, rproc->firmware, pas->= pas_id, - pas->mem_phys, &pas->pas_metadata); - if (ret) - goto disable_px_supply; - - ret =3D qcom_mdt_load_no_init(pas->dev, pas->firmware, rproc->firmware, - pas->mem_region, pas->mem_phys, pas->mem_size, - &pas->mem_reloc); + ret =3D qcom_mdt_pas_load(pas->pas_ctx, pas->firmware, rproc->firmware, + pas->mem_region, &pas->dtb_mem_reloc); if (ret) goto release_pas_metadata; =20 @@ -332,9 +317,9 @@ static int qcom_pas_start(struct rproc *rproc) goto release_pas_metadata; } =20 - qcom_scm_pas_metadata_release(&pas->pas_metadata); + qcom_scm_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(&pas->dtb_pas_metadata); + qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); =20 /* firmware is used to pass reference from qcom_pas_start(), drop it now = */ pas->firmware =3D NULL; @@ -342,9 +327,9 @@ static int qcom_pas_start(struct rproc *rproc) return 0; =20 release_pas_metadata: - qcom_scm_pas_metadata_release(&pas->pas_metadata); + qcom_scm_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(&pas->dtb_pas_metadata); + qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); disable_px_supply: if (pas->px_supply) regulator_disable(pas->px_supply); @@ -779,12 +764,33 @@ static int qcom_pas_probe(struct platform_device *pde= v) } =20 qcom_add_ssr_subdev(rproc, &pas->ssr_subdev, desc->ssr_name); + + pas->pas_ctx =3D qcom_scm_pas_context_init(pas->dev, pas->pas_id, pas->me= m_phys, + pas->mem_size); + if (IS_ERR(pas->pas_ctx)) { + ret =3D PTR_ERR(pas->pas_ctx); + goto remove_ssr_sysmon; + } + + pas->dtb_pas_ctx =3D qcom_scm_pas_context_init(pas->dev, pas->dtb_pas_id, + pas->dtb_mem_phys, pas->dtb_mem_size); + if (IS_ERR(pas->dtb_pas_ctx)) { + ret =3D PTR_ERR(pas->dtb_pas_ctx); + goto destroy_pas_ctx; + } + ret =3D rproc_add(rproc); if (ret) - goto remove_ssr_sysmon; + goto destroy_dtb_pas_ctx; =20 return 0; =20 +destroy_dtb_pas_ctx: + qcom_scm_pas_context_destroy(pas->dtb_pas_ctx); + +destroy_pas_ctx: + qcom_scm_pas_context_destroy(pas->pas_ctx); + remove_ssr_sysmon: qcom_remove_ssr_subdev(rproc, &pas->ssr_subdev); qcom_remove_sysmon_subdev(pas->sysmon); @@ -807,6 +813,8 @@ static void qcom_pas_remove(struct platform_device *pde= v) { struct qcom_pas *pas =3D platform_get_drvdata(pdev); =20 + qcom_scm_pas_context_destroy(pas->dtb_pas_ctx); + qcom_scm_pas_context_destroy(pas->pas_ctx); rproc_del(pas->rproc); =20 qcom_q6v5_deinit(&pas->q6v5); diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index 31855836b251..105a44f42ba7 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -234,13 +234,13 @@ EXPORT_SYMBOL_GPL(qcom_mdt_read_metadata); * @fw_name: name of the firmware, for construction of segment file names * @pas_id: PAS identifier * @mem_phys: physical address of allocated memory region - * @ctx: PAS metadata context, to be released by caller + * @ctx: PAS context, ctx->metadata to be released by caller * * Returns 0 on success, negative errno otherwise. */ int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, const char *fw_name, int pas_id, phys_addr_t mem_phys, - struct qcom_scm_pas_metadata *ctx) + struct qcom_scm_pas_context *ctx) { const struct elf32_phdr *phdrs; const struct elf32_phdr *phdr; @@ -505,8 +505,7 @@ int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx,= const struct firmware *f { int ret; =20 - ret =3D qcom_mdt_pas_init(ctx->dev, fw, firmware, ctx->pas_id, ctx->mem_p= hys, - ctx->metadata); + ret =3D qcom_mdt_pas_init(ctx->dev, fw, firmware, ctx->pas_id, ctx->mem_p= hys, ctx); if (ret) return ret; =20 diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index e82fdc200df7..af6ab837ad5a 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -84,8 +84,8 @@ void *qcom_scm_pas_context_init(struct device *dev, u32 p= as_id, phys_addr_t mem_ size_t mem_size); void qcom_scm_pas_context_destroy(struct qcom_scm_pas_context *ctx); int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size, - struct qcom_scm_pas_metadata *ctx); -void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx); + struct qcom_scm_pas_context *ctx); +void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx); int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size); int qcom_scm_pas_auth_and_reset(u32 pas_id); int qcom_scm_pas_shutdown(u32 pas_id); diff --git a/include/linux/soc/qcom/mdt_loader.h b/include/linux/soc/qcom/m= dt_loader.h index 2832e0717729..7d57746fbbfa 100644 --- a/include/linux/soc/qcom/mdt_loader.h +++ b/include/linux/soc/qcom/mdt_loader.h @@ -10,7 +10,6 @@ =20 struct device; struct firmware; -struct qcom_scm_pas_metadata; struct qcom_scm_pas_context; =20 #if IS_ENABLED(CONFIG_QCOM_MDT_LOADER) @@ -18,7 +17,7 @@ struct qcom_scm_pas_context; ssize_t qcom_mdt_get_size(const struct firmware *fw); int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, const char *fw_name, int pas_id, phys_addr_t mem_phys, - struct qcom_scm_pas_metadata *pas_metadata_ctx); + struct qcom_scm_pas_context *pas_ctx); int qcom_mdt_load(struct device *dev, const struct firmware *fw, const char *fw_name, int pas_id, void *mem_region, phys_addr_t mem_phys, size_t mem_size, @@ -43,7 +42,7 @@ static inline ssize_t qcom_mdt_get_size(const struct firm= ware *fw) =20 static inline int qcom_mdt_pas_init(struct device *dev, const struct firmw= are *fw, const char *fw_name, int pas_id, phys_addr_t mem_phys, - struct qcom_scm_pas_metadata *pas_metadata_ctx) + struct qcom_scm_pas_context *pas_ctx) { return -ENODEV; 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When Gunyah hypervisor is present, PAS SMC calls from Linux running at EL1 are trapped by Gunyah running @ EL2, which handles SHMbridge creation for both metadata and remoteproc carveout memory before invoking the calls to TZ. On SoCs running with a non-Gunyah-based hypervisor, Linux must take responsibility for creating the SHM bridge before invoking PAS SMC calls. For the auth_and_reset() call, the remoteproc carveout memory must first be registered with TZ via a SHMbridge SMC call and once authentication and reset are complete, the SHMbridge memory can be deregistered. Introduce qcom_scm_pas_prepare_and_auth_reset(), which sets up the SHM bridge over the remoteproc carveout memory when Linux operates at EL2. This behavior is indicated by a new field added to the PAS context data structure. The function then invokes the auth_and_reset SMC call. Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 48 ++++++++++++++++++++++++++++++= ++++ include/linux/firmware/qcom/qcom_scm.h | 2 ++ 2 files changed, 50 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 7b4ff3cb26ed..ab2543d44097 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -791,6 +791,54 @@ int qcom_scm_pas_auth_and_reset(u32 pas_id) } EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset); =20 +/** + * qcom_scm_pas_prepare_and_auth_reset() - Prepare, authenticate, and rese= t the + * remote processor + * + * @ctx: Context saved during call to qcom_scm_pas_context_init() + * + * This function performs the necessary steps to prepare a PAS subsystem, + * authenticate it using the provided metadata, and initiate a reset seque= nce. + * + * It should be used when Linux is in control setting up the IOMMU hardware + * for remote subsystem during secure firmware loading processes. The prep= aration + * step sets up a shmbridge over the firmware memory before TrustZone acce= sses the + * firmware memory region for authentication. The authentication step veri= fies + * the integrity and authenticity of the firmware or configuration using s= ecure + * metadata. Finally, the reset step ensures the subsystem starts in a cle= an and + * sane state. + * + * Return: 0 on success, negative errno on failure. + */ +int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx) +{ + u64 handle; + int ret; + + if (!ctx->has_iommu) + return qcom_scm_pas_auth_and_reset(ctx->pas_id); + + /* + * When Linux running @ EL1, Gunyah hypervisor running @ EL2 traps the + * auth_and_reset call and create an shmbridge on the remote subsystem + * memory region and then invokes a call to TrustZone to authenticate. + * When Linux runs @ EL2 Linux must create the shmbridge itself and then + * subsequently call TrustZone for authenticate and reset. + */ + ret =3D qcom_tzmem_shm_bridge_create(ctx->mem_phys, ctx->mem_size, &handl= e); + if (ret) { + dev_err(__scm->dev, "Failed to create shmbridge ret=3D%d %u\n", + ret, ctx->pas_id); + return ret; + } + + ret =3D qcom_scm_pas_auth_and_reset(ctx->pas_id); + qcom_tzmem_shm_bridge_delete(handle); + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_scm_pas_prepare_and_auth_reset); + /** * qcom_scm_pas_shutdown() - Shut down the remote processor * @pas_id: peripheral authentication service id diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index af6ab837ad5a..d6e7a6c9583d 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -78,6 +78,7 @@ struct qcom_scm_pas_context { phys_addr_t mem_phys; size_t mem_size; struct qcom_scm_pas_metadata *metadata; + bool has_iommu; }; =20 void *qcom_scm_pas_context_init(struct device *dev, u32 pas_id, phys_addr_= t mem_phys, @@ -90,6 +91,7 @@ int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, = phys_addr_t size); int qcom_scm_pas_auth_and_reset(u32 pas_id); int qcom_scm_pas_shutdown(u32 pas_id); bool qcom_scm_pas_supported(u32 pas_id); +int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx); =20 int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); --=20 2.50.1 From nobody Mon Feb 9 10:39:31 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4544A2EA157 for ; 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Reviewed-by: Bryan O'Donoghue Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 58 +++++++++++++++++++++++-------------= ---- 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index ab2543d44097..b8626897c8a7 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -612,6 +612,37 @@ void qcom_scm_pas_context_destroy(struct qcom_scm_pas_= context *ctx) } EXPORT_SYMBOL_GPL(qcom_scm_pas_context_destroy); =20 +static int __qcom_scm_pas_init_image(u32 pas_id, dma_addr_t mdata_phys, vo= id *metadata, + size_t size, struct qcom_scm_res *res) +{ + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_PIL, + .cmd =3D QCOM_SCM_PIL_PAS_INIT_IMAGE, + .arginfo =3D QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW), + .args[0] =3D pas_id, + .owner =3D ARM_SMCCC_OWNER_SIP, + }; + int ret; + + ret =3D qcom_scm_clk_enable(); + if (ret) + return ret; + + ret =3D qcom_scm_bw_enable(); + if (ret) + goto disable_clk; + + desc.args[1] =3D mdata_phys; + + ret =3D qcom_scm_call(__scm->dev, &desc, res); + qcom_scm_bw_disable(); + +disable_clk: + qcom_scm_clk_disable(); + + return ret; +} + /** * qcom_scm_pas_init_image() - Initialize peripheral authentication service * state machine for a given peripheral, using the @@ -633,17 +664,10 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *m= etadata, size_t size, struct qcom_scm_pas_context *ctx) { struct qcom_scm_pas_metadata *mdt_ctx; + struct qcom_scm_res res; dma_addr_t mdata_phys; void *mdata_buf; int ret; - struct qcom_scm_desc desc =3D { - .svc =3D QCOM_SCM_SVC_PIL, - .cmd =3D QCOM_SCM_PIL_PAS_INIT_IMAGE, - .arginfo =3D QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW), - .args[0] =3D pas_id, - .owner =3D ARM_SMCCC_OWNER_SIP, - }; - struct qcom_scm_res res; =20 /* * During the scm call memory protection will be enabled for the meta @@ -664,23 +688,7 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *me= tadata, size_t size, =20 memcpy(mdata_buf, metadata, size); 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We have taken care the things required for qcom_scm_pas_auth_and_reset(). Lets put these awareness of above conditions into qcom_scm_pas_init_image() and qcom_scm_pas_metadata_release(). Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 44 ++++++++++++++++++++++++++++++= +--- include/linux/firmware/qcom/qcom_scm.h | 5 +++- 2 files changed, 45 insertions(+), 4 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index b8626897c8a7..75811ba64c8f 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -643,6 +643,35 @@ static int __qcom_scm_pas_init_image(u32 pas_id, dma_a= ddr_t mdata_phys, void *me return ret; } =20 +static int qcom_scm_pas_prep_and_init_image(struct qcom_scm_pas_context *c= tx, + const void *metadata, size_t size) +{ + struct qcom_scm_pas_metadata *mdt_ctx; + struct qcom_scm_res res; + phys_addr_t mdata_phys; + void *mdata_buf; + int ret; + + mdt_ctx =3D ctx->metadata; + mdata_buf =3D qcom_tzmem_alloc(__scm->mempool, size, GFP_KERNEL); + if (!mdata_buf) + return -ENOMEM; + + memcpy(mdata_buf, metadata, size); + mdata_phys =3D qcom_tzmem_to_phys(mdata_buf); + + ret =3D __qcom_scm_pas_init_image(ctx->pas_id, mdata_phys, mdata_buf, siz= e, &res); + if (ret < 0 || !mdt_ctx) { + qcom_tzmem_free(mdata_buf); + } else if (mdt_ctx) { + mdt_ctx->ptr =3D mdata_buf; + mdt_ctx->addr.phys_addr =3D mdata_phys; + mdt_ctx->size =3D size; + } + + return ret ? : res.result[0]; +} + /** * qcom_scm_pas_init_image() - Initialize peripheral authentication service * state machine for a given peripheral, using the @@ -669,6 +698,9 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *met= adata, size_t size, void *mdata_buf; int ret; =20 + if (ctx && ctx->has_iommu) + return qcom_scm_pas_prep_and_init_image(ctx, metadata, size); + /* * During the scm call memory protection will be enabled for the meta * data blob, so make sure it's physically contiguous, 4K aligned and @@ -694,7 +726,7 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *met= adata, size_t size, } else if (ctx && ctx->metadata) { mdt_ctx =3D ctx->metadata; mdt_ctx->ptr =3D mdata_buf; - mdt_ctx->phys =3D mdata_phys; + mdt_ctx->addr.dma_addr =3D mdata_phys; mdt_ctx->size =3D size; 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Static resources are fixed like for example, memory-mapped addresses required by the subsystem and dynamic resources, such as shared memory in DDR etc., are determined at runtime during the boot process. For most of the Qualcomm SoCs, when run with Gunyah or older QHEE hypervisor, all the resources whether it is static or dynamic, is managed by the hypervisor. Dynamic resources if it is present for a remote processor will always be coming from secure world via SMC call while static resources may be present in remote processor firmware binary or it may be coming qcom_scm_pas_get_rsc_table() SMC call along with dynamic resources. Some of the remote processor drivers, such as video, GPU, IPA, etc., do not check whether resources are present in their remote processor firmware binary. In such cases, the caller of this function should set input_rt and input_rt_size as NULL and zero respectively. Remoteproc framework has method to check whether firmware binary contain resources or not and they should be pass resource table pointer to input_rt and resource table size to input_rt_size and this will be forwarded to TrustZone for authentication. TrustZone will then append the dynamic resources and return the complete resource table in output_rt More about documentation on resource table format can be found in include/linux/remoteproc.h Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 157 +++++++++++++++++++++++++++++= ++++ drivers/firmware/qcom/qcom_scm.h | 1 + include/linux/firmware/qcom/qcom_scm.h | 4 + 3 files changed, 162 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 75811ba64c8f..b8535b5a855b 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include =20 @@ -111,6 +112,10 @@ enum qcom_scm_qseecom_tz_cmd_info { QSEECOM_TZ_CMD_INFO_VERSION =3D 3, }; =20 +enum qcom_scm_rsctable_resp_type { + RSCTABLE_BUFFER_NOT_SUFFICIENT =3D 20, +}; + #define QSEECOM_MAX_APP_NAME_SIZE 64 #define SHMBRIDGE_RESULT_NOTSUPP 4 =20 @@ -800,6 +805,158 @@ int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t ad= dr, phys_addr_t size) } EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup); =20 +static int __qcom_scm_pas_get_rsc_table(u32 pas_id, void *input_rt, size_t= input_rt_size, + void **output_rt, size_t *output_rt_size) +{ + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_PIL, + .cmd =3D QCOM_SCM_PIL_PAS_GET_RSCTABLE, + .arginfo =3D QCOM_SCM_ARGS(5, QCOM_SCM_VAL, QCOM_SCM_RO, QCOM_SCM_VAL, + QCOM_SCM_RW, QCOM_SCM_VAL), + .args[0] =3D pas_id, + .owner =3D ARM_SMCCC_OWNER_SIP, + }; + void *input_rt_buf, *output_rt_buf; + struct resource_table *rsc; + struct qcom_scm_res res; + int ret; + + ret =3D qcom_scm_clk_enable(); + if (ret) + return ret; + + ret =3D qcom_scm_bw_enable(); + if (ret) + goto disable_clk; + + /* + * TrustZone can not accept buffer as NULL value as argument Hence, + * we need to pass a input buffer indicating that subsystem firmware + * does not have resource table by filling resource table structure. + */ + if (!input_rt) + input_rt_size =3D sizeof(*rsc); + + input_rt_buf =3D qcom_tzmem_alloc(__scm->mempool, input_rt_size, GFP_KERN= EL); + if (!input_rt_buf) { + ret =3D -ENOMEM; + goto disable_scm_bw; + } + + if (!input_rt) { + rsc =3D input_rt_buf; + rsc->num =3D 0; + } else { + memcpy(input_rt_buf, input_rt, input_rt_size); + } + + output_rt_buf =3D qcom_tzmem_alloc(__scm->mempool, *output_rt_size, GFP_K= ERNEL); + if (!output_rt_buf) { + ret =3D -ENOMEM; + goto free_input_rt_buf; + } + + desc.args[1] =3D qcom_tzmem_to_phys(input_rt_buf); + desc.args[2] =3D input_rt_size; + desc.args[3] =3D qcom_tzmem_to_phys(output_rt_buf); + desc.args[4] =3D *output_rt_size; + + /* + * Whether SMC fail or pass, res.result[2] will hold actual resource table + * size. + * + * if passed 'output_rt_size' buffer size is not sufficient to hold the + * resource table TrustZone sends, response code in res.result[1] as + * RSCTABLE_BUFFER_NOT_SUFFICIENT so that caller can retry this SMC call = with + * output_rt buffer with res.result[2] size. + */ + ret =3D qcom_scm_call(__scm->dev, &desc, &res); + *output_rt_size =3D res.result[2]; + if (!ret) + memcpy(*output_rt, output_rt_buf, *output_rt_size); + + if (ret && res.result[1] =3D=3D RSCTABLE_BUFFER_NOT_SUFFICIENT) + ret =3D -EAGAIN; + + qcom_tzmem_free(output_rt_buf); + +free_input_rt_buf: + qcom_tzmem_free(input_rt_buf); + +disable_scm_bw: + qcom_scm_bw_disable(); + +disable_clk: + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} + +/** + * qcom_scm_pas_get_rsc_table() - Retrieve the resource table in passed ou= tput buffer + * for a given peripheral. + * + * Qualcomm remote processor may rely on both static and dynamic resources= for + * its functionality. Static resources typically refer to memory-mapped ad= dresses + * required by the subsystem and are often embedded within the firmware bi= nary + * and dynamic resources, such as shared memory in DDR etc., are determine= d at + * runtime during the boot process. + * + * On Qualcomm Technologies devices, it's possible that static resources a= re not + * embedded in the firmware binary and instead are provided by TrustZone H= owever, + * dynamic resources are always expected to come from TrustZone. This indi= cates + * that for Qualcomm devices, all resources (static and dynamic) will be p= rovided + * by TrustZone via the SMC call. + * + * If the remote processor firmware binary does contain static resources, = they + * should be passed in input_rt. These will be forwarded to TrustZone for + * authentication. TrustZone will then append the dynamic resources and re= turn + * the complete resource table in output_rt. + * + * If the remote processor firmware binary does not include a resource tab= le, + * the caller of this function should set input_rt as NULL and input_rt_si= ze + * as zero respectively. + * + * More about documentation on resource table data structures can be found= in + * include/linux/rsc_table.h + * + * @ctx: PAS context + * @pas_id: peripheral authentication service id + * @input_rt: resource table buffer which is present in firmware bin= ary + * @input_rt_size: size of the resource table present in firmware binary + * @output_rt: buffer to which the both static and dynamic resources w= ill + * be returned. + * @output_rt_size: TrustZone expects caller should pass worst case size f= or + * the output_rt. + * + * Return: 0 on success and nonzero on failure. + * + * Upon successful return, output_rt will have the resource table and outp= ut_rt_size + * will have actual resource table size, + */ +int qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_context *ctx, void *inp= ut_rt, + size_t input_rt_size, void **output_rt, + size_t *output_rt_size) +{ + int ret; + + do { + *output_rt =3D devm_kzalloc(ctx->dev, *output_rt_size, GFP_KERNEL); + if (!*output_rt) + return -ENOMEM; + + ret =3D __qcom_scm_pas_get_rsc_table(ctx->pas_id, input_rt, + input_rt_size, output_rt, + output_rt_size); + if (ret) + devm_kfree(ctx->dev, *output_rt); + + } while (ret =3D=3D -EAGAIN); + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_scm_pas_get_rsc_table); + /** * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmw= are * and reset the remote processor diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_= scm.h index a56c8212cc0c..50d87c628d78 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -105,6 +105,7 @@ int qcom_scm_shm_bridge_enable(struct device *scm_dev); #define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06 #define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07 #define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a +#define QCOM_SCM_PIL_PAS_GET_RSCTABLE 0x21 =20 #define QCOM_SCM_SVC_IO 0x05 #define QCOM_SCM_IO_READ 0x01 diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index edb2cccee9af..a8b6185c0ed6 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -94,6 +94,10 @@ int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr,= phys_addr_t size); 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a=ed25519-sha256; t=1759855751; l=4661; i=mukesh.ojha@oss.qualcomm.com; s=20250708; h=from:subject:message-id; bh=z1QANoF5R7XjUfSd6H1T6pJE0Sh7B2+LMNkBRlo24CU=; b=1gI4rCJyvUWYmOCWI4RG2FEdbbUbSzgmpvJ3M26s9x4RPeuELNYZscH/BwFu7TPAM80/lxxZU k/88Q3DY3RECzrs7mqi66xAlVCx7+2icbpB0qpHb4Rc1Xo54un2KO5O X-Developer-Key: i=mukesh.ojha@oss.qualcomm.com; a=ed25519; pk=eX8dr/7d4HJz/HEXZIpe3c+Ukopa/wZmxH+5YV3gdNc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA0MDAzNyBTYWx0ZWRfXydLfFgBily/2 ky86PQ8M/dpNjaKEZ5oqW4iQ3w0eoo1yHVABjFeQGC+eduDapSxGb38YmTuFzZQ8ZDDaZmw4l3d p+67cOFkBq+1pwHO7/RQekIxAub9JKZfVIEHRoofwqk0mNUioUPc+O6UKEXSFYl7A9l4QM8ys7C zomvyRsmdF3Y4IMg8kqePIb/6kV9Vg4dUHcnGkaIaP5S7MMU52lh1KyJ0ZwXH/eV2hVfPa3vHPJ DhdaUVnrPgMeQ9D0mB1NM6sdBzo47xNexbuhFTSr5zAGPvMEOaxSB8I7JLNMfsjquzS1xuoJQL2 YC65JatFhz7YmvdrClPajkV4NqKwNqPBgoaYijEXj6yrBeUi6rND3lNtY+p1KqRg61Jjyp5GQtf 1wVC9uL5OGIvEpWWmwJWlpLk3PLRuQ== X-Proofpoint-ORIG-GUID: dvi_i9NJaThrcmWKae1J4yUA-xRvql5d X-Authority-Analysis: v=2.4 cv=WIdyn3sR c=1 sm=1 tr=0 ts=68e544b1 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=EUspDBNiAAAA:8 a=KMz1R6K7GWUeRkMKapkA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: dvi_i9NJaThrcmWKae1J4yUA-xRvql5d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-07_02,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 bulkscore=0 spamscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2510040037 Qualcomm remote processor may rely on static and dynamic resources for it to be functional. For most of the Qualcomm SoCs, when run with Gunyah or older QHEE hypervisor, all the resources whether it is static or dynamic, is managed by the hypervisor. Dynamic resources if it is present for a remote processor will always be coming from secure world via SMC call while static resources may be present in remote processor firmware binary or it may be coming from SMC call along with dynamic resources. Remoteproc already has method like rproc_elf_load_rsc_table() to check firmware binary has resources or not and if it is not having then we pass NULL and zero as input resource table and its size argument respectively to qcom_scm_pas_get_rsc_table() and while it has resource present then it should pass the present resources to Trustzone(TZ) so that it could authenticate the present resources and append dynamic resource to return in output_rt argument along with authenticated resources. Extend parse_fw callback to include SMC call to get resources from Trustzone and to leverage resource table parsing and mapping and unmapping code from the remoteproc framework. Signed-off-by: Mukesh Ojha --- drivers/remoteproc/qcom_q6v5_pas.c | 60 ++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q= 6v5_pas.c index 46a23fdefd48..ed7bd931dfd5 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -34,6 +34,7 @@ #define QCOM_PAS_DECRYPT_SHUTDOWN_DELAY_MS 100 =20 #define MAX_ASSIGN_COUNT 3 +#define MAX_RSCTABLE_SIZE SZ_16K =20 struct qcom_pas_data { int crash_reason_smem; @@ -412,6 +413,61 @@ static void *qcom_pas_da_to_va(struct rproc *rproc, u6= 4 da, size_t len, bool *is return pas->mem_region + offset; } =20 +static int qcom_pas_parse_firmware(struct rproc *rproc, const struct firmw= are *fw) +{ + size_t output_rt_size =3D MAX_RSCTABLE_SIZE; + struct qcom_pas *pas =3D rproc->priv; + struct resource_table *table =3D NULL; + void *output_rt; + size_t table_sz; + int ret; + + ret =3D qcom_register_dump_segments(rproc, fw); + if (ret) { + dev_err(pas->dev, "Error in registering dump segments\n"); + return ret; + } + + if (!rproc->has_iommu) + return ret; + + ret =3D rproc_elf_load_rsc_table(rproc, fw); + if (ret) + dev_info(&rproc->dev, "Error in loading resource table from firmware\n"); + + table =3D rproc->table_ptr; + table_sz =3D rproc->table_sz; + + /* + * Qualcomm remote processor may rely on static and dynamic resources for + * it to be functional. For most of the Qualcomm SoCs, when run with Guny= ah + * or older QHEE hypervisor, all the resources whether it is static or dy= namic, + * is managed by present hypervisor. Dynamic resources if it is present f= or + * a remote processor will always be coming from secure world via SMC call + * while static resources may be present in remote processor firmware bin= ary + * or it may be coming from SMC call along with dynamic resources. + * + * Here, we call rproc_elf_load_rsc_table() to check firmware binary has = resources + * or not and if it is not having then we pass NULL and zero as input res= ource + * table pointer and size respectively to the argument of qcom_scm_pas_ge= t_rsc_table() + * and this is even true for Qualcomm remote processor who does follow re= moteproc + * framework. + */ + ret =3D qcom_scm_pas_get_rsc_table(pas->pas_ctx, table, table_sz, &output= _rt, + &output_rt_size); + if (ret) { + dev_err(pas->dev, "error %d getting resource_table\n", ret); + return ret; + } + + kfree(rproc->cached_table); + rproc->cached_table =3D output_rt; + rproc->table_ptr =3D rproc->cached_table; + rproc->table_sz =3D output_rt_size; + + return ret; +} + static unsigned long qcom_pas_panic(struct rproc *rproc) { struct qcom_pas *pas =3D rproc->priv; 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This includes mapping memory regions and device memory resources for remote processors by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are later removed during teardown. Additionally, SHM bridge setup is required to enable memory protection for both remoteproc metadata and its memory regions. When the aforementioned hypervisor is absent, the operating system must perform these configurations instead. When Linux runs as the hypervisor (@ EL2) on a SoC, it will have its own device tree overlay file that specifies the firmware stream ID now managed by Linux for a particular remote processor. If the iommus property is specified in the remoteproc device tree node, it indicates that IOMMU configuration must be handled by Linux. In this case, the has_iommu flag is set for the remote processor, which ensures that the resource table, carveouts, and SHM bridge are properly configured before memory is passed to TrustZone for authentication. Otherwise, the has_iommu flag remains unset, which indicates default behavior. Enables Secure PAS support for remote processors when IOMMU configuration is managed by Linux. Signed-off-by: Mukesh Ojha --- drivers/remoteproc/qcom_q6v5_pas.c | 61 ++++++++++++++++++++++++++++++++++= ---- 1 file changed, 56 insertions(+), 5 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q= 6v5_pas.c index ed7bd931dfd5..940fd89d4fc4 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -255,6 +256,22 @@ static int qcom_pas_load(struct rproc *rproc, const st= ruct firmware *fw) return ret; } =20 +static void qcom_pas_unmap_carveout(struct rproc *rproc, phys_addr_t mem_p= hys, size_t size) +{ + if (rproc->has_iommu) + iommu_unmap(rproc->domain, mem_phys, size); +} + +static int qcom_pas_map_carveout(struct rproc *rproc, phys_addr_t mem_phys= , size_t size) +{ + int ret =3D 0; + + if (rproc->has_iommu) + ret =3D iommu_map(rproc->domain, mem_phys, mem_phys, size, + IOMMU_READ | IOMMU_WRITE, GFP_KERNEL); + return ret; +} + static int qcom_pas_start(struct rproc *rproc) { struct qcom_pas *pas =3D rproc->priv; @@ -289,11 +306,15 @@ static int qcom_pas_start(struct rproc *rproc) } =20 if (pas->dtb_pas_id) { - ret =3D qcom_scm_pas_auth_and_reset(pas->dtb_pas_id); + ret =3D qcom_pas_map_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_siz= e); + if (ret) + goto disable_px_supply; + + ret =3D qcom_scm_pas_prepare_and_auth_reset(pas->dtb_pas_ctx); if (ret) { dev_err(pas->dev, "failed to authenticate dtb image and release reset\n"); - goto disable_px_supply; + goto unmap_dtb_carveout; } } =20 @@ -304,18 +325,22 @@ static int qcom_pas_start(struct rproc *rproc) =20 qcom_pil_info_store(pas->info_name, pas->mem_phys, pas->mem_size); =20 - ret =3D qcom_scm_pas_auth_and_reset(pas->pas_id); + ret =3D qcom_pas_map_carveout(rproc, pas->mem_phys, pas->mem_size); + if (ret) + goto release_pas_metadata; + + ret =3D qcom_scm_pas_prepare_and_auth_reset(pas->pas_ctx); if (ret) { dev_err(pas->dev, "failed to authenticate image and release reset\n"); - goto release_pas_metadata; + goto unmap_carveout; } =20 ret =3D qcom_q6v5_wait_for_start(&pas->q6v5, msecs_to_jiffies(5000)); if (ret =3D=3D -ETIMEDOUT) { dev_err(pas->dev, "start timed out\n"); qcom_scm_pas_shutdown(pas->pas_id); - goto release_pas_metadata; + goto unmap_carveout; } =20 qcom_scm_pas_metadata_release(pas->pas_ctx); @@ -327,10 +352,16 @@ static int qcom_pas_start(struct rproc *rproc) =20 return 0; =20 +unmap_carveout: + qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size); release_pas_metadata: qcom_scm_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); + +unmap_dtb_carveout: + if (pas->dtb_pas_id) + qcom_pas_unmap_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size); disable_px_supply: if (pas->px_supply) regulator_disable(pas->px_supply); @@ -386,8 +417,12 @@ static int qcom_pas_stop(struct rproc *rproc) ret =3D qcom_scm_pas_shutdown(pas->dtb_pas_id); if (ret) dev_err(pas->dev, "failed to shutdown dtb: %d\n", ret); + + qcom_pas_unmap_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size); } =20 + qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size); 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However, it is possible for us to boot Linux at EL2 on these devices [1]. When running under Gunyah, remote processor firmware IOMMU streams is controlled by the Gunyah however when Linux take ownership of it in EL2, It need to configure it properly to use remote processor. Add a EL2-specific DT overlay and apply it to Lemans IOT variant devices to create -el2.dtb for each of them alongside "normal" dtb. [1] https://docs.qualcomm.com/bundle/publicresource/topics/80-70020-4/boot-deve= loper-touchpoints.html#uefi Signed-off-by: Mukesh Ojha --- arch/arm64/boot/dts/qcom/Makefile | 7 +++++- arch/arm64/boot/dts/qcom/lemans-el2.dtso | 41 ++++++++++++++++++++++++++++= ++++ 2 files changed, 47 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 296688f7cb26..e2eb6c4f8e25 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -35,6 +35,8 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk.dtb lemans-evk-camera-csi1-imx577-dtbs :=3D lemans-evk.dtb lemans-evk-camera-c= si1-imx577.dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-camera-csi1-imx577.dtb +lemans-evk-el2-dtbs :=3D lemans-evk.dtb lemans-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb @@ -136,7 +138,10 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-rb3gen2-vision-me= zzanine.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8300-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride.dtb -dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride-r3.dtb +qcs9100-ride-el2-dtbs :=3D qcs9100-ride.dtb lemans-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride.dtb qcs9100-ride-el2.dtb +qcs9100-ride-r3-el2-dtbs :=3D qcs9100-ride-r3.dtb lemans-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride-r3.dtb qcs9100-ride-r3-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qrb2210-rb1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qrb4210-rb2.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-el2.dtso b/arch/arm64/boot/dts= /qcom/lemans-el2.dtso new file mode 100644 index 000000000000..582b0a3a291a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-el2.dtso @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* + * Lemans specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +&iris { + /* TODO: Add video-firmware iommus to start IRIS from EL2 */ + status =3D "disabled"; +}; + +/* + * When running under Gunyah, remote processor firmware IOMMU streams is + * controlled by the Gunyah however when we take ownership of it in EL2, + * we need to configure it properly to use remote processor. + */ +&remoteproc_adsp { + iommus =3D <&apps_smmu 0x3000 0x0>; +}; + +&remoteproc_cdsp0 { + iommus =3D <&apps_smmu 0x21c0 0x0400>; +}; + +&remoteproc_cdsp1 { + iommus =3D <&apps_smmu 0x29c0 0x0400>; +}; + +&remoteproc_gpdsp0 { + iommus =3D <&apps_smmu 0x38a0 0x0>; +}; + +&remoteproc_gpdsp1 { + iommus =3D <&apps_smmu 0x38c0 0x0>; +}; --=20 2.50.1