From nobody Wed Dec 17 21:28:09 2025 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24436212B0A for ; Mon, 6 Oct 2025 23:21:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759792916; cv=none; b=Pak4pGIOLaRC2TVOU+zRFJjM5KXtq6cjxwIUYbywZxotmOyMOslm25gsDOCrXKe9hbDhtVHn+4zUxFrTlKTMm17bacCerojU+Ha5wFCF3EH6WzTfttkCS6kWp1/rXv5G5hVbkIEFhpWVvj7C7sTP8avL6oNC6i33RHzyrKO5ZzA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759792916; c=relaxed/simple; bh=D0B/3CMcDU9a2Vd2mxDjaxI/NV+yVz5OCUlM/Qg5GDg=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=UeaBBIlfD480sbVdgL1qqy4w0amQ6B5ZPLLtx0TCXVN16ZqLmNZe1Czd69LkmJ+KnZtiCbrabCvUa3P0jype/QwSNYr10jDlLmG+MuQJiMrv9XETitTxIfwLagLglLtP85TlbUAJsiqTGQUhJ+1RoKVImxBpacKiLUQ9xmidgQA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--royluo.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=ZsXrpdUg; arc=none smtp.client-ip=209.85.214.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--royluo.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="ZsXrpdUg" Received: by mail-pl1-f202.google.com with SMTP id d9443c01a7336-267fa90a2fbso70546895ad.1 for ; Mon, 06 Oct 2025 16:21:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1759792912; x=1760397712; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=w967xfPWK/pzLBoL3jCuMC/cxufe5CBtxtvzybdMgXo=; b=ZsXrpdUgAvhBlq5KyDZNSfTxlWhGx3/t1Z5gLg7EQA/J2BLYUqNAlsHjpE1CEger5n 3aH+Hp0naZFUmuZrafs80wp6VboeIdjtA0y5iHtdLEdwlk/PdnbGfp7/DtaTFVRS85+b 6DHnKsCcsAi5o1Len8tC8P7cbasC0hOZm02dATBu2NGWukXfWVAX66vOfoWRxBEtRg8N u4o/WPoCD2MmayEcca260w27TUIEQOWHsgqBbGbJ5JxlAMU0m8QTW6lT1MBKnICUek1G 9rPb5hO0JOlfIb+hR9gqjub3xa4v942htzT0wui5ziXbgzHngzwJVuS2HAs8Tn+MeVpV LVNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759792912; x=1760397712; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=w967xfPWK/pzLBoL3jCuMC/cxufe5CBtxtvzybdMgXo=; b=vgun/8JT+mOk/uukMdf4RGsMXdfOq9jc36eqxr9vepPUNBngSWmVnJzMcVLzxqdLrx 8uXY3P8M9Sfut7bGUNOhK1S/I1c0/8OMbSJDWOHT5Ij2WB4xiYeJdsu/9Af5ywo9RvEI Nl/tpnoZNe/Cl2r7UaOzJeUbB8QFmash+JAq1cC9jnE7ZM9UpyLJo0Mq3Y+WzTsndSUB fOj6FQtJq3RmE2aN8gKd7JUtJejaFwbSFR+9IDoIriRDc8tMp5v4zawfPU7S6bNPNGjW 1dKUi7GIRKn93QSCtUzku8AMzO5qq1sfd+gXxtzXS9nUSlC2WJ1+h8cq8TaT5J94HXSj WsXw== X-Forwarded-Encrypted: i=1; AJvYcCVue8WdUYfoGOAdr18W1XPjqctDx+gI9MkvSf1qZd1PW10tAsFIvCf1BufF1Wp6PE5gkdJ4VzT87okn6zE=@vger.kernel.org X-Gm-Message-State: AOJu0YzP36+RApvPcg6hmZ9+spyJtwIB3y5kdErJP6UyhtXwmNFzFa3/ K67s93tIro9O1XM7w+CyLtQwHPJP0FkiV2uQhZNGy98U6pib7C/7SAdjrSpuP/JgGUMVRhhPzZ3 4KGBuow== X-Google-Smtp-Source: AGHT+IGvhZqVEc02AsJccZ+iHZWg9bEyrWDQDXpBN8Z99t8bmtGsNvli1DohWrj10+/6dRyzYRLa4P/feg8= X-Received: from plbbg10.prod.google.com ([2002:a17:902:8e8a:b0:267:dbc3:f98d]) (user=royluo job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:2c0f:b0:28e:873d:8a with SMTP id d9443c01a7336-28ec9c5093dmr14795115ad.15.1759792912366; Mon, 06 Oct 2025 16:21:52 -0700 (PDT) Date: Mon, 6 Oct 2025 23:21:22 +0000 In-Reply-To: <20251006232125.1833979-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251006232125.1833979-1-royluo@google.com> X-Mailer: git-send-email 2.51.0.618.g983fd99d29-goog Message-ID: <20251006232125.1833979-2-royluo@google.com> Subject: [PATCH v1 1/4] usb: dwc3: Add Google SoC DWC3 glue driver From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds support for the DWC3 USB controller found on Google Tensor SoCs. The controller features dual-role functionality and hibernation. The primary focus is implementing hibernation support in host mode, enabling the controller to enter a low-power state (D3). This is particularly relevant during system power state transition and runtime power management for power efficiency. Highlights: - Align suspend callback with dwc3_suspend_common() for deciding between a full teardown and hibernation in host mode. - Integration with `usb_psw_pd` and `usb_top_pd` power domains, managing their states and device links to support hibernation. - A notifier callback dwc3_google_usb_psw_pd_notifier() for `usb_psw_pd` power domain events to manage controller state transitions to/from D3. - Coordination of the `usbc_non_sticky` reset during power state transitions, asserting it on D3 entry and deasserting on D0 entry in hibernation scenario. - Handling of U2 (high-speed) and U3 (super-speed) PME interrupts that are generated by remote wakeup during hibernation. Co-developed-by: Joy Chakraborty Signed-off-by: Joy Chakraborty Co-developed-by: Naveen Kumar Signed-off-by: Naveen Kumar Signed-off-by: Roy Luo --- drivers/usb/dwc3/Kconfig | 8 + drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-google.c | 597 +++++++++++++++++++++++++++++++++ 3 files changed, 606 insertions(+) create mode 100644 drivers/usb/dwc3/dwc3-google.c diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 310d182e10b5..685405464339 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -189,4 +189,12 @@ config USB_DWC3_RTK or dual-role mode. Say 'Y' or 'M' if you have such device. =20 +config USB_DWC3_GOOGLE + tristate "Google Platform" + depends on OF && COMMON_CLK && RESET_CONTROLLER + default USB_DWC3 + help + Support Google Tensor SoCs with DesignWare core USB3 IP. + Say 'Y' or 'M' if you have one such device. + endif diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 830e6c9e5fe0..a94982630657 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) +=3D dwc3-imx8mp.o obj-$(CONFIG_USB_DWC3_XILINX) +=3D dwc3-xilinx.o obj-$(CONFIG_USB_DWC3_OCTEON) +=3D dwc3-octeon.o obj-$(CONFIG_USB_DWC3_RTK) +=3D dwc3-rtk.o +obj-$(CONFIG_USB_DWC3_GOOGLE) +=3D dwc3-google.o diff --git a/drivers/usb/dwc3/dwc3-google.c b/drivers/usb/dwc3/dwc3-google.c new file mode 100644 index 000000000000..c9737da3ff3b --- /dev/null +++ b/drivers/usb/dwc3/dwc3-google.c @@ -0,0 +1,597 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dwc3-google.c - Google DWC3 Specific Glue Layer + * + * Copyright (c) 2025, Google LLC + * Author: Roy Luo + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "core.h" +#include "glue.h" + +/* HOST CFG registers */ +#define HC_STATUS_OFFSET 0x0 +#define HC_STATUS_CURRENT_POWER_STATE_U2PMU GENMASK(1, 0) +#define HC_STATUS_CURRENT_POWER_STATE_U3PMU GENMASK(4, 3) + +#define HOST_CFG1_OFFSET 0x4 +#define HOST_CFG1_PME_EN BIT(3) +#define HOST_CFG1_PM_POWER_STATE_REQUEST GENMASK(5, 4) +#define HOST_CFG1_PM_POWER_STATE_D0 0x0 +#define HOST_CFG1_PM_POWER_STATE_D3 0x3 + +/* USBINT registers */ +#define USBINT_CFG1_OFFSET 0x0 +#define USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK BIT(2) +#define USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK BIT(3) +#define USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN BIT(8) +#define USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN BIT(9) +#define USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR BIT(14) +#define USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR BIT(15) + +#define USBINT_STATUS_OFFSET 0x4 +#define USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW BIT(2) +#define USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW BIT(3) + +#define DWC3_GOOGLE_MAX_RESETS 5 + +struct dwc3_google { + struct device *dev; + struct dwc3 dwc; + struct clk_bulk_data *clks; + int num_clks; + struct reset_control_bulk_data rsts[DWC3_GOOGLE_MAX_RESETS]; + int num_rsts; + struct reset_control *usbc_non_sticky_rst; + struct device *usb_psw_pd; + struct device_link *usb_psw_pd_dl; + struct notifier_block usb_psw_pd_nb; + struct device *usb_top_pd; + struct device_link *usb_top_pd_dl; + void __iomem *host_cfg_base; + void __iomem *usbint_base; + int hs_pme_irq; + int ss_pme_irq; + bool is_hibernation; +}; + +#define to_dwc3_google(d) container_of((d), struct dwc3_google, dwc) + +static int dwc3_google_rst_init(struct dwc3_google *google) +{ + int ret; + + google->num_rsts =3D 5; + google->rsts[0].id =3D "usbc_non_sticky"; + google->rsts[1].id =3D "usbc_sticky"; + google->rsts[2].id =3D "usb_drd_bus"; + google->rsts[3].id =3D "u2phy_apb"; + google->rsts[4].id =3D "usb_top_csr"; + + ret =3D devm_reset_control_bulk_get_exclusive(google->dev, + google->num_rsts, + google->rsts); + + if (ret < 0) + return ret; + + google->usbc_non_sticky_rst =3D google->rsts[0].rstc; + + return 0; +} + +static int dwc3_google_set_pmu_state(struct dwc3_google *google, int state) +{ + u32 reg; + int ret; + + reg =3D readl(google->host_cfg_base + HOST_CFG1_OFFSET); + reg &=3D ~HOST_CFG1_PM_POWER_STATE_REQUEST; + reg |=3D (FIELD_PREP(HOST_CFG1_PM_POWER_STATE_REQUEST, state) | + HOST_CFG1_PME_EN); + writel(reg, google->host_cfg_base + HOST_CFG1_OFFSET); + + ret =3D readl_poll_timeout(google->host_cfg_base + HC_STATUS_OFFSET, reg, + (FIELD_GET(HC_STATUS_CURRENT_POWER_STATE_U2PMU, reg) =3D=3D state && + FIELD_GET(HC_STATUS_CURRENT_POWER_STATE_U3PMU, reg) =3D=3D state), + 10, 10000); + + if (ret) + dev_err(google->dev, "failed to set PMU state %d\n", state); + + return ret; +} + +/* + * Clear pme interrupts and report their status. + * The hardware requires write-1 then write-0 sequence to clear the interr= upt bits. + */ +static u32 dwc3_google_clear_pme_irqs(struct dwc3_google *google) +{ + u32 irq_status, reg_set, reg_clear; + + irq_status =3D readl(google->usbint_base + USBINT_STATUS_OFFSET); + irq_status &=3D (USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW | + USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW); + if (!irq_status) + return irq_status; + + reg_set =3D readl(google->usbint_base + USBINT_CFG1_OFFSET); + reg_clear =3D reg_set; + if (irq_status & USBINT_STATUS_USBDRD_PME_GEN_U2P_INTR_STS_RAW) { + reg_set |=3D USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR; + reg_clear &=3D ~USBINT_CFG1_USBDRD_PME_GEN_U2_INTR_CLR; + } + if (irq_status & USBINT_STATUS_USBDRD_PME_GEN_U3P_INTR_STS_RAW) { + reg_set |=3D USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR; + reg_clear &=3D ~USBINT_CFG1_USBDRD_PME_GEN_U3_INTR_CLR; + } + + writel(reg_set, google->usbint_base + USBINT_CFG1_OFFSET); + writel(reg_clear, google->usbint_base + USBINT_CFG1_OFFSET); + + return irq_status; +} + +static void dwc3_google_enable_pme_irq(struct dwc3_google *google) +{ + u32 reg; + + reg =3D readl(google->usbint_base + USBINT_CFG1_OFFSET); + reg &=3D ~(USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK | + USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK); + reg |=3D (USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN | + USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN); + writel(reg, google->usbint_base + USBINT_CFG1_OFFSET); + + enable_irq(google->hs_pme_irq); + enable_irq(google->ss_pme_irq); + enable_irq_wake(google->hs_pme_irq); + enable_irq_wake(google->ss_pme_irq); +} + +static void dwc3_google_disable_pme_irq(struct dwc3_google *google) +{ + u32 reg; + + reg =3D readl(google->usbint_base + USBINT_CFG1_OFFSET); + reg &=3D ~(USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_INT_EN | + USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_INT_EN); + reg |=3D (USBINT_CFG1_USBDRD_PME_GEN_U2P_INTR_MSK | + USBINT_CFG1_USBDRD_PME_GEN_U3P_INTR_MSK); + writel(reg, google->usbint_base + USBINT_CFG1_OFFSET); + + disable_irq_wake(google->hs_pme_irq); + disable_irq_wake(google->ss_pme_irq); + disable_irq_nosync(google->hs_pme_irq); + disable_irq_nosync(google->ss_pme_irq); +} + +static irqreturn_t dwc3_google_resume_irq(int irq, void *data) +{ + struct dwc3_google *google =3D data; + struct dwc3 *dwc =3D &google->dwc; + u32 irq_status, dr_role; + + irq_status =3D dwc3_google_clear_pme_irqs(google); + dr_role =3D dwc->current_dr_role; + + if (!irq_status || !google->is_hibernation || + dr_role !=3D DWC3_GCTL_PRTCAP_HOST) { + dev_warn(google->dev, "spurious pme irq %d, hibernation %d, dr_role %u\n= ", + irq, google->is_hibernation, dr_role); + return IRQ_HANDLED; + } + + if (dwc->xhci) + pm_runtime_resume(&dwc->xhci->dev); + + return IRQ_HANDLED; +} + +static int dwc3_google_request_irq(struct dwc3_google *google, struct plat= form_device *pdev, + const char *irq_name, const char *req_name) +{ + int ret; + int irq; + + irq =3D platform_get_irq_byname(pdev, irq_name); + if (irq < 0) { + dev_err(google->dev, "invalid irq name %s\n", irq_name); + return irq; + } + + irq_set_status_flags(irq, IRQ_NOAUTOEN); + ret =3D devm_request_threaded_irq(google->dev, irq, NULL, + dwc3_google_resume_irq, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + req_name, google); + if (ret < 0) { + dev_err(google->dev, "failed to request irq %s\n", req_name); + return ret; + } + + return irq; +} + +static int dwc3_google_usb_psw_pd_notifier(struct notifier_block *nb, unsi= gned long action, void *d) +{ + struct dwc3_google *google =3D container_of(nb, struct dwc3_google, usb_p= sw_pd_nb); + int ret; + + if (!google->is_hibernation) + return NOTIFY_OK; + + if (action =3D=3D GENPD_NOTIFY_OFF) { + dev_dbg(google->dev, "enter D3 power state\n"); + dwc3_google_set_pmu_state(google, HOST_CFG1_PM_POWER_STATE_D3); + ret =3D reset_control_assert(google->usbc_non_sticky_rst); + if (ret) + dev_err(google->dev, "non sticky reset assert failed: %d\n", ret); + } else if (action =3D=3D GENPD_NOTIFY_ON) { + dev_dbg(google->dev, "enter D0 power state\n"); + dwc3_google_clear_pme_irqs(google); + ret =3D reset_control_deassert(google->usbc_non_sticky_rst); + if (ret) + dev_err(google->dev, "non sticky reset deassert failed: %d\n", ret); + dwc3_google_set_pmu_state(google, HOST_CFG1_PM_POWER_STATE_D0); + } + + return NOTIFY_OK; +} + +static void dwc3_google_pm_domain_deinit(struct dwc3_google *google) +{ + if (google->usb_top_pd_dl) + device_link_del(google->usb_top_pd_dl); + + if (!IS_ERR_OR_NULL(google->usb_top_pd)) { + device_set_wakeup_capable(google->usb_top_pd, false); + dev_pm_domain_detach(google->usb_top_pd, true); + } + + if (google->usb_psw_pd_dl) + device_link_del(google->usb_psw_pd_dl); + + if (!IS_ERR_OR_NULL(google->usb_psw_pd)) { + dev_pm_genpd_remove_notifier(google->usb_psw_pd); + dev_pm_domain_detach(google->usb_psw_pd, true); + } +} + +static int dwc3_google_pm_domain_init(struct dwc3_google *google) +{ + int ret; + + /* + * Estalibsh PM RUNTIME link between dwc dev and its power domain usb_psw= _pd, + * register notifier block to handle hibernation. + */ + google->usb_psw_pd =3D dev_pm_domain_attach_by_name(google->dev, "usb_psw= _pd"); + if (IS_ERR_OR_NULL(google->usb_psw_pd)) { + dev_err(google->dev, "failed to get usb psw pd"); + ret =3D google->usb_psw_pd ? PTR_ERR(google->usb_psw_pd) : -ENODATA; + return ret; + } + + google->usb_psw_pd_nb.notifier_call =3D dwc3_google_usb_psw_pd_notifier; + ret =3D dev_pm_genpd_add_notifier(google->usb_psw_pd, &google->usb_psw_pd= _nb); + if (ret) { + dev_err(google->dev, "failed to add usb psw pd notifier"); + goto err; + } + + google->usb_psw_pd_dl =3D device_link_add(google->dev, google->usb_psw_pd, + DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (!google->usb_psw_pd_dl) { + dev_err(google->usb_psw_pd, "failed to add device link"); + ret =3D -ENODEV; + goto err; + } + + /* + * usb_top_pd is the parent power domain of usb_psw_pd. Keeping usb_top_p= d on + * while usb_psw_pd is off places the controller in a power-gated state, + * essential for hibernation. Acquire a handle to usb_top_pd and sets it = as + * wakeup-capable to allow the domain to be left on during system suspend. + */ + google->usb_top_pd =3D dev_pm_domain_attach_by_name(google->dev, "usb_top= _pd"); + if (IS_ERR_OR_NULL(google->usb_top_pd)) { + dev_err(google->dev, "failed to get usb top pd"); + ret =3D google->usb_top_pd ? PTR_ERR(google->usb_top_pd) : -ENODATA; + goto err; + } + device_set_wakeup_capable(google->usb_top_pd, true); + + google->usb_top_pd_dl =3D device_link_add(google->dev, google->usb_top_pd, + DL_FLAG_STATELESS); + if (!google->usb_top_pd_dl) { + dev_err(google->usb_top_pd, "failed to add device link"); + ret =3D -ENODEV; + goto err; + } + + return 0; + +err: + dwc3_google_pm_domain_deinit(google); + + return ret; +} + +static int dwc3_google_probe(struct platform_device *pdev) +{ + struct dwc3_probe_data probe_data =3D {}; + struct device *dev =3D &pdev->dev; + struct dwc3_google *google; + struct resource *res; + int ret; + + google =3D devm_kzalloc(&pdev->dev, sizeof(*google), GFP_KERNEL); + if (!google) + return -ENOMEM; + + google->dev =3D &pdev->dev; + + ret =3D dwc3_google_pm_domain_init(google); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "failed to init pdom\n"); + + ret =3D devm_clk_bulk_get_all_enabled(dev, &google->clks); + if (ret < 0) { + ret =3D dev_err_probe(&pdev->dev, ret, "failed to get and enable clks\n"= ); + goto err_deinit_pdom; + } + google->num_clks =3D ret; + + ret =3D dwc3_google_rst_init(google); + if (ret) { + ret =3D dev_err_probe(&pdev->dev, ret, "failed to get resets\n"); + goto err_deinit_pdom; + } + + ret =3D reset_control_bulk_deassert(google->num_rsts, google->rsts); + if (ret) { + ret =3D dev_err_probe(&pdev->dev, ret, "failed to deassert rsts\n"); + goto err_deinit_pdom; + } + + ret =3D dwc3_google_request_irq(google, pdev, "hs_pme_irq", "USB HS wakeu= p"); + if (ret < 0) { + ret =3D dev_err_probe(&pdev->dev, ret, "failed to request hs pme irq"); + goto err_reset_assert; + } + google->hs_pme_irq =3D ret; + + ret =3D dwc3_google_request_irq(google, pdev, "ss_pme_irq", "USB SS wakeu= p"); + if (ret < 0) { + ret =3D dev_err_probe(&pdev->dev, ret, "failed to request ss pme irq"); + goto err_reset_assert; + } + google->ss_pme_irq =3D ret; + + google->host_cfg_base =3D + devm_platform_ioremap_resource_byname(pdev, "host_cfg_csr"); + if (IS_ERR(google->host_cfg_base)) { + ret =3D dev_err_probe(&pdev->dev, PTR_ERR(google->host_cfg_base), + "invalid host cfg csr\n"); + goto err_reset_assert; + } + + google->usbint_base =3D + devm_platform_ioremap_resource_byname(pdev, "usbint_csr"); + if (IS_ERR(google->usbint_base)) { + ret =3D dev_err_probe(&pdev->dev, PTR_ERR(google->usbint_base), + "invalid usbint csr\n"); + goto err_reset_assert; + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "dwc3_core"); + if (!res) { + ret =3D dev_err_probe(dev, -ENODEV, "invalid dwc3 core memory\n"); + goto err_reset_assert; + } + + device_init_wakeup(dev, true); + + google->dwc.dev =3D dev; + probe_data.dwc =3D &google->dwc; + probe_data.res =3D res; + probe_data.ignore_clocks_and_resets =3D true; + ret =3D dwc3_core_probe(&probe_data); + if (ret) { + ret =3D dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); + goto err_reset_assert; + } + + return 0; + +err_reset_assert: + reset_control_bulk_assert(google->num_rsts, google->rsts); + +err_deinit_pdom: + dwc3_google_pm_domain_deinit(google); + + return ret; +} + +static void dwc3_google_remove(struct platform_device *pdev) +{ + struct dwc3 *dwc =3D platform_get_drvdata(pdev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + + dwc3_core_remove(&google->dwc); + + reset_control_bulk_assert(google->num_rsts, google->rsts); + + dwc3_google_pm_domain_deinit(google); +} + +static int dwc3_google_suspend(struct dwc3_google *google, pm_message_t ms= g) +{ + if (pm_runtime_suspended(google->dev)) + return 0; + + if (google->dwc.current_dr_role =3D=3D DWC3_GCTL_PRTCAP_HOST) { + /* + * Follow dwc3_suspend_common() guidelines for deciding between + * a full teardown and hibernation. + */ + if (PMSG_IS_AUTO(msg) || device_may_wakeup(google->dev)) { + dev_dbg(google->dev, "enter hibernation"); + pm_runtime_get_sync(google->usb_top_pd); + device_wakeup_enable(google->usb_top_pd); + dwc3_google_enable_pme_irq(google); + google->is_hibernation =3D true; + return 0; + } + } + + reset_control_bulk_assert(google->num_rsts, google->rsts); + clk_bulk_disable_unprepare(google->num_clks, google->clks); + + return 0; +} + +static int dwc3_google_resume(struct dwc3_google *google, pm_message_t msg) +{ + int ret; + + if (google->is_hibernation) { + dev_dbg(google->dev, "exit hibernation"); + dwc3_google_disable_pme_irq(google); + device_wakeup_disable(google->usb_top_pd); + pm_runtime_put_sync(google->usb_top_pd); + google->is_hibernation =3D false; + return 0; + } + + ret =3D clk_bulk_prepare_enable(google->num_clks, google->clks); + if (ret) + return ret; + + ret =3D reset_control_bulk_deassert(google->num_rsts, google->rsts); + if (ret) { + clk_bulk_disable_unprepare(google->num_clks, google->clks); + return ret; + } + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int dwc3_google_pm_suspend(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + int ret; + + ret =3D dwc3_pm_suspend(&google->dwc); + if (ret) + return ret; + + return dwc3_google_suspend(google, PMSG_SUSPEND); +} + +static int dwc3_google_pm_resume(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + int ret; + + ret =3D dwc3_google_resume(google, PMSG_RESUME); + if (ret) + return ret; + + return dwc3_pm_resume(&google->dwc); +} + +static void dwc3_google_complete(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + + dwc3_pm_complete(dwc); +} + +static int dwc3_google_prepare(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + + return dwc3_pm_prepare(dwc); +} +#else +#define dwc3_google_complete NULL +#define dwc3_google_prepare NULL +#endif /* CONFIG_PM_SLEEP */ + +#ifdef CONFIG_PM +static int dwc3_google_runtime_suspend(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + int ret; + + ret =3D dwc3_runtime_suspend(&google->dwc); + if (ret) + return ret; + + return dwc3_google_suspend(google, PMSG_AUTO_SUSPEND); +} + +static int dwc3_google_runtime_resume(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_google *google =3D to_dwc3_google(dwc); + int ret; + + ret =3D dwc3_google_resume(google, PMSG_AUTO_RESUME); + if (ret) + return ret; + + return dwc3_runtime_resume(&google->dwc); +} + +static int dwc3_google_runtime_idle(struct device *dev) +{ + return dwc3_runtime_idle(dev_get_drvdata(dev)); +} +#endif /* CONFIG_PM */ + +static const struct dev_pm_ops dwc3_google_dev_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(dwc3_google_pm_suspend, dwc3_google_pm_resume) + SET_RUNTIME_PM_OPS(dwc3_google_runtime_suspend, dwc3_google_runtime_resum= e, + dwc3_google_runtime_idle) + .complete =3D dwc3_google_complete, + .prepare =3D dwc3_google_prepare, +}; + +static const struct of_device_id dwc3_google_of_match[] =3D { + { .compatible =3D "google,snps-dwc3" }, + { } +}; +MODULE_DEVICE_TABLE(of, dwc3_google_of_match); + +static struct platform_driver dwc3_google_driver =3D { + .probe =3D dwc3_google_probe, + .remove =3D dwc3_google_remove, + .driver =3D { + .name =3D "google-dwc3", + .pm =3D &dwc3_google_dev_pm_ops, + .of_match_table =3D dwc3_google_of_match, + }, +}; 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AJvYcCVGBs59Z7rTO4ihcBFS5Kr20TJ9jQylYrB6UVjK9Tq9J+upY/U5OPk1+GVjphaODjeMtnWQtIUsLFp+OGY=@vger.kernel.org X-Gm-Message-State: AOJu0Yy5zBhftuvbnOh/MEJ8rVi8OPJHxVby/WCevWOz4KKfKMFazONv po7omN5JESXFnAUbQeXDfJkVT9Yds+it85z5IExpqWKd38q2iEzQx5H8Vdd5mR4XVxaWmBto76p FLW/jsw== X-Google-Smtp-Source: AGHT+IHuvSLSe+7hqIjhfAafsJ/Rg53JuStEyumsyKGui3lJI0P+5OWjCcwfbXPLbHA2q9kxTGLsRs1awBo= X-Received: from oala19.prod.google.com ([2002:a05:6870:b153:b0:359:cc61:b60e]) (user=royluo job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6870:959a:b0:345:bbd6:b0a1 with SMTP id 586e51a60fabf-3b10283e13cmr8039798fac.30.1759792915730; Mon, 06 Oct 2025 16:21:55 -0700 (PDT) Date: Mon, 6 Oct 2025 23:21:23 +0000 In-Reply-To: <20251006232125.1833979-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251006232125.1833979-1-royluo@google.com> X-Mailer: git-send-email 2.51.0.618.g983fd99d29-goog Message-ID: <20251006232125.1833979-3-royluo@google.com> Subject: [PATCH v1 2/4] dt-bindings: usb: dwc3: Add Google SoC DWC3 USB From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the DWC3 USB bindings for Google Tensor SoCs. Signed-off-by: Roy Luo --- .../bindings/usb/google,snps-dwc3.yaml | 144 ++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/google,snps-dwc3.= yaml diff --git a/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml b/= Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml new file mode 100644 index 000000000000..3e8bcc0c2cef --- /dev/null +++ b/Documentation/devicetree/bindings/usb/google,snps-dwc3.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2025, Google LLC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/google,snps-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google DWC3 USB SoC Controller + +maintainers: + - Roy Luo + +description: + Describes the Google DWC3 USB block, based on Synopsys DWC3 IP. + +properties: + compatible: + items: + - enum: + - google,lga-dwc3 + - const: google,snps-dwc3 + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + description: | + The following memory regions must present: + - dwc3_core: Core DWC3 IP registers. + - host_cfg_csr: Hibernation control registers. + - usbint_csr: Hibernation interrupt registers. + items: + - const: dwc3_core + - const: host_cfg_csr + - const: usbint_csr + + interrupts: + minItems: 3 + maxItems: 3 + + interrupt-names: + description: | + The following interrupts must present: + - dwc_usb3: Core DWC3 interrupt. + - hs_pme_irq: High speed remote wakeup interrupt for hibernation. + - ss_pme_irq: Super speed remote wakeup interrupt for hibernation. + items: + - const: dwc_usb3 + - const: hs_pme_irq + - const: ss_pme_irq + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + minItems: 3 + maxItems: 3 + + resets: + minItems: 5 + maxItems: 5 + + reset-names: + items: + - const: usbc_non_sticky + - const: usbc_sticky + - const: usb_drd_bus + - const: u2phy_apb + - const: usb_top_csr + + power-domains: + minItems: 2 + maxItems: 2 + + power-domain-names: + description: | + The following power domain must present: + - usb_psw_pd: The child power domain of usb_top_pd. Turning it o= n puts the controller + into full power state, turning it off puts the co= ntroller into power + gated state. + - usb_top_pd: The parent power domain of usb_psw_pd. Turning it = on puts the controller + into power gated state, turning it off completely= shuts off the + controller. + items: + - const: usb_psw_pd + - const: usb_top_pd + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - resets + - reset-names + - power-domains + - power-domain-names + +allOf: + - $ref: snps,dwc3-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + usb@c400000 { + compatible =3D "google,lga-dwc3", "google,snps-dwc3"; + reg =3D <0 0x0c400000 0 0xd060>, <0 0x0c450000 0 0x14>, <0 0x= 0c450020 0 0x8>; + reg-names =3D "dwc3_core", "host_cfg_csr", "usbint_csr"; + interrupts =3D , + , + ; + interrupt-names =3D "dwc_usb3", "hs_pme_irq", "ss_pme_irq"; + clocks =3D <&hsion_usbc_non_sticky_clk>, <&hsion_usbc_sticky_= clk>, + <&hsion_u2phy_apb_clk>; + clock-names =3D "usbc_non_sticky", "usbc_sticky", "u2phy_apb"; + resets =3D <&hsion_resets_usbc_non_sticky>, <&hsion_resets_usb= c_sticky>, + <&hsion_resets_usb_drd_bus>, <&hsion_resets_u2phy_apb= >, + <&hsion_resets_usb_top_csr>; + reset-names =3D "usbc_non_sticky", "usbc_sticky", + "usb_drd_bus", "u2phy_apb", + "usb_top_csr"; + power-domains =3D <&hsio_n_usb_psw_pd>, <&hsio_n_usb_pd>; + power-domain-names =3D "usb_psw_pd", "usb_top_pd"; + phys =3D <&usb_phy 0>; + phy-names =3D "usb2-phy"; + snps,quirk-frame-length-adjustment =3D <0x20>; + snps,gfladj-refclk-lpm-sel-quirk; + snps,incr-burst-type-adjustment =3D <4>; + }; + }; +... --=20 2.51.0.618.g983fd99d29-goog From nobody Wed Dec 17 21:28:09 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA35C221578 for ; Mon, 6 Oct 2025 23:21:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759792921; cv=none; b=kDN+O3yjFy9tCSdYDSydB5Vr0ZpxXD/KqM53O52uW4QgCyeeILs0HoKeyAf46axuAMpxqUF9xn/mkeEd8cnm2nYioVOn+1bcCleU+TWckAk/wKxo7ndQtA2V/wCM8kxJHumu2FFDICNkkGQw/ETZJer+vRbI5gpjfIh5lpHXPac= ARC-Message-Signature: i=1; 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AJvYcCUuLuLAbcsgFRTeXQidCXdswD7lXQOfnfKYzdvkuyEh3Q70nfF10uYyHQYzzejujQF7cbfH2LRZRXjfGRE=@vger.kernel.org X-Gm-Message-State: AOJu0YxwsyDk/km52EIMnhChs0SLbcVtlGekw85wMRBxYPSR6dINdUrn ac9zuKy036Dq1/asmRTzzmHgEpgYja18J/KGaqPue1VHMdnJLmZybMwIDbLt5q+Qu8mAmZ24VWc rialI7A== X-Google-Smtp-Source: AGHT+IHCrazxJE0VodxQkYh/ySiAwffUOkcLakkOzySzdYCDetGseFf+qCf9zIoQeCWY/XlH7ga9uvTYgzY= X-Received: from pjbb16.prod.google.com ([2002:a17:90a:110:b0:32f:46d:993b]) (user=royluo job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:4a8f:b0:330:852e:2bcc with SMTP id 98e67ed59e1d1-339c27b94e9mr15676987a91.21.1759792918222; Mon, 06 Oct 2025 16:21:58 -0700 (PDT) Date: Mon, 6 Oct 2025 23:21:24 +0000 In-Reply-To: <20251006232125.1833979-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251006232125.1833979-1-royluo@google.com> X-Mailer: git-send-email 2.51.0.618.g983fd99d29-goog Message-ID: <20251006232125.1833979-4-royluo@google.com> Subject: [PATCH v1 3/4] usb: dwc3: Add Google SoC USB PHY driver From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support the USB PHY found on Google Tensor SoCs. This particular USB PHY supports both high-speed and super-speed operations, and is paired with the SNPS DWC3 controller that's also integrated on the SoCs. This initial patch specifically adds functionality for high-speed. Co-developed-by: Joy Chakraborty Signed-off-by: Joy Chakraborty Co-developed-by: Naveen Kumar Signed-off-by: Naveen Kumar Signed-off-by: Roy Luo --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/google/Kconfig | 15 ++ drivers/phy/google/Makefile | 2 + drivers/phy/google/phy-google-usb.c | 286 ++++++++++++++++++++++++++++ 5 files changed, 305 insertions(+) create mode 100644 drivers/phy/google/Kconfig create mode 100644 drivers/phy/google/Makefile create mode 100644 drivers/phy/google/phy-google-usb.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 58c911e1b2d2..7772c04d5f5c 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -106,6 +106,7 @@ source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" source "drivers/phy/cadence/Kconfig" source "drivers/phy/freescale/Kconfig" +source "drivers/phy/google/Kconfig" source "drivers/phy/hisilicon/Kconfig" source "drivers/phy/ingenic/Kconfig" source "drivers/phy/lantiq/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index c670a8dac468..1b6dd784351c 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -18,6 +18,7 @@ obj-y +=3D allwinner/ \ broadcom/ \ cadence/ \ freescale/ \ + google/ \ hisilicon/ \ ingenic/ \ intel/ \ diff --git a/drivers/phy/google/Kconfig b/drivers/phy/google/Kconfig new file mode 100644 index 000000000000..2ba13b77c819 --- /dev/null +++ b/drivers/phy/google/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Phy drivers for Google platforms +# +config PHY_GOOGLE_USB + tristate "Google Tensor SoC series USB PHY driver" + depends on HAS_IOMEM + depends on OF + depends on TYPEC + depends on USB_DWC3_GOOGLE + select GENERIC_PHY + default y + help + Add support for the USB PHY on Google SoC series, providing + the PHY interface for the integrated USB DRD controller. diff --git a/drivers/phy/google/Makefile b/drivers/phy/google/Makefile new file mode 100644 index 000000000000..f926bd033533 --- /dev/null +++ b/drivers/phy/google/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_GOOGLE_USB) +=3D phy-google-usb.o diff --git a/drivers/phy/google/phy-google-usb.c b/drivers/phy/google/phy-g= oogle-usb.c new file mode 100644 index 000000000000..f666ea6fbd4e --- /dev/null +++ b/drivers/phy/google/phy-google-usb.c @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-google-usb.c - Google USB PHY driver + * + * Copyright (C) 2025, Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define USBCS_USB2PHY_CFG19_OFFSET 0x0 +#define USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV GENMASK(19, 8) + +#define USBCS_USB2PHY_CFG21_OFFSET 0x8 +#define USBCS_USB2PHY_CFG21_PHY_ENABLE BIT(12) +#define USBCS_USB2PHY_CFG21_REF_FREQ_SEL GENMASK(15, 13) +#define USBCS_USB2PHY_CFG21_PHY_TX_DIG_BYPASS_SEL BIT(19) + +#define USBCS_PHY_CFG1_OFFSET 0x28 +#define USBCS_PHY_CFG1_SYS_VBUSVALID BIT(17) + +#define USBCS_TOP_CTRL_CFG1_OFFSET 0x0 +#define USBCS_TOP_CTRL_CFG1_USB2ONLY_MODE BIT(5) + +enum google_usb_phy_id { + GOOGLE_USB2_PHY, + GOOGLE_USB_PHY_NUM, +}; + +struct google_usb_phy_instance { + int index; + struct phy *phy; + struct clk *clk; + struct reset_control *rst; +}; + +struct google_usb_phy { + struct device *dev; + void __iomem *usb2_cfg_base; + void __iomem *dp_top_base; + void __iomem *usb_top_cfg_base; + struct google_usb_phy_instance insts[GOOGLE_USB_PHY_NUM]; + /* serialize phy access */ + struct mutex phy_mutex; + struct typec_switch_dev *sw; + enum typec_orientation orientation; +}; + +static inline struct google_usb_phy *to_google_usb_phy(struct google_usb_p= hy_instance *inst) +{ + return container_of(inst, struct google_usb_phy, insts[inst->index]); +} + +static void set_vbus_valid(struct google_usb_phy *gphy) +{ + u32 reg; + + if (gphy->orientation =3D=3D TYPEC_ORIENTATION_NONE) { + reg =3D readl(gphy->dp_top_base + USBCS_PHY_CFG1_OFFSET); + reg &=3D ~USBCS_PHY_CFG1_SYS_VBUSVALID; + writel(reg, gphy->dp_top_base + USBCS_PHY_CFG1_OFFSET); + } else { + reg =3D readl(gphy->dp_top_base + USBCS_PHY_CFG1_OFFSET); + reg |=3D USBCS_PHY_CFG1_SYS_VBUSVALID; + writel(reg, gphy->dp_top_base + USBCS_PHY_CFG1_OFFSET); + } +} + +static int google_usb_set_orientation(struct typec_switch_dev *sw, + enum typec_orientation orientation) +{ + struct google_usb_phy *gphy =3D typec_switch_get_drvdata(sw); + + dev_dbg(gphy->dev, "set orientation %d\n", orientation); + + gphy->orientation =3D orientation; + + if (pm_runtime_suspended(gphy->dev)) + return 0; + + guard(mutex)(&gphy->phy_mutex); + + set_vbus_valid(gphy); + + return 0; +} + +static int google_usb2_phy_init(struct phy *_phy) +{ + struct google_usb_phy_instance *inst =3D phy_get_drvdata(_phy); + struct google_usb_phy *gphy =3D to_google_usb_phy(inst); + u32 reg; + int ret =3D 0; + + dev_dbg(gphy->dev, "initializing usb2 phy\n"); + + guard(mutex)(&gphy->phy_mutex); + + /* + * TODO: usb2only mode should be removed once usb3 is supported + */ + reg =3D readl(gphy->usb_top_cfg_base + USBCS_TOP_CTRL_CFG1_OFFSET); + reg |=3D USBCS_TOP_CTRL_CFG1_USB2ONLY_MODE; + writel(reg, gphy->usb_top_cfg_base + USBCS_TOP_CTRL_CFG1_OFFSET); + + reg =3D readl(gphy->usb2_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + reg &=3D ~USBCS_USB2PHY_CFG21_PHY_TX_DIG_BYPASS_SEL; + reg &=3D ~USBCS_USB2PHY_CFG21_REF_FREQ_SEL; + reg |=3D FIELD_PREP(USBCS_USB2PHY_CFG21_REF_FREQ_SEL, 0); + writel(reg, gphy->usb2_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + + reg =3D readl(gphy->usb2_cfg_base + USBCS_USB2PHY_CFG19_OFFSET); + reg &=3D ~USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV; + reg |=3D FIELD_PREP(USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV, 368); + writel(reg, gphy->usb2_cfg_base + USBCS_USB2PHY_CFG19_OFFSET); + + set_vbus_valid(gphy); + + ret =3D clk_prepare_enable(inst->clk); + if (ret) + return ret; + + ret =3D reset_control_deassert(inst->rst); + if (ret) { + clk_disable_unprepare(inst->clk); + return ret; + } + + reg =3D readl(gphy->usb2_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + reg |=3D USBCS_USB2PHY_CFG21_PHY_ENABLE; + writel(reg, gphy->usb2_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + + return ret; +} + +static int google_usb2_phy_exit(struct phy *_phy) +{ + struct google_usb_phy_instance *inst =3D phy_get_drvdata(_phy); + struct google_usb_phy *gphy =3D to_google_usb_phy(inst); + u32 reg; + + dev_dbg(gphy->dev, "exiting usb2 phy\n"); + + guard(mutex)(&gphy->phy_mutex); + + reg =3D readl(gphy->usb2_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + reg &=3D ~USBCS_USB2PHY_CFG21_PHY_ENABLE; + writel(reg, gphy->usb2_cfg_base + USBCS_USB2PHY_CFG21_OFFSET); + + reset_control_assert(inst->rst); + clk_disable_unprepare(inst->clk); + + return 0; +} + +static const struct phy_ops google_usb2_phy_ops =3D { + .init =3D google_usb2_phy_init, + .exit =3D google_usb2_phy_exit, +}; + +static struct phy *google_usb_phy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct google_usb_phy *gphy =3D dev_get_drvdata(dev); + + if (args->args[0] >=3D GOOGLE_USB_PHY_NUM) { + dev_err(dev, "invalid PHY index requested from DT\n"); + return ERR_PTR(-ENODEV); + } + return gphy->insts[args->args[0]].phy; +} + +static int google_usb_phy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct google_usb_phy *gphy; + struct phy *phy; + struct google_usb_phy_instance *inst; + struct phy_provider *phy_provider; + struct typec_switch_desc sw_desc =3D { }; + int ret; + + gphy =3D devm_kzalloc(dev, sizeof(*gphy), GFP_KERNEL); + if (!gphy) + return -ENOMEM; + + dev_set_drvdata(dev, gphy); + gphy->dev =3D dev; + + ret =3D devm_mutex_init(dev, &gphy->phy_mutex); + if (ret) + return ret; + + gphy->usb2_cfg_base =3D + devm_platform_ioremap_resource_byname(pdev, "usb2_cfg_csr"); + if (IS_ERR(gphy->usb2_cfg_base)) + return dev_err_probe(dev, PTR_ERR(gphy->usb2_cfg_base), + "invalid usb2 cfg csr\n"); + + gphy->dp_top_base =3D + devm_platform_ioremap_resource_byname(pdev, "dp_top_csr"); + if (IS_ERR(gphy->dp_top_base)) + return dev_err_probe(dev, PTR_ERR(gphy->dp_top_base), + "invalid dp top csr\n"); + + gphy->usb_top_cfg_base =3D + devm_platform_ioremap_resource_byname(pdev, "usb_top_cfg_csr"); + if (IS_ERR(gphy->usb_top_cfg_base)) + return dev_err_probe(dev, PTR_ERR(gphy->usb_top_cfg_base), + "invalid usb top cfg csr\n"); + + inst =3D &gphy->insts[GOOGLE_USB2_PHY]; + inst->index =3D GOOGLE_USB2_PHY; + phy =3D devm_phy_create(dev, NULL, &google_usb2_phy_ops); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), + "failed to create usb2 phy instance\n"); + inst->phy =3D phy; + phy_set_drvdata(phy, inst); + inst->clk =3D devm_clk_get(dev, "usb2_phy_clk"); + if (IS_ERR(inst->clk)) + return dev_err_probe(dev, PTR_ERR(inst->clk), + "failed to get usb2 phy clk\n"); + inst->rst =3D devm_reset_control_get_exclusive(dev, "usb2_phy_reset"); + if (IS_ERR(inst->rst)) + return dev_err_probe(dev, PTR_ERR(inst->rst), + "failed to get usb2 phy reset\n"); + + phy_provider =3D devm_of_phy_provider_register(dev, google_usb_phy_xlate); + if (IS_ERR(phy_provider)) + return dev_err_probe(dev, PTR_ERR(phy_provider), + "failed to register phy provider\n"); + + pm_runtime_enable(dev); + + sw_desc.fwnode =3D dev_fwnode(dev); + sw_desc.drvdata =3D gphy; + sw_desc.name =3D fwnode_get_name(dev_fwnode(dev)); + sw_desc.set =3D google_usb_set_orientation; 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Mon, 06 Oct 2025 16:22:00 -0700 (PDT) Date: Mon, 6 Oct 2025 23:21:25 +0000 In-Reply-To: <20251006232125.1833979-1-royluo@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251006232125.1833979-1-royluo@google.com> X-Mailer: git-send-email 2.51.0.618.g983fd99d29-goog Message-ID: <20251006232125.1833979-5-royluo@google.com> Subject: [PATCH v1 4/4] dt-bindings: phy: google: Add Google SoC USB PHY From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the USB PHY bindings for Google Tensor SoCs. Signed-off-by: Roy Luo --- .../bindings/phy/google,usb-phy.yaml | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/google,usb-phy.ya= ml diff --git a/Documentation/devicetree/bindings/phy/google,usb-phy.yaml b/Do= cumentation/devicetree/bindings/phy/google,usb-phy.yaml new file mode 100644 index 000000000000..5552696edfff --- /dev/null +++ b/Documentation/devicetree/bindings/phy/google,usb-phy.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025, Google LLC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/google,usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google USB PHY + +maintainers: + - Roy Luo + +description: + Describes the USB PHY block on Google Tensor SoCs. + +properties: + compatible: + items: + - enum: + - google,lga-usb-phy + - const: google,usb-phy + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + items: + - const: usb2_cfg_csr + - const: dp_top_csr + - const: usb_top_cfg_csr + + "#phy-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: usb2_phy_clk + + resets: + maxItems: 1 + + reset-names: + items: + - const: usb2_phy_reset + + power-domains: + maxItems: 1 + + orientation-switch: + type: boolean + description: + Indicates the PHY as a handler of USB Type-C orientation changes + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + usb_phy: usb_phy@c410000 { + compatible =3D "google,lga-usb-phy", "google,usb-phy"; + reg =3D <0 0x0c450014 0 0xc>, + <0 0x0c637000 0 0xa0>, + <0 0x0c45002c 0 0x4>; + reg-names =3D "usb2_cfg_csr", "dp_top_csr", "usb_top_cfg_csr"; + #phy-cells =3D <1>; + clocks =3D <&hsion_usb2_phy_reset_clk>; + clock-names =3D "usb2_phy_clk"; + resets =3D <&hsion_resets_usb2_phy>; + reset-names =3D "usb2_phy_reset"; + power-domains =3D <&hsio_n_usb_pd>; + orientation-switch; + }; + }; +... --=20 2.51.0.618.g983fd99d29-goog