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charset="utf-8" From: Mary Guillemard Currently memory allocated by VM_BIND uAPI can only have a granuality matching PAGE_SIZE (4KiB in common case) To have a better memory management and to allow big (64KiB) and huge (2MiB) pages later in the serie, we are now passing the page shift all around the internals of UVMM. Co-developed-by: Mohamed Ahmed Signed-off-by: Mohamed Ahmed Signed-off-by: Mary Guillemard --- drivers/gpu/drm/nouveau/nouveau_uvmm.c | 55 ++++++++++++++++---------- drivers/gpu/drm/nouveau/nouveau_uvmm.h | 1 + 2 files changed, 35 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_uvmm.c b/drivers/gpu/drm/nouve= au/nouveau_uvmm.c index 79eefdfd08a2..a92c729600d6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_uvmm.c +++ b/drivers/gpu/drm/nouveau/nouveau_uvmm.c @@ -107,34 +107,34 @@ nouveau_uvmm_vmm_sparse_unref(struct nouveau_uvmm *uv= mm, =20 static int nouveau_uvmm_vmm_get(struct nouveau_uvmm *uvmm, - u64 addr, u64 range) + u64 addr, u64 range, u8 page_shift) { struct nvif_vmm *vmm =3D &uvmm->vmm.vmm; =20 - return nvif_vmm_raw_get(vmm, addr, range, PAGE_SHIFT); + return nvif_vmm_raw_get(vmm, addr, range, page_shift); } =20 static int nouveau_uvmm_vmm_put(struct nouveau_uvmm *uvmm, - u64 addr, u64 range) + u64 addr, u64 range, u8 page_shift) { struct nvif_vmm *vmm =3D &uvmm->vmm.vmm; =20 - return nvif_vmm_raw_put(vmm, addr, range, PAGE_SHIFT); + return nvif_vmm_raw_put(vmm, addr, range, page_shift); } =20 static int nouveau_uvmm_vmm_unmap(struct nouveau_uvmm *uvmm, - u64 addr, u64 range, bool sparse) + u64 addr, u64 range, u8 page_shift, bool sparse) { struct nvif_vmm *vmm =3D &uvmm->vmm.vmm; =20 - return nvif_vmm_raw_unmap(vmm, addr, range, PAGE_SHIFT, sparse); + return nvif_vmm_raw_unmap(vmm, addr, range, page_shift, sparse); } =20 static int nouveau_uvmm_vmm_map(struct nouveau_uvmm *uvmm, - u64 addr, u64 range, + u64 addr, u64 range, u8 page_shift, u64 bo_offset, u8 kind, struct nouveau_mem *mem) { @@ -163,7 +163,7 @@ nouveau_uvmm_vmm_map(struct nouveau_uvmm *uvmm, return -ENOSYS; } =20 - return nvif_vmm_raw_map(vmm, addr, range, PAGE_SHIFT, + return nvif_vmm_raw_map(vmm, addr, range, page_shift, &args, argc, &mem->mem, bo_offset); } @@ -182,8 +182,9 @@ nouveau_uvma_vmm_put(struct nouveau_uvma *uvma) { u64 addr =3D uvma->va.va.addr; u64 range =3D uvma->va.va.range; + u8 page_shift =3D uvma->page_shift; =20 - return nouveau_uvmm_vmm_put(to_uvmm(uvma), addr, range); + return nouveau_uvmm_vmm_put(to_uvmm(uvma), addr, range, page_shift); } =20 static int @@ -193,9 +194,11 @@ nouveau_uvma_map(struct nouveau_uvma *uvma, u64 addr =3D uvma->va.va.addr; u64 offset =3D uvma->va.gem.offset; u64 range =3D uvma->va.va.range; + u8 page_shift =3D uvma->page_shift; =20 return nouveau_uvmm_vmm_map(to_uvmm(uvma), addr, range, - offset, uvma->kind, mem); + page_shift, offset, uvma->kind, + mem); } =20 static int @@ -203,12 +206,13 @@ nouveau_uvma_unmap(struct nouveau_uvma *uvma) { u64 addr =3D uvma->va.va.addr; u64 range =3D uvma->va.va.range; + u8 page_shift =3D uvma->page_shift; bool sparse =3D !!uvma->region; =20 if (drm_gpuva_invalidated(&uvma->va)) return 0; =20 - return nouveau_uvmm_vmm_unmap(to_uvmm(uvma), addr, range, sparse); + return nouveau_uvmm_vmm_unmap(to_uvmm(uvma), addr, range, page_shift, spa= rse); } =20 static int @@ -501,7 +505,8 @@ nouveau_uvmm_sm_prepare_unwind(struct nouveau_uvmm *uvm= m, =20 if (vmm_get_range) nouveau_uvmm_vmm_put(uvmm, vmm_get_start, - vmm_get_range); + vmm_get_range, + PAGE_SHIFT); break; } case DRM_GPUVA_OP_REMAP: { @@ -528,6 +533,7 @@ nouveau_uvmm_sm_prepare_unwind(struct nouveau_uvmm *uvm= m, u64 ustart =3D va->va.addr; u64 urange =3D va->va.range; u64 uend =3D ustart + urange; + u8 page_shift =3D uvma_from_va(va)->page_shift; =20 /* Nothing to do for mappings we merge with. */ if (uend =3D=3D vmm_get_start || @@ -538,7 +544,8 @@ nouveau_uvmm_sm_prepare_unwind(struct nouveau_uvmm *uvm= m, u64 vmm_get_range =3D ustart - vmm_get_start; =20 nouveau_uvmm_vmm_put(uvmm, vmm_get_start, - vmm_get_range); + vmm_get_range, + page_shift); } vmm_get_start =3D uend; break; @@ -581,7 +588,8 @@ static int op_map_prepare(struct nouveau_uvmm *uvmm, struct nouveau_uvma **puvma, struct drm_gpuva_op_map *op, - struct uvmm_map_args *args) + struct uvmm_map_args *args, + u8 page_shift) { struct nouveau_uvma *uvma; int ret; @@ -592,6 +600,7 @@ op_map_prepare(struct nouveau_uvmm *uvmm, =20 uvma->region =3D args->region; uvma->kind =3D args->kind; + uvma->page_shift =3D page_shift; =20 drm_gpuva_map(&uvmm->base, &uvma->va, op); =20 @@ -627,13 +636,14 @@ nouveau_uvmm_sm_prepare(struct nouveau_uvmm *uvmm, case DRM_GPUVA_OP_MAP: { u64 vmm_get_range =3D vmm_get_end - vmm_get_start; =20 - ret =3D op_map_prepare(uvmm, &new->map, &op->map, args); + ret =3D op_map_prepare(uvmm, &new->map, &op->map, args, PAGE_SHIFT); if (ret) goto unwind; =20 if (vmm_get_range) { ret =3D nouveau_uvmm_vmm_get(uvmm, vmm_get_start, - vmm_get_range); + vmm_get_range, + new->map->page_shift); if (ret) { op_map_prepare_unwind(new->map); goto unwind; @@ -657,7 +667,7 @@ nouveau_uvmm_sm_prepare(struct nouveau_uvmm *uvmm, =20 if (r->prev) { ret =3D op_map_prepare(uvmm, &new->prev, r->prev, - &remap_args); + &remap_args, uvma_from_va(va)->page_shift); if (ret) goto unwind; =20 @@ -667,7 +677,7 @@ nouveau_uvmm_sm_prepare(struct nouveau_uvmm *uvmm, =20 if (r->next) { ret =3D op_map_prepare(uvmm, &new->next, r->next, - &remap_args); + &remap_args, uvma_from_va(va)->page_shift); if (ret) { if (r->prev) op_map_prepare_unwind(new->prev); @@ -689,6 +699,7 @@ nouveau_uvmm_sm_prepare(struct nouveau_uvmm *uvmm, u64 ustart =3D va->va.addr; u64 urange =3D va->va.range; u64 uend =3D ustart + urange; + u8 page_shift =3D uvma_from_va(va)->page_shift; =20 op_unmap_prepare(u); =20 @@ -704,7 +715,7 @@ nouveau_uvmm_sm_prepare(struct nouveau_uvmm *uvmm, u64 vmm_get_range =3D ustart - vmm_get_start; =20 ret =3D nouveau_uvmm_vmm_get(uvmm, vmm_get_start, - vmm_get_range); + vmm_get_range, page_shift); if (ret) { op_unmap_prepare_unwind(va); goto unwind; @@ -799,10 +810,11 @@ op_unmap_range(struct drm_gpuva_op_unmap *u, u64 addr, u64 range) { struct nouveau_uvma *uvma =3D uvma_from_va(u->va); + u8 page_shift =3D uvma->page_shift; bool sparse =3D !!uvma->region; =20 if (!drm_gpuva_invalidated(u->va)) - nouveau_uvmm_vmm_unmap(to_uvmm(uvma), addr, range, sparse); + nouveau_uvmm_vmm_unmap(to_uvmm(uvma), addr, range, page_shift, sparse); } =20 static void @@ -882,6 +894,7 @@ nouveau_uvmm_sm_cleanup(struct nouveau_uvmm *uvmm, struct drm_gpuva_op_map *n =3D r->next; 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charset="utf-8" From: Mary Guillemard Now that everything in UVMM knows about the variable page shift, we can select larger values. The proposed approach rely on nouveau_bo::page unless it would cause alignment issues (in which case we fall back to searching an appropriate shift) Co-developed-by: Mohamed Ahmed Signed-off-by: Mohamed Ahmed Signed-off-by: Mary Guillemard --- drivers/gpu/drm/nouveau/nouveau_uvmm.c | 55 +++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_uvmm.c b/drivers/gpu/drm/nouve= au/nouveau_uvmm.c index a92c729600d6..c336a121e320 100644 --- a/drivers/gpu/drm/nouveau/nouveau_uvmm.c +++ b/drivers/gpu/drm/nouveau/nouveau_uvmm.c @@ -454,6 +454,56 @@ op_unmap_prepare_unwind(struct drm_gpuva *va) drm_gpuva_insert(va->vm, va); } =20 +static bool +op_map_aligned_to_page_shift(const struct drm_gpuva_op_map *op, u8 page_sh= ift) +{ + u64 page_size =3D 1ULL << page_shift; + + return op->va.addr % page_size =3D=3D 0 && op->va.range % page_size =3D= =3D 0 && + op->gem.offset % page_size =3D=3D 0; +} + +static u8 +select_page_shift(struct nouveau_uvmm *uvmm, struct drm_gpuva_op_map *op) +{ + struct nouveau_bo *nvbo =3D nouveau_gem_object(op->gem.obj); + + if (nvbo) { + /* If the BO preferred page shift already fits, use it. */ + if (op_map_aligned_to_page_shift(op, nvbo->page)) + return nvbo->page; + + struct nouveau_mem *mem =3D nouveau_mem(nvbo->bo.resource); + struct nvif_vmm *vmm =3D &uvmm->vmm.vmm; + int i; + + /* Otherwise let's find a granuality that will fit. */ + for (i =3D 0; i < vmm->page_nr; i++) { + /* Ignore anything that is bigger or identical to the BO preference. */ + if (vmm->page[i].shift >=3D nvbo->page) + continue; + + /* Skip incompatible domains. */ + if ((mem->mem.type & NVIF_MEM_VRAM) && !vmm->page[i].vram) + continue; + if ((mem->mem.type & NVIF_MEM_HOST) && + (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT)) + continue; + + /* If it fits, return the proposed shift. */ + if (op_map_aligned_to_page_shift(op, vmm->page[i].shift)) + return vmm->page[i].shift; + } + + /* If we get here then nothing can reconcile the requirements. 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Mon, 06 Oct 2025 12:14:18 -0700 (PDT) Received: from fedora ([154.182.208.105]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4256866060fsm16646435f8f.14.2025.10.06.12.14.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Oct 2025 12:14:18 -0700 (PDT) From: Mohamed Ahmed To: linux-kernel@vger.kernel.org Cc: dri-devel@lists.freedesktop.org, Mary Guillemard , Faith Ekstrand , Ben Skeggs , Lyude Paul , Danilo Krummrich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , nouveau@lists.freedesktop.org Subject: [PATCH 3/5] drm/nouveau/mmu/gp100: Remove unused/broken support for compression Date: Mon, 6 Oct 2025 22:13:26 +0300 Message-ID: <20251006191329.277485-4-mohamedahmedegypt2001@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251006191329.277485-1-mohamedahmedegypt2001@gmail.com> References: <20251006191329.277485-1-mohamedahmedegypt2001@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ben Skeggs From GP100 onwards it's not possible to initialise comptag RAM without PMU firmware, which nouveau has no support for. As such, this code is essentially a no-op and will always revert to the equivalent non-compressed kind due to comptag allocation failure. It's also broken for the needs of VM_BIND/Vulkan. Remove the code entirely to make way for supporting compression on GPUs that support GSM-RM. Signed-off-by: Ben Skeggs --- .../drm/nouveau/nvkm/subdev/mmu/vmmgp100.c | 39 ++----------------- .../drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c | 4 +- 2 files changed, 6 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c b/drivers/g= pu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c index 851fd847a2a9..ecff1096a1bb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c @@ -21,9 +21,7 @@ */ #include "vmm.h" =20 -#include #include -#include #include #include =20 @@ -117,8 +115,6 @@ gp100_vmm_pgt_pte(struct nvkm_vmm *vmm, struct nvkm_mmu= _pt *pt, { u64 data =3D (addr >> 4) | map->type; =20 - map->type +=3D ptes * map->ctag; - while (ptes--) { VMM_WO064(pt, vmm, ptei++ * 8, data); data +=3D map->next; @@ -142,7 +138,6 @@ gp100_vmm_pgt_dma(struct nvkm_vmm *vmm, struct nvkm_mmu= _pt *pt, while (ptes--) { const u64 data =3D (*map->dma++ >> 4) | map->type; VMM_WO064(pt, vmm, ptei++ * 8, data); - map->type +=3D map->ctag; } nvkm_done(pt->memory); return; @@ -200,8 +195,6 @@ gp100_vmm_pd0_pte(struct nvkm_vmm *vmm, struct nvkm_mmu= _pt *pt, { u64 data =3D (addr >> 4) | map->type; =20 - map->type +=3D ptes * map->ctag; - while (ptes--) { VMM_WO128(pt, vmm, ptei++ * 0x10, data, 0ULL); data +=3D map->next; @@ -411,8 +404,6 @@ gp100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 a= rgc, struct gp100_vmm_map_vn vn; struct gp100_vmm_map_v0 v0; } *args =3D argv; - struct nvkm_device *device =3D vmm->mmu->subdev.device; - struct nvkm_memory *memory =3D map->memory; u8 kind, kind_inv, priv, ro, vol; int kindn, aper, ret =3D -ENOSYS; const u8 *kindm; @@ -450,30 +441,8 @@ gp100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 = argc, } =20 if (kindm[kind] !=3D kind) { - u64 tags =3D nvkm_memory_size(memory) >> 16; - if (aper !=3D 0 || !(page->type & NVKM_VMM_PAGE_COMP)) { - VMM_DEBUG(vmm, "comp %d %02x", aper, page->type); - return -EINVAL; - } - - if (!map->no_comp) { - ret =3D nvkm_memory_tags_get(memory, device, tags, - nvkm_ltc_tags_clear, - &map->tags); - if (ret) { - VMM_DEBUG(vmm, "comp %d", ret); - return ret; - } - } - - if (!map->no_comp && map->tags->mn) { - tags =3D map->tags->mn->offset + (map->offset >> 16); - map->ctag |=3D ((1ULL << page->shift) >> 16) << 36; - map->type |=3D tags << 36; - map->next |=3D map->ctag; - } else { - kind =3D kindm[kind]; - } + /* Revert to non-compressed kind. */ + kind =3D kindm[kind]; } =20 map->type |=3D BIT(0); @@ -592,8 +561,8 @@ gp100_vmm =3D { { 47, &gp100_vmm_desc_16[4], NVKM_VMM_PAGE_Sxxx }, { 38, &gp100_vmm_desc_16[3], NVKM_VMM_PAGE_Sxxx }, { 29, &gp100_vmm_desc_16[2], NVKM_VMM_PAGE_Sxxx }, - { 21, &gp100_vmm_desc_16[1], NVKM_VMM_PAGE_SVxC }, - { 16, &gp100_vmm_desc_16[0], NVKM_VMM_PAGE_SVxC }, + { 21, &gp100_vmm_desc_16[1], NVKM_VMM_PAGE_SVxx }, + { 16, &gp100_vmm_desc_16[0], NVKM_VMM_PAGE_SVxx }, { 12, &gp100_vmm_desc_12[0], NVKM_VMM_PAGE_SVHx }, {} } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c b/drivers/g= pu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c index e081239afe58..5791d134962b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.c @@ -34,8 +34,8 @@ gp10b_vmm =3D { { 47, &gp100_vmm_desc_16[4], NVKM_VMM_PAGE_Sxxx }, { 38, &gp100_vmm_desc_16[3], NVKM_VMM_PAGE_Sxxx }, { 29, &gp100_vmm_desc_16[2], NVKM_VMM_PAGE_Sxxx }, - { 21, &gp100_vmm_desc_16[1], NVKM_VMM_PAGE_SxHC }, - { 16, &gp100_vmm_desc_16[0], NVKM_VMM_PAGE_SxHC }, + { 21, &gp100_vmm_desc_16[1], NVKM_VMM_PAGE_SxHx }, + { 16, &gp100_vmm_desc_16[0], NVKM_VMM_PAGE_SxHx }, { 12, &gp100_vmm_desc_12[0], NVKM_VMM_PAGE_SxHx }, {} } --=20 2.51.0 From nobody Sun Dec 7 14:31:41 2025 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D24A32DF121 for ; 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charset="utf-8" From: Ben Skeggs Allow compressed PTE kinds to be written into PTEs when GSP-RM is present, rather than reverting to their non-compressed versions. Signed-off-by: Ben Skeggs --- .../drm/nouveau/nvkm/subdev/mmu/vmmgp100.c | 46 ++++++++++++++++++- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c b/drivers/g= pu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c index ecff1096a1bb..ed15a4475181 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c @@ -109,12 +109,34 @@ gp100_vmm_pgt_pfn(struct nvkm_vmm *vmm, struct nvkm_m= mu_pt *pt, nvkm_done(pt->memory); } =20 +static inline u64 +gp100_vmm_comptag_nr(u64 size) +{ + return size >> 16; /* One comptag per 64KiB VRAM. */ +} + +static inline u64 +gp100_vmm_pte_comptagline_base(u64 addr) +{ + /* RM allocates enough comptags for all of VRAM, so use a 1:1 mapping. */ + return (1 + gp100_vmm_comptag_nr(addr)) << 36; /* NV_MMU_VER2_PTE_COMPTAG= LINE */ +} + +static inline u64 +gp100_vmm_pte_comptagline_incr(u32 page_size) +{ + return gp100_vmm_comptag_nr(page_size) << 36; /* NV_MMU_VER2_PTE_COMPTAGL= INE */ +} + static inline void gp100_vmm_pgt_pte(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes, struct nvkm_vmm_map *map, u64 addr) { u64 data =3D (addr >> 4) | map->type; =20 + if (map->ctag) + data |=3D gp100_vmm_pte_comptagline_base(addr); + while (ptes--) { VMM_WO064(pt, vmm, ptei++ * 8, data); data +=3D map->next; @@ -195,6 +217,9 @@ gp100_vmm_pd0_pte(struct nvkm_vmm *vmm, struct nvkm_mmu= _pt *pt, { u64 data =3D (addr >> 4) | map->type; =20 + if (map->ctag) + data |=3D gp100_vmm_pte_comptagline_base(addr); + while (ptes--) { VMM_WO128(pt, vmm, ptei++ * 0x10, data, 0ULL); data +=3D map->next; @@ -440,9 +465,26 @@ gp100_vmm_valid(struct nvkm_vmm *vmm, void *argv, u32 = argc, return -EINVAL; } =20 + /* Handle compression. */ if (kindm[kind] !=3D kind) { - /* Revert to non-compressed kind. */ - kind =3D kindm[kind]; + struct nvkm_device *device =3D vmm->mmu->subdev.device; + + /* Compression is only supported when using GSP-RM, as + * PMU firmware is required in order to initialise the + * compbit backing store. + */ + if (nvkm_gsp_rm(device->gsp)) { + /* Turing GPUs require PTE_COMPTAGLINE to be filled, + * in addition to specifying a compressed kind. + */ + if (device->card_type < GA100) { + map->ctag =3D gp100_vmm_pte_comptagline_incr(1 << map->page->shift); + map->next |=3D map->ctag; + } + } else { + /* Revert to non-compressed kind. */ + kind =3D kindm[kind]; + } } =20 map->type |=3D BIT(0); --=20 2.51.0 From nobody Sun Dec 7 14:31:41 2025 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97DB42DF12E for ; Mon, 6 Oct 2025 19:14:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759778071; cv=none; b=MQoP42susQSF2V9NH+lEeGE9Kkm9BDzTnhbxX2yETLkIOv7rAnMPVBvCMtW0PjWynoxy26uzOM+aJu1UNBwsHROGIVMmvYXqwYmhSBi2Yri40I4gS35jkOw77VgIReK7kM0TsMhiplTkg45ypna/0PIu75xDv10m+na6ubOgRuI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759778071; c=relaxed/simple; bh=drAafvzz1pDZDG8f4ieZYxlF0QAwe5Jk7b+PINMyv8A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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charset="utf-8" This is so that NVK can enable compression for kernels that support it and avoid cases where an older kernel would MMU fault when a newer mesa would try to use compression. Signed-off-by: Mohamed Ahmed --- drivers/gpu/drm/nouveau/nouveau_drv.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouvea= u/nouveau_drv.h index 55abc510067b..9983dc57efc5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -10,7 +10,7 @@ =20 #define DRIVER_MAJOR 1 #define DRIVER_MINOR 4 -#define DRIVER_PATCHLEVEL 0 +#define DRIVER_PATCHLEVEL 1 =20 /* * 1.1.1: @@ -35,6 +35,8 @@ * programs that get directly linked with NVKM. * 1.3.1: * - implemented limited ABI16/NVIF interop + * 1.4.1: + * - add variable page sizes and compression for Turing+ */ =20 #include --=20 2.51.0