From nobody Mon Dec 8 01:26:12 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6AA22D8DB9; Mon, 6 Oct 2025 15:58:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759766339; cv=none; b=pPU57TlYS5RRRc2CN//7FrACiT/Z2nuzoJiBQu5KQJkKDOTxZ6lUWgjqj6zr1VON7ta2a+WKtnmrbyx1sDvkEnir1MCiqoZroAsXlHHRA65owW8PFjNpJRUFFJg0ztfAqGTO/DtU39qqA3U4ZeAlorGPvzV6bZmHmtai25vYvCc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759766339; c=relaxed/simple; bh=tICIjNuKpUmKFK93meEYeXqkDKxdYHSUFm3JlHZZWuA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PbdlY0RRaGLsBKJbBmqNS+F0azNB1884nnMbjt3Q++OuYsKZ2oHKkhwcAIKGibnMooeGG51QN0PdqKvn9sizpHub9gzoiZsIMhP5yTzV/3z/Vx/hEolOsxvsc6G6nml51mW52HnUrl8hjxDo6EuRi2ldHZu5vTCdq+DkrS6TWIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MG3cTR1V; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MG3cTR1V" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1759766337; x=1791302337; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tICIjNuKpUmKFK93meEYeXqkDKxdYHSUFm3JlHZZWuA=; b=MG3cTR1Vd9UDT6v/PQ8vCLK05AyUsRf/dAFrWIuxlk2clsExYBPNjWTq +e/SOiY9f0wsmKjM98Gg7qlI6mp41ngytnrb8cYjgGr/7gGwaVtEpnLV6 xRTWpFVUnWCRgw1+vi2Xbky4cLxTUT06DNd2yXApsb3w8uvaJEEWrI7VB hfszO/EArrGNYVWJXmyw0dSPepcs0cuznsRhztXYe/I8jBu4Hfq3+Hokc 8/aoVfMJtmcdOUlNM86lpwZIOOF63e9MSVFLDZmTOj4MXmagrdPtsJLUn 8jxiI94SREUAi3Yp5oGiW9GJyY/FXXDDHxgiIiYaJyaS0v0MhuIpiNn/q A==; X-CSE-ConnectionGUID: t2NhwkHtSFetpd4BeMHcEg== X-CSE-MsgGUID: Cs2LJbkiSKaWzJQc/1uYgw== X-IronPort-AV: E=McAfee;i="6800,10657,11574"; a="61150562" X-IronPort-AV: E=Sophos;i="6.18,320,1751266800"; d="scan'208";a="61150562" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2025 08:58:54 -0700 X-CSE-ConnectionGUID: Bl2oNqNPQgmC5nzGI+gq6Q== X-CSE-MsgGUID: TZbgicnSSvm7lvsVGzj25g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,320,1751266800"; d="scan'208";a="185189577" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO fdefranc-mobl3.intel.com) ([10.245.245.98]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2025 08:58:49 -0700 From: "Fabio M. De Francesco" To: linux-cxl@vger.kernel.org Cc: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Gregory Price , Robert Richter , Cheatham Benjamin , "Fabio M. De Francesco" Subject: [PATCH 1/4 v5] cxl/core: Change match_*_by_range() signatures Date: Mon, 6 Oct 2025 17:58:04 +0200 Message-ID: <20251006155836.791418-2-fabio.m.de.francesco@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251006155836.791418-1-fabio.m.de.francesco@linux.intel.com> References: <20251006155836.791418-1-fabio.m.de.francesco@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace struct range parameter with struct cxl_endpoint_decoder of which range is a member in the match_*_by_range() functions and rename them according to their semantics. This is in preparation for expanding these helpers to perform arch specific Root Decoders and Region matchings with cxl_endpoint_decoder(s). Cc: Alison Schofield Cc: Dan Williams Cc: Dave Jiang Cc: Ira Weiny Reviewed-by: Jonathan Cameron Signed-off-by: Fabio M. De Francesco Reviewed-by: Dave Jiang Reviewed-by: Gregory Price --- drivers/cxl/core/region.c | 62 ++++++++++++++++++++++----------------- 1 file changed, 35 insertions(+), 27 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index e14c1d305b22..43a854036202 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1766,27 +1766,29 @@ static int cmp_interleave_pos(const void *a, const = void *b) return cxled_a->pos - cxled_b->pos; } =20 -static int match_switch_decoder_by_range(struct device *dev, - const void *data) +static int match_cxlsd_to_cxled_by_range(struct device *dev, const void *d= ata) { + const struct cxl_endpoint_decoder *cxled =3D data; struct cxl_switch_decoder *cxlsd; - const struct range *r1, *r2 =3D data; - + const struct range *r1, *r2; =20 if (!is_switch_decoder(dev)) return 0; =20 cxlsd =3D to_cxl_switch_decoder(dev); r1 =3D &cxlsd->cxld.hpa_range; + r2 =3D &cxled->cxld.hpa_range; =20 if (is_root_decoder(dev)) return range_contains(r1, r2); return (r1->start =3D=3D r2->start && r1->end =3D=3D r2->end); } =20 -static int find_pos_and_ways(struct cxl_port *port, struct range *range, - int *pos, int *ways) +static int find_pos_and_ways(struct cxl_port *port, + struct cxl_endpoint_decoder *cxled, int *pos, + int *ways) { + struct range *range =3D &cxled->cxld.hpa_range; struct cxl_switch_decoder *cxlsd; struct cxl_port *parent; struct device *dev; @@ -1796,8 +1798,8 @@ static int find_pos_and_ways(struct cxl_port *port, s= truct range *range, if (!parent) return rc; =20 - dev =3D device_find_child(&parent->dev, range, - match_switch_decoder_by_range); + dev =3D device_find_child(&parent->dev, cxled, + match_cxlsd_to_cxled_by_range); if (!dev) { dev_err(port->uport_dev, "failed to find decoder mapping %#llx-%#llx\n", @@ -1883,7 +1885,7 @@ static int cxl_calc_interleave_pos(struct cxl_endpoin= t_decoder *cxled) if (is_cxl_root(iter)) break; =20 - rc =3D find_pos_and_ways(iter, range, &parent_pos, &parent_ways); + rc =3D find_pos_and_ways(iter, cxled, &parent_pos, &parent_ways); if (rc) return rc; =20 @@ -3342,24 +3344,30 @@ static int devm_cxl_add_dax_region(struct cxl_regio= n *cxlr) return rc; } =20 -static int match_decoder_by_range(struct device *dev, const void *data) +static int match_cxlrd_to_cxled_by_range(struct device *dev, const void *d= ata) { - const struct range *r1, *r2 =3D data; - struct cxl_decoder *cxld; + const struct cxl_endpoint_decoder *cxled =3D data; + struct cxl_root_decoder *cxlrd; + const struct range *r1, *r2; =20 - if (!is_switch_decoder(dev)) + if (!is_root_decoder(dev)) return 0; =20 - cxld =3D to_cxl_decoder(dev); - r1 =3D &cxld->hpa_range; + cxlrd =3D to_cxl_root_decoder(dev); + r1 =3D &cxlrd->cxlsd.cxld.hpa_range; + r2 =3D &cxled->cxld.hpa_range; + return range_contains(r1, r2); } =20 static struct cxl_decoder * -cxl_port_find_switch_decoder(struct cxl_port *port, struct range *hpa) +cxl_port_find_root_decoder(struct cxl_port *port, + struct cxl_endpoint_decoder *cxled) { - struct device *cxld_dev =3D device_find_child(&port->dev, hpa, - match_decoder_by_range); + struct device *cxld_dev; + + cxld_dev =3D device_find_child(&port->dev, cxled, + match_cxlrd_to_cxled_by_range); =20 return cxld_dev ? to_cxl_decoder(cxld_dev) : NULL; } @@ -3371,9 +3379,8 @@ cxl_find_root_decoder(struct cxl_endpoint_decoder *cx= led) struct cxl_port *port =3D cxled_to_port(cxled); struct cxl_root *cxl_root __free(put_cxl_root) =3D find_cxl_root(port); struct cxl_decoder *root, *cxld =3D &cxled->cxld; - struct range *hpa =3D &cxld->hpa_range; =20 - root =3D cxl_port_find_switch_decoder(&cxl_root->port, hpa); + root =3D cxl_port_find_root_decoder(&cxl_root->port, cxled); if (!root) { dev_err(cxlmd->dev.parent, "%s:%s no CXL window for range %#llx:%#llx\n", @@ -3385,11 +3392,12 @@ cxl_find_root_decoder(struct cxl_endpoint_decoder *= cxled) return to_cxl_root_decoder(&root->dev); } =20 -static int match_region_by_range(struct device *dev, const void *data) +static int match_region_to_cxled_by_range(struct device *dev, const void *= data) { + const struct cxl_endpoint_decoder *cxled =3D data; + const struct range *r =3D &cxled->cxld.hpa_range; struct cxl_region_params *p; struct cxl_region *cxlr; - const struct range *r =3D data; =20 if (!is_cxl_region(dev)) return 0; @@ -3547,12 +3555,13 @@ static struct cxl_region *construct_region(struct c= xl_root_decoder *cxlrd, } =20 static struct cxl_region * -cxl_find_region_by_range(struct cxl_root_decoder *cxlrd, struct range *hpa) +cxl_find_region_by_range(struct cxl_root_decoder *cxlrd, + struct cxl_endpoint_decoder *cxled) { struct device *region_dev; =20 - region_dev =3D device_find_child(&cxlrd->cxlsd.cxld.dev, hpa, - match_region_by_range); + region_dev =3D device_find_child(&cxlrd->cxlsd.cxld.dev, cxled, + match_region_to_cxled_by_range); if (!region_dev) return NULL; =20 @@ -3561,7 +3570,6 @@ cxl_find_region_by_range(struct cxl_root_decoder *cxl= rd, struct range *hpa) =20 int cxl_add_to_region(struct cxl_endpoint_decoder *cxled) { - struct range *hpa =3D &cxled->cxld.hpa_range; struct cxl_region_params *p; bool attach =3D false; int rc; @@ -3577,7 +3585,7 @@ int cxl_add_to_region(struct cxl_endpoint_decoder *cx= led) */ mutex_lock(&cxlrd->range_lock); struct cxl_region *cxlr __free(put_cxl_region) =3D - cxl_find_region_by_range(cxlrd, hpa); + cxl_find_region_by_range(cxlrd, cxled); if (!cxlr) cxlr =3D construct_region(cxlrd, cxled); mutex_unlock(&cxlrd->range_lock); --=20 2.50.1 From nobody Mon Dec 8 01:26:12 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 579272D9494; Mon, 6 Oct 2025 15:58:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759766341; cv=none; b=gJRrHFNWJvQq4HU9wnil+Y4J6wFrXtZJPlA1A6azDlKRjAO/ZfyhmuDZk4EVV2T3xvC5+ofMUmLqWRTf/Cx17dBt/3VlOSBAuG3eF4wRe+2QfWpCxwrqFvfIukJekXRlA+1W/IpdKB9cqTzCH/WLhikr7aoV8fYeh4UNGjFRx94= ARC-Message-Signature: i=1; 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d="scan'208";a="185189594" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO fdefranc-mobl3.intel.com) ([10.245.245.98]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2025 08:58:53 -0700 From: "Fabio M. De Francesco" To: linux-cxl@vger.kernel.org Cc: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Gregory Price , Robert Richter , Cheatham Benjamin , "Fabio M. De Francesco" Subject: [PATCH 2/4 v5] cxl/core: Add helpers to detect Low Memory Holes on x86 Date: Mon, 6 Oct 2025 17:58:05 +0200 Message-ID: <20251006155836.791418-3-fabio.m.de.francesco@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251006155836.791418-1-fabio.m.de.francesco@linux.intel.com> References: <20251006155836.791418-1-fabio.m.de.francesco@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On a x86 platform with a low memory hole (LHM), the BIOS may publish CFMWS that describes a system physical address (SPA) range that typically is only a subset of the corresponding CXL intermediate switch and endpoint decoder's host physical address (HPA) ranges. The CFMWS range never intersects the LHM and so the driver instantiates a root decoder whose HPA range size doesn't fully contain the matching switch and endpoint decoders' HPA ranges.[1] To construct regions and attach decoders, the driver needs to match root decoders and regions with endpoint decoders. The process fails and returns errors because the driver is not designed to deal with SPA ranges which are smaller than the corresponding hardware decoders HPA ranges. Introduce two functions that indirectly detect the presence of x86 LMH and allow the matching between a root decoder or an already constructed region with a corresponding intermediate switch or endpoint decoder to enable the construction of a region and the subsequent attachment of the same decoders to that region. These functions return true when SPA/HPA misalignments due to LMH's are detected under specific conditions: - Both the SPA and HPA ranges must start at LMH_CFMWS_RANGE_START (i.e., 0x0 on x86 with LMH's). - The SPA range's size is less than HPA's. - The SPA range's size is less than 4G. - The HPA range's size is aligned to the NIW * 256M rule. Also introduce a function that adjusts the range end of a region to be constructed and the DPA range's end of the endpoint decoders that will be later attached to that region. [1] commit 7a81173f3 ("cxl: Documentation/driver-api/cxl: Describe the x86 = Low Memory Hole solution") Cc: Alison Schofield Cc: Dan Williams Cc: Dave Jiang Cc: Ira Weiny Signed-off-by: Fabio M. De Francesco Reviewed-by: Gregory Price --- drivers/cxl/Kconfig | 4 ++ drivers/cxl/core/Makefile | 1 + drivers/cxl/core/platform_quirks.c | 99 ++++++++++++++++++++++++++++++ drivers/cxl/core/platform_quirks.h | 33 ++++++++++ 4 files changed, 137 insertions(+) create mode 100644 drivers/cxl/core/platform_quirks.c create mode 100644 drivers/cxl/core/platform_quirks.h diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 48b7314afdb8..03c0583bc9a3 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -211,6 +211,10 @@ config CXL_REGION =20 If unsure say 'y' =20 +config CXL_PLATFORM_QUIRKS + def_bool y + depends on CXL_REGION + config CXL_REGION_INVALIDATION_TEST bool "CXL: Region Cache Management Bypass (TEST)" depends on CXL_REGION diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index 5ad8fef210b5..1684e46b8709 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -17,6 +17,7 @@ cxl_core-y +=3D cdat.o cxl_core-y +=3D ras.o cxl_core-$(CONFIG_TRACING) +=3D trace.o cxl_core-$(CONFIG_CXL_REGION) +=3D region.o +cxl_core-$(CONFIG_CXL_PLATFORM_QUIRKS) +=3D platform_quirks.o cxl_core-$(CONFIG_CXL_MCE) +=3D mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D edac.o diff --git a/drivers/cxl/core/platform_quirks.c b/drivers/cxl/core/platform= _quirks.c new file mode 100644 index 000000000000..7e76e392b1ae --- /dev/null +++ b/drivers/cxl/core/platform_quirks.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include "platform_quirks.h" +#include "cxlmem.h" +#include "core.h" + +/* Start of CFMWS range that end before x86 Low Memory Holes */ +#define LMH_CFMWS_RANGE_START 0x0ULL + +/** + * platform_cxlrd_matches_cxled() - Platform quirk to match CXL Root and + * Endpoint Decoders. It allows matching on platforms with LMH's. + * @cxlrd: The Root Decoder against which @cxled is tested for matching. + * @cxled: The Endpoint Decoder to be tested for matching @cxlrd. + * + * platform_cxlrd_matches_cxled() is typically called from the + * match_*_by_range() functions in region.c. It checks if an endpoint deco= der + * matches a given root decoder and returns true to allow the driver to su= cceed + * in the construction of regions where it would otherwise fail for the pr= esence + * of a Low Memory Hole (see Documentation/driver-api/cxl/conventions.rst). + * + * In x86 platforms with LMH's, the CFMWS ranges never intersect the LMH, = the + * endpoint decoder's HPA range size is always guaranteed aligned to NIW*2= 56MB + * and also typically larger than the matching root decoder's, and the root + * decoder's range end is at an address that is necessarily less than SZ_4G + * (i.e., the Hole is in Low Memory - this function doesn't deal with other + * kinds of holes). + * + * Return: true if an endpoint matches a root decoder, else false. + */ +bool platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) +{ + const struct range *rd_r, *sd_r; + int align; + + rd_r =3D &cxlrd->cxlsd.cxld.hpa_range; + sd_r =3D &cxled->cxld.hpa_range; + align =3D cxled->cxld.interleave_ways * SZ_256M; + + if (rd_r->start =3D=3D LMH_CFMWS_RANGE_START && + rd_r->start =3D=3D sd_r->start && rd_r->end < sd_r->end && + rd_r->end < (LMH_CFMWS_RANGE_START + SZ_4G) && + IS_ALIGNED(range_len(sd_r), align)) + return true; + + return false; +} + +/** + * platform_region_matches_cxld() - Platform quirk to match a CXL Region a= nd a + * Switch or Endpoint Decoder. It allows matching on platforms with LMH's. + * @p: Region Params against which @cxled is matched. + * @cxld: Switch or Endpoint Decoder to be tested for matching @p. + * + * Similar to platform_cxlrd_matches_cxled(), it matches regions and + * decoders on platforms with LMH's. + * + * Return: true if a Decoder matches a Region, else false. + */ +bool platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld) +{ + const struct range *r =3D &cxld->hpa_range; + const struct resource *res =3D p->res; + int align =3D cxld->interleave_ways * SZ_256M; + + if (res->start =3D=3D LMH_CFMWS_RANGE_START && res->start =3D=3D r->start= && + res->end < r->end && res->end < (LMH_CFMWS_RANGE_START + SZ_4G) && + IS_ALIGNED(range_len(r), align)) + return true; + + return false; +} + +void platform_res_adjust(struct resource *res, + struct cxl_endpoint_decoder *cxled, + const struct cxl_root_decoder *cxlrd) +{ + if (!platform_cxlrd_matches_cxled(cxlrd, cxled)) + return; + + guard(rwsem_write)(&cxl_rwsem.dpa); + dev_dbg(cxled_to_memdev(cxled)->dev.parent, + "Low Memory Hole detected. Resources were (%s: %pr, %pr)\n", + dev_name(&cxled->cxld.dev), res, cxled->dpa_res); + if (res) { + /* Trim region resource overlap with LMH */ + res->end =3D cxlrd->res->end; + } + /* Match endpoint decoder's DPA resource to root decoder's */ + cxled->dpa_res->end =3D + cxled->dpa_res->start + + resource_size(cxlrd->res) / cxled->cxld.interleave_ways - 1; + dev_info(cxled_to_memdev(cxled)->dev.parent, + "Resources have been adjusted for LMH (%s: %pr, %pr)\n", + dev_name(&cxled->cxld.dev), res, cxled->dpa_res); +} diff --git a/drivers/cxl/core/platform_quirks.h b/drivers/cxl/core/platform= _quirks.h new file mode 100644 index 000000000000..a15592b4e90e --- /dev/null +++ b/drivers/cxl/core/platform_quirks.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "cxl.h" + +#ifdef CONFIG_CXL_PLATFORM_QUIRKS +bool platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled); +bool platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld); +void platform_res_adjust(struct resource *res, + struct cxl_endpoint_decoder *cxled, + const struct cxl_root_decoder *cxlrd); +#else +static inline bool +platform_root_decoder_contains(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) +{ + return false; +} + +static inline bool +platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld) +{ + return false; +} + +inline void platform_res_adjust(struct resource *res, + struct cxl_endpoint_decoder *cxled, + const struct cxl_root_decoder *cxlrd) +{ +} +#endif /* CONFIG_CXL_PLATFORM_QUIRKS */ --=20 2.50.1 From nobody Mon Dec 8 01:26:12 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2FD92D9494; Mon, 6 Oct 2025 15:59:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759766349; cv=none; b=Q+KHvnGgIXyDJbYDsXRCum5cqcQphfiwMEp5cX3z0VDLXyeczemp2/xlqtt03wdiR7/FnQEL+yabAsmlQflQddxVyTgzl08Tng0xha/LiQ8hHrdeWsUAMzSSOzhVWrn6pfrjrb99Nao2Rg9diUR/orD8otfesH1295y7O2wdSZE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759766349; c=relaxed/simple; bh=yBUM9OFJir9sKXcqYDtMwtTiT7jrTjmUM4oGbKvhxH8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e3QL744jhh/vVm+mwuLwSVtUuyLYmzJvoy0hh8QXPMd2+sMwCJnV8LHk17S47Ra6TSvKz1BzpxvIBap64dKWqf7h/WQsbkeM1xvfxsPqh3lpOTJyqdHhqn67UPRfLQEeM1NUKfsDAbrTS1nNqfRq/sANgxGxli3SjkxWit0/svA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HYHHvwPk; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HYHHvwPk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1759766348; x=1791302348; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yBUM9OFJir9sKXcqYDtMwtTiT7jrTjmUM4oGbKvhxH8=; b=HYHHvwPkyKloOc+kiaZdt34alpzCgDUqvNSHhWioblUss+QT4+bfCT0z J620Svc7/X5WskPodxDYhfhFn7ksMe4Z672EifDixF2NyQfL2QnPSdtB5 d1MS9Wdm7ykWtRAQEPBv83Kh9j7KdC1mjn5zAkEhWlOuKLbtDFR0ydFFn LcdcPKlVZI9Zd9hexbPRq1KFEFJraN2haj1t6IubTRBzfGDrA8CjJfhNW konBqsZM66O2meQY4BOXhL0JaDHRksmFEMUfqhv4jqzH7gUL3R6l9BNxe qZzkkzcUTyJHpyOEMh3YjxsCqNSEkiKQMYQoVFoBHnMIpiriYF5Zm9ED5 w==; X-CSE-ConnectionGUID: YmS/laQsTKCrljiuGZfZjg== X-CSE-MsgGUID: /sxzGT4xT/qjfHJVsrqemA== X-IronPort-AV: E=McAfee;i="6800,10657,11574"; a="61150589" X-IronPort-AV: E=Sophos;i="6.18,320,1751266800"; d="scan'208";a="61150589" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2025 08:59:03 -0700 X-CSE-ConnectionGUID: 7CLoz8tYSXSV1RsVmN4n2A== X-CSE-MsgGUID: ckdc9OYuTV26PmTZErmryw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,320,1751266800"; d="scan'208";a="185189616" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO fdefranc-mobl3.intel.com) ([10.245.245.98]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2025 08:58:58 -0700 From: "Fabio M. De Francesco" To: linux-cxl@vger.kernel.org Cc: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Gregory Price , Robert Richter , Cheatham Benjamin , "Fabio M. De Francesco" Subject: [PATCH 3/4 v5] cxl/core: Enable Region creation on x86 with LMH Date: Mon, 6 Oct 2025 17:58:06 +0200 Message-ID: <20251006155836.791418-4-fabio.m.de.francesco@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251006155836.791418-1-fabio.m.de.francesco@linux.intel.com> References: <20251006155836.791418-1-fabio.m.de.francesco@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CXL Fixed Memory Window Structure (CFMWS) describes zero or more Host Physical Address (HPA) windows that are associated with each CXL Host Bridge. Each window represents a contiguous HPA that may be interleaved with one or more targets (CXL v3.2 - 9.18.1.3). The Low Memory Hole (LMH) of x86 is a range of addresses of physical low memory to which systems cannot send transactions. In some case the size of that hole is not compatible with the constraint that the CFMWS size shall be multiple of Interleave Ways * 256 MB. (CXL v3.2 - Table 9-22). On those systems, the BIOS publishes CFMWS which communicate the active System Physical Address (SPA) ranges that map to a subset of the Host Physical Address (HPA) ranges. The SPA range trims out the hole, and the capacity in the endpoint is lost with no SPA to map to CXL HPA in that hole. In the early stages of CXL regions construction and attach on platforms that have Low Memory Holes, cxl_add_to_region() fails and returns an error for it can't find any CFMWS range that matches a given endpoint decoder. Detect an LMH by comparing root decoder and endpoint decoder range. Match root decoders HPA range and constructed region with the corresponding endpoint decoders. Construct CXL region with the end of its HPA ranges end adjusted to the matching SPA and adjust the DPA resource end of the hardware decoders to fit the region. Allow the attach target process to complete by allowing regions and decoders to bypass the constraints that don't hold when an LMH is present.[1] [1] commit 7a81173f3 ("cxl: Documentation/driver-api/cxl: Describe the x86 = Low Memory Hole solution") Cc: Alison Schofield Cc: Dan Williams Cc: Dave Jiang Cc: Ira Weiny Signed-off-by: Fabio M. De Francesco Reviewed-by: Gregory Price --- drivers/cxl/core/region.c | 47 ++++++++++++++++++++++++++++++++------- tools/testing/cxl/Kbuild | 1 + 2 files changed, 40 insertions(+), 8 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 43a854036202..9a499bfca23d 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -14,6 +14,7 @@ #include #include #include +#include "platform_quirks.h" #include "core.h" =20 /** @@ -841,6 +842,8 @@ static int match_free_decoder(struct device *dev, const= void *data) static bool region_res_match_cxl_range(const struct cxl_region_params *p, struct range *range) { + struct cxl_decoder *cxld; + if (!p->res) return false; =20 @@ -849,8 +852,13 @@ static bool region_res_match_cxl_range(const struct cx= l_region_params *p, * to be fronted by the DRAM range in current known implementation. * This assumption will be made until a variant implementation exists. */ - return p->res->start + p->cache_size =3D=3D range->start && - p->res->end =3D=3D range->end; + if (p->res->start + p->cache_size =3D=3D range->start && + p->res->end =3D=3D range->end) + return true; + + cxld =3D container_of(range, struct cxl_decoder, hpa_range); + + return platform_region_matches_cxld(p, cxld); } =20 static int match_auto_decoder(struct device *dev, const void *data) @@ -1770,6 +1778,7 @@ static int match_cxlsd_to_cxled_by_range(struct devic= e *dev, const void *data) { const struct cxl_endpoint_decoder *cxled =3D data; struct cxl_switch_decoder *cxlsd; + struct cxl_root_decoder *cxlrd; const struct range *r1, *r2; =20 if (!is_switch_decoder(dev)) @@ -1779,8 +1788,13 @@ static int match_cxlsd_to_cxled_by_range(struct devi= ce *dev, const void *data) r1 =3D &cxlsd->cxld.hpa_range; r2 =3D &cxled->cxld.hpa_range; =20 - if (is_root_decoder(dev)) - return range_contains(r1, r2); + if (is_root_decoder(dev)) { + if (range_contains(r1, r2)) + return 1; + cxlrd =3D to_cxl_root_decoder(dev); + if (platform_cxlrd_matches_cxled(cxlrd, cxled)) + return 1; + } return (r1->start =3D=3D r2->start && r1->end =3D=3D r2->end); } =20 @@ -1997,7 +2011,7 @@ static int cxl_region_attach(struct cxl_region *cxlr, } =20 if (resource_size(cxled->dpa_res) * p->interleave_ways + p->cache_size != =3D - resource_size(p->res)) { + resource_size(p->res) && !platform_cxlrd_matches_cxled(cxlrd, cxled))= { dev_dbg(&cxlr->dev, "%s:%s-size-%#llx * ways-%d + cache-%#llx !=3D region-size-%#llx\n", dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), @@ -3357,7 +3371,8 @@ static int match_cxlrd_to_cxled_by_range(struct devic= e *dev, const void *data) r1 =3D &cxlrd->cxlsd.cxld.hpa_range; r2 =3D &cxled->cxld.hpa_range; =20 - return range_contains(r1, r2); + return (range_contains(r1, r2)) || + (platform_cxlrd_matches_cxled(cxlrd, cxled)); } =20 static struct cxl_decoder * @@ -3406,8 +3421,12 @@ static int match_region_to_cxled_by_range(struct dev= ice *dev, const void *data) p =3D &cxlr->params; =20 guard(rwsem_read)(&cxl_rwsem.region); - if (p->res && p->res->start =3D=3D r->start && p->res->end =3D=3D r->end) - return 1; + if (p->res) { + if (p->res->start =3D=3D r->start && p->res->end =3D=3D r->end) + return 1; + if (platform_region_matches_cxld(p, &cxled->cxld)) + return 1; + } =20 return 0; } @@ -3479,6 +3498,12 @@ static int __construct_region(struct cxl_region *cxl= r, *res =3D DEFINE_RES_MEM_NAMED(hpa->start, range_len(hpa), dev_name(&cxlr->dev)); =20 + /* + * Trim the HPA retrieved from hardware to fit the SPA mapped by the + * platform + */ + platform_res_adjust(res, cxled, cxlrd); + rc =3D cxl_extended_linear_cache_resize(cxlr, res); if (rc && rc !=3D -EOPNOTSUPP) { /* @@ -3588,6 +3613,12 @@ int cxl_add_to_region(struct cxl_endpoint_decoder *c= xled) cxl_find_region_by_range(cxlrd, cxled); if (!cxlr) cxlr =3D construct_region(cxlrd, cxled); + else + /* + * Adjust the Endpoint Decoder's dpa_res to fit the Region which + * it has to be attached to + */ + platform_res_adjust(NULL, cxled, cxlrd); mutex_unlock(&cxlrd->range_lock); =20 rc =3D PTR_ERR_OR_ZERO(cxlr); diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 0d5ce4b74b9f..205f4c813468 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -61,6 +61,7 @@ cxl_core-y +=3D $(CXL_CORE_SRC)/cdat.o cxl_core-y +=3D $(CXL_CORE_SRC)/ras.o cxl_core-$(CONFIG_TRACING) +=3D $(CXL_CORE_SRC)/trace.o cxl_core-$(CONFIG_CXL_REGION) +=3D $(CXL_CORE_SRC)/region.o +cxl_core-$(CONFIG_CXL_PLATFORM_QUIRKS) +=3D $(CXL_CORE_SRC)/platform_quirk= s.o cxl_core-$(CONFIG_CXL_MCE) +=3D $(CXL_CORE_SRC)/mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D $(CXL_CORE_SRC)/features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D $(CXL_CORE_SRC)/edac.o --=20 2.50.1 From nobody Mon Dec 8 01:26:12 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE3FA2D8DA6; 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X-CSE-ConnectionGUID: XuyKweYERDSuL+g7Vq6JTA== X-CSE-MsgGUID: BD86v2RUTHeTkG2fuWl4fw== X-IronPort-AV: E=McAfee;i="6800,10657,11574"; a="61150597" X-IronPort-AV: E=Sophos;i="6.18,320,1751266800"; d="scan'208";a="61150597" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2025 08:59:07 -0700 X-CSE-ConnectionGUID: Q9IMtVk9TiacfrfB73koIA== X-CSE-MsgGUID: LVwMukrOSgyBgVFe47ufpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,320,1751266800"; d="scan'208";a="185189636" Received: from fdefranc-mobl3.ger.corp.intel.com (HELO fdefranc-mobl3.intel.com) ([10.245.245.98]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2025 08:59:03 -0700 From: "Fabio M. De Francesco" To: linux-cxl@vger.kernel.org Cc: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Gregory Price , Robert Richter , Cheatham Benjamin , "Fabio M. De Francesco" Subject: [PATCH 4/4 v5] cxl/test: Simulate an x86 Low Memory Hole for tests Date: Mon, 6 Oct 2025 17:58:07 +0200 Message-ID: <20251006155836.791418-5-fabio.m.de.francesco@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251006155836.791418-1-fabio.m.de.francesco@linux.intel.com> References: <20251006155836.791418-1-fabio.m.de.francesco@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Simulate an x86 Low Memory Hole for the CXL tests by changing the first mock CFMWS range size to 768MB and the CXL Endpoint Decoder HPA range sizes to 1GB. The auto-created region of cxl-test uses mock_cfmws[0], therefore the LMH path in the CXL Driver will be exercised every time the cxl-test module is loaded. Since mock_cfmws[0] range base address is typically different from the one published by the BIOS on real hardware, the driver would fail to create and attach CXL Regions when it's run on the mock environment created by cxl-tests. Furthermore, cxl-topology.sh, cxl-events.sh, and cxl-sanitize.sh, would also fail. To make the above-mentioned tests succeed again, add two "mock" versions of platform_*() that check the HPA range start of mock_cfmws[0] instead of LMH_CFMWS_RANGE_START. When cxl_core calls a cxl_core exported function and that function is mocked by cxl_test, the call chain causes a circular dependency issue. Then add also two "redirect" versions of platform_*() to work out the circular dependency issue. Cc: Alison Schofield Cc: Dan Williams Cc: Dave Jiang Cc: Ira Weiny Signed-off-by: Fabio M. De Francesco Reviewed-by: Dave Jiang --- drivers/cxl/core/platform_quirks.c | 23 +++++++----- drivers/cxl/core/platform_quirks.h | 20 +++++++++-- tools/testing/cxl/cxl_core_exports.c | 23 ++++++++++++ tools/testing/cxl/exports.h | 7 ++++ tools/testing/cxl/test/cxl.c | 54 ++++++++++++++++++++++++++++ tools/testing/cxl/test/mock.c | 48 +++++++++++++++++++++++++ tools/testing/cxl/test/mock.h | 4 +++ 7 files changed, 168 insertions(+), 11 deletions(-) diff --git a/drivers/cxl/core/platform_quirks.c b/drivers/cxl/core/platform= _quirks.c index 7e76e392b1ae..aecd376f2766 100644 --- a/drivers/cxl/core/platform_quirks.c +++ b/drivers/cxl/core/platform_quirks.c @@ -1,20 +1,23 @@ -// SPDX-License-Identifier: GPL-2.0-only +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright(c) 2025 Intel Corporation. */ =20 #include +#include +#include + #include "platform_quirks.h" -#include "cxlmem.h" #include "core.h" =20 /* Start of CFMWS range that end before x86 Low Memory Holes */ #define LMH_CFMWS_RANGE_START 0x0ULL =20 /** - * platform_cxlrd_matches_cxled() - Platform quirk to match CXL Root and + * __platform_cxlrd_matches_cxled() - Platform quirk to match CXL Root and * Endpoint Decoders. It allows matching on platforms with LMH's. * @cxlrd: The Root Decoder against which @cxled is tested for matching. * @cxled: The Endpoint Decoder to be tested for matching @cxlrd. * - * platform_cxlrd_matches_cxled() is typically called from the + * __platform_cxlrd_matches_cxled() is typically called from the * match_*_by_range() functions in region.c. It checks if an endpoint deco= der * matches a given root decoder and returns true to allow the driver to su= cceed * in the construction of regions where it would otherwise fail for the pr= esence @@ -29,8 +32,8 @@ * * Return: true if an endpoint matches a root decoder, else false. */ -bool platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, - const struct cxl_endpoint_decoder *cxled) +bool __platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) { const struct range *rd_r, *sd_r; int align; @@ -47,9 +50,10 @@ bool platform_cxlrd_matches_cxled(const struct cxl_root_= decoder *cxlrd, =20 return false; } +EXPORT_SYMBOL_NS_GPL(__platform_cxlrd_matches_cxled, "CXL"); =20 /** - * platform_region_matches_cxld() - Platform quirk to match a CXL Region a= nd a + * __platform_region_matches_cxld() - Platform quirk to match a CXL Region= and a * Switch or Endpoint Decoder. It allows matching on platforms with LMH's. * @p: Region Params against which @cxled is matched. * @cxld: Switch or Endpoint Decoder to be tested for matching @p. @@ -59,8 +63,8 @@ bool platform_cxlrd_matches_cxled(const struct cxl_root_d= ecoder *cxlrd, * * Return: true if a Decoder matches a Region, else false. */ -bool platform_region_matches_cxld(const struct cxl_region_params *p, - const struct cxl_decoder *cxld) +bool __platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld) { const struct range *r =3D &cxld->hpa_range; const struct resource *res =3D p->res; @@ -73,6 +77,7 @@ bool platform_region_matches_cxld(const struct cxl_region= _params *p, =20 return false; } +EXPORT_SYMBOL_NS_GPL(__platform_region_matches_cxld, "CXL"); =20 void platform_res_adjust(struct resource *res, struct cxl_endpoint_decoder *cxled, diff --git a/drivers/cxl/core/platform_quirks.h b/drivers/cxl/core/platform= _quirks.h index a15592b4e90e..bdea00365dad 100644 --- a/drivers/cxl/core/platform_quirks.h +++ b/drivers/cxl/core/platform_quirks.h @@ -1,4 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright(c) 2025 Intel Corporation. */ + +#ifndef __PLATFORM_QUIRKS_H__ +#define __PLATFORM_QUIRKS_H__ =20 #include "cxl.h" =20 @@ -7,13 +11,17 @@ bool platform_cxlrd_matches_cxled(const struct cxl_root_= decoder *cxlrd, const struct cxl_endpoint_decoder *cxled); bool platform_region_matches_cxld(const struct cxl_region_params *p, const struct cxl_decoder *cxld); +bool __platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled); +bool __platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld); void platform_res_adjust(struct resource *res, struct cxl_endpoint_decoder *cxled, const struct cxl_root_decoder *cxlrd); #else static inline bool -platform_root_decoder_contains(const struct cxl_root_decoder *cxlrd, - const struct cxl_endpoint_decoder *cxled) +platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) { return false; } @@ -31,3 +39,11 @@ inline void platform_res_adjust(struct resource *res, { } #endif /* CONFIG_CXL_PLATFORM_QUIRKS */ + +#ifndef CXL_TEST_ENABLE +#define DECLARE_TESTABLE(x) __##x +#define platform_cxlrd_matches_cxled DECLARE_TESTABLE(platform_cxlrd_match= es_cxled) +#define platform_region_matches_cxld DECLARE_TESTABLE(platform_region_matc= hes_cxld) +#endif + +#endif /* __PLATFORM_QUIRKS_H__ */ diff --git a/tools/testing/cxl/cxl_core_exports.c b/tools/testing/cxl/cxl_c= ore_exports.c index 6754de35598d..a9e37156d126 100644 --- a/tools/testing/cxl/cxl_core_exports.c +++ b/tools/testing/cxl/cxl_core_exports.c @@ -3,6 +3,7 @@ =20 #include "cxl.h" #include "exports.h" +#include "platform_quirks.h" =20 /* Exporting of cxl_core symbols that are only used by cxl_test */ EXPORT_SYMBOL_NS_GPL(cxl_num_decoders_committed, "CXL"); @@ -27,3 +28,25 @@ int devm_cxl_switch_port_decoders_setup(struct cxl_port = *port) return _devm_cxl_switch_port_decoders_setup(port); } EXPORT_SYMBOL_NS_GPL(devm_cxl_switch_port_decoders_setup, "CXL"); + +platform_cxlrd_matches_cxled_fn _platform_cxlrd_matches_cxled =3D + __platform_cxlrd_matches_cxled; +EXPORT_SYMBOL_NS_GPL(_platform_cxlrd_matches_cxled, "CXL"); + +bool platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) +{ + return _platform_cxlrd_matches_cxled(cxlrd, cxled); +} +EXPORT_SYMBOL_NS_GPL(platform_cxlrd_matches_cxled, "CXL"); + +platform_region_matches_cxld_fn _platform_region_matches_cxld =3D + __platform_region_matches_cxld; +EXPORT_SYMBOL_NS_GPL(_platform_region_matches_cxld, "CXL"); + +bool platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld) +{ + return _platform_region_matches_cxld(p, cxld); +} +EXPORT_SYMBOL_NS_GPL(platform_region_matches_cxld, "CXL"); diff --git a/tools/testing/cxl/exports.h b/tools/testing/cxl/exports.h index 7ebee7c0bd67..e0e4c58dadf2 100644 --- a/tools/testing/cxl/exports.h +++ b/tools/testing/cxl/exports.h @@ -10,4 +10,11 @@ extern cxl_add_dport_by_dev_fn _devm_cxl_add_dport_by_de= v; typedef int(*cxl_switch_decoders_setup_fn)(struct cxl_port *port); extern cxl_switch_decoders_setup_fn _devm_cxl_switch_port_decoders_setup; =20 +typedef bool(*platform_cxlrd_matches_cxled_fn)(const struct cxl_root_decod= er *cxlrd, + const struct cxl_endpoint_decoder *cxled); +extern platform_cxlrd_matches_cxled_fn _platform_cxlrd_matches_cxled; + +typedef bool(*platform_region_matches_cxld_fn)(const struct cxl_region_par= ams *p, + const struct cxl_decoder *cxld); +extern platform_region_matches_cxld_fn _platform_region_matches_cxld; #endif diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index 2d135ca533d0..ada431b180f4 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -9,6 +9,8 @@ #include #include #include + +#include #include =20 #include "../watermark.h" @@ -213,7 +215,11 @@ static struct { .restrictions =3D ACPI_CEDT_CFMWS_RESTRICT_HOSTONLYMEM | ACPI_CEDT_CFMWS_RESTRICT_VOLATILE, .qtg_id =3D FAKE_QTG_ID, +#if defined(CONFIG_CXL_PLATFORM_QUIRKS) + .window_size =3D SZ_256M * 3UL, +#else .window_size =3D SZ_256M * 4UL, +#endif }, .target =3D { 0 }, }, @@ -426,6 +432,13 @@ static struct cxl_mock_res *alloc_mock_res(resource_si= ze_t size, int align) return res; } =20 +static u64 mock_cfmws0_range_start; + +static void set_mock_cfmws0_range_start(u64 start) +{ + mock_cfmws0_range_start =3D start; +} + static int populate_cedt(void) { struct cxl_mock_res *res; @@ -454,6 +467,8 @@ static int populate_cedt(void) if (!res) return -ENOMEM; window->base_hpa =3D res->range.start; + if (i =3D=3D 0) + set_mock_cfmws0_range_start(res->range.start); } =20 return 0; @@ -738,7 +753,11 @@ static void mock_init_hdm_decoder(struct cxl_decoder *= cxld) struct cxl_endpoint_decoder *cxled; struct cxl_switch_decoder *cxlsd; struct cxl_port *port, *iter; +#if defined(CONFIG_CXL_PLATFORM_QUIRKS) + const int size =3D SZ_1G; +#else const int size =3D SZ_512M; +#endif struct cxl_memdev *cxlmd; struct cxl_dport *dport; struct device *dev; @@ -1103,6 +1122,39 @@ static void mock_cxl_endpoint_parse_cdat(struct cxl_= port *port) cxl_endpoint_get_perf_coordinates(port, ep_c); } =20 +static bool +mock_platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) +{ + const struct range *rd_r, *ed_r; + int align; + + rd_r =3D &cxlrd->cxlsd.cxld.hpa_range; + ed_r =3D &cxled->cxld.hpa_range; + align =3D cxled->cxld.interleave_ways * SZ_256M; + + return rd_r->start =3D=3D mock_cfmws0_range_start && + rd_r->start =3D=3D ed_r->start && + rd_r->end < (mock_cfmws0_range_start + SZ_4G) && + rd_r->end < ed_r->end && + IS_ALIGNED(range_len(ed_r), align); +} + +static bool +mock_platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld) +{ + const struct range *r =3D &cxld->hpa_range; + const struct resource *res =3D p->res; + int align =3D cxld->interleave_ways * SZ_256M; + + return res->start =3D=3D mock_cfmws0_range_start && + res->start =3D=3D r->start && + res->end < (mock_cfmws0_range_start + SZ_4G) && + res->end < r->end && + IS_ALIGNED(range_len(r), align); +} + static struct cxl_mock_ops cxl_mock_ops =3D { .is_mock_adev =3D is_mock_adev, .is_mock_bridge =3D is_mock_bridge, @@ -1117,6 +1169,8 @@ static struct cxl_mock_ops cxl_mock_ops =3D { .devm_cxl_port_enumerate_dports =3D mock_cxl_port_enumerate_dports, .cxl_endpoint_parse_cdat =3D mock_cxl_endpoint_parse_cdat, .devm_cxl_add_dport_by_dev =3D mock_cxl_add_dport_by_dev, + .platform_cxlrd_matches_cxled =3D mock_platform_cxlrd_matches_cxled, + .platform_region_matches_cxld =3D mock_platform_region_matches_cxld, .list =3D LIST_HEAD_INIT(cxl_mock_ops.list), }; =20 diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index 995269a75cbd..45d8fe67e3e9 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -7,6 +7,8 @@ #include #include #include + +#include #include #include #include "mock.h" @@ -18,6 +20,12 @@ static struct cxl_dport * redirect_devm_cxl_add_dport_by_dev(struct cxl_port *port, struct device *dport_dev); static int redirect_devm_cxl_switch_port_decoders_setup(struct cxl_port *p= ort); +static bool +redirect_platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled); +static bool +redirect_platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld); =20 void register_cxl_mock_ops(struct cxl_mock_ops *ops) { @@ -25,6 +33,8 @@ void register_cxl_mock_ops(struct cxl_mock_ops *ops) _devm_cxl_add_dport_by_dev =3D redirect_devm_cxl_add_dport_by_dev; _devm_cxl_switch_port_decoders_setup =3D redirect_devm_cxl_switch_port_decoders_setup; + _platform_cxlrd_matches_cxled =3D redirect_platform_cxlrd_matches_cxled; + _platform_region_matches_cxld =3D redirect_platform_region_matches_cxld; } EXPORT_SYMBOL_GPL(register_cxl_mock_ops); =20 @@ -35,6 +45,8 @@ void unregister_cxl_mock_ops(struct cxl_mock_ops *ops) _devm_cxl_switch_port_decoders_setup =3D __devm_cxl_switch_port_decoders_setup; _devm_cxl_add_dport_by_dev =3D __devm_cxl_add_dport_by_dev; + _platform_cxlrd_matches_cxled =3D __platform_cxlrd_matches_cxled; + _platform_region_matches_cxld =3D __platform_region_matches_cxld; list_del_rcu(&ops->list); synchronize_srcu(&cxl_mock_srcu); } @@ -285,6 +297,42 @@ struct cxl_dport *redirect_devm_cxl_add_dport_by_dev(s= truct cxl_port *port, return dport; } =20 +static bool +redirect_platform_cxlrd_matches_cxled(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled) +{ + int index; + bool match; + struct cxl_mock_ops *ops =3D get_cxl_mock_ops(&index); + struct cxl_port *port =3D to_cxl_port(cxled->cxld.dev.parent); + + if (ops && ops->is_mock_port(port->uport_dev)) + match =3D ops->platform_cxlrd_matches_cxled(cxlrd, cxled); + else + match =3D __platform_cxlrd_matches_cxled(cxlrd, cxled); + put_cxl_mock_ops(index); + + return match; +} + +static bool +redirect_platform_region_matches_cxld(const struct cxl_region_params *p, + const struct cxl_decoder *cxld) +{ + int index; + bool match; + struct cxl_mock_ops *ops =3D get_cxl_mock_ops(&index); + struct cxl_port *port =3D to_cxl_port(cxld->dev.parent); + + if (ops && ops->is_mock_port(port->uport_dev)) + match =3D ops->platform_region_matches_cxld(p, cxld); + else + match =3D __platform_region_matches_cxld(p, cxld); + put_cxl_mock_ops(index); + + return match; +} + MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("cxl_test: emulation module"); MODULE_IMPORT_NS("ACPI"); diff --git a/tools/testing/cxl/test/mock.h b/tools/testing/cxl/test/mock.h index 4ed932e76aae..803d7cc0197c 100644 --- a/tools/testing/cxl/test/mock.h +++ b/tools/testing/cxl/test/mock.h @@ -25,6 +25,10 @@ struct cxl_mock_ops { void (*cxl_endpoint_parse_cdat)(struct cxl_port *port); struct cxl_dport *(*devm_cxl_add_dport_by_dev)(struct cxl_port *port, struct device *dport_dev); + bool (*platform_cxlrd_matches_cxled)(const struct cxl_root_decoder *cxlrd, + const struct cxl_endpoint_decoder *cxled); + bool (*platform_region_matches_cxld)(const struct cxl_region_params *p, + const struct cxl_decoder *cxld); }; =20 void register_cxl_mock_ops(struct cxl_mock_ops *ops); --=20 2.50.1