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Mon, 6 Oct 2025 11:50:57 +0200 (CEST) From: Matthias Schiffer To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@ew.tq-group.com, Matthias Schiffer Subject: [PATCH] arm64: dts: ti: k3-am642-tqma64xxl: add boot phase tags Date: Mon, 6 Oct 2025 11:50:36 +0200 Message-ID: <20251006095036.16367-1-matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-cloud-security-sender: matthias.schiffer@ew.tq-group.com X-cloud-security-recipient: linux-kernel@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: matthias.schiffer@ew.tq-group.com X-cloud-security-Mailarchivtype: outbound X-cloud-security-Virusscan: CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay95-hz2.antispameurope.com with 4cgDzj62dxz2Dj9k X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest: a80b39d10b8b7722f74fa46e8949e3b1 X-cloud-security: scantime:1.793 DKIM-Signature: a=rsa-sha256; bh=ZrFYIzPuk9rtzNXWXOQAERqhNp/BdwtufnfrutqIGq8=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1759744267; v=1; b=cO81gOx+H6KRj+7k5PztZPs3fmZLaAAZbgsAcE20N+3855VCtM8VqzdEWKXolDG0iM60lNYr UXcKQ09otfbQaRWwXvKivti4Q6X5B3VwdBdKql0drhaK3KlZqAAJBY1wLHY7yCa3875sYGudAkG vcC5qUDj2iEoYXTpCHIHF5VUo2/My5khC9XM58sqX/uXewGzlhGTkkf8IBY6DnxW7eX0HIfi2Kt p7hu6Rz0Kjd+LomSTXA7MTXh/3cG5FmgVg0RRFXUUEmJHUMhwjhCqm856BQqJy9CRsqjuarw5/3 9+XyaRP/QKTUjm+iXHRnmobreAy5p09LRl+ikmc03JqTw== Similar to other AM64x-based boards, add boot phase tags to make the Device Trees usable for firmware/bootloaders without modification. Supported boot devices are eMMC/SD card, SPI-NOR and USB (both mass storage and DFU). The I2C EEPROM is included to allow the firmware to select the correct RAM configuration for different TQMa64xxL variants. Signed-off-by: Matthias Schiffer --- .../dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 12 ++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/= arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts index 8f64d6272b1ba..81e9e047281fd 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -167,6 +167,7 @@ reg_pwm_fan: regulator-pwm-fan { }; =20 reg_sd: regulator-sd { + bootph-all; compatible =3D "regulator-fixed"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc1_reg_pins>; @@ -245,6 +246,7 @@ icssg1_phy0c: ethernet-phy@c { =20 =20 &main_gpio0 { + bootph-all; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_gpio0_digital_pins>, <&main_gpio0_hog_pins>; @@ -263,6 +265,7 @@ &main_gpio0 { }; =20 &main_gpio1 { + bootph-all; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_gpio1_hog_pins>, <&main_gpio1_pru_pins>; @@ -332,6 +335,7 @@ &main_spi0 { =20 /* UART/USB adapter port 1 */ &main_uart0 { + bootph-pre-ram; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins>; status =3D "okay"; @@ -492,11 +496,17 @@ &mcu_uart1 { }; =20 &serdes_ln_ctrl { + bootph-all; idle-states =3D ; }; =20 +&serdes_refclk { + bootph-all; +}; + &serdes0 { serdes0_usb_link: phy@0 { + bootph-all; reg =3D <0>; #phy-cells =3D <0>; resets =3D <&serdes_wiz0 1>; @@ -506,6 +516,7 @@ serdes0_usb_link: phy@0 { }; =20 &sdhci1 { + bootph-all; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc1_pins>; bus-width =3D <4>; @@ -524,6 +535,7 @@ adc { }; =20 &usb0 { + bootph-all; /* * The CDNS USB driver currently doesn't support overcurrent GPIOs, * so there is no overcurrent detection. The OC pin is configured @@ -538,6 +550,7 @@ &usb0 { }; =20 &usbss0 { + bootph-all; ti,vbus-divider; }; =20 @@ -621,6 +634,7 @@ AM64X_IOPAD(0x00ac, PIN_INPUT, 7) }; =20 main_gpio0_hog_pins: main-gpio0-hog-pins { + bootph-all; pinctrl-single,pins =3D < /* (P19) GPMC0_CSn2.GPIO0_43 - MMC1_CTRL */ AM64X_IOPAD(0x00b0, PIN_OUTPUT, 7) @@ -730,6 +744,7 @@ AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) }; =20 main_mmc1_pins: main-mmc1-pins { + bootph-all; pinctrl-single,pins =3D < /* (J19) MMC1_CMD */ AM64X_IOPAD(0x0294, PIN_INPUT, 0) @@ -751,6 +766,7 @@ AM64X_IOPAD(0x0290, PIN_INPUT, 0) }; =20 main_mmc1_reg_pins: main-mmc1-reg-pins { + bootph-all; pinctrl-single,pins =3D < /* (C13) SPI0_CS1.GPIO1_43 - MMC1_SD_EN */ AM64X_IOPAD(0x020c, PIN_OUTPUT, 7) @@ -791,6 +807,7 @@ AM64X_IOPAD(0x026c, PIN_INPUT, 7) }; =20 main_uart0_pins: main-uart0-pins { + bootph-pre-ram; pinctrl-single,pins =3D < /* (D15) UART0_RXD */ AM64X_IOPAD(0x0230, PIN_INPUT, 0) @@ -861,6 +878,7 @@ AM64X_IOPAD(0x0088, PIN_OUTPUT, 2) }; =20 main_usb0_pins: main-usb0-pins { + bootph-all; pinctrl-single,pins =3D < /* (E19) USB0_DRVVBUS */ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am642-tqma64xxl.dtsi index ff3b2e0b8dd45..a78297b9fa57e 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -14,6 +14,7 @@ aliases { }; =20 memory@80000000 { + bootph-pre-ram; device_type =3D "memory"; /* 1G RAM - default variant */ reg =3D <0x00000000 0x80000000 0x00000000 0x40000000>; @@ -54,7 +55,12 @@ reg_1v8: regulator-1v8 { }; }; =20 +&fss { + bootph-all; +}; + &main_i2c0 { + bootph-pre-ram; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_pins>; clock-frequency =3D <400000>; @@ -67,6 +73,7 @@ tmp1075: temperature-sensor@4a { }; =20 eeprom0: eeprom@50 { + bootph-pre-ram; compatible =3D "st,24c02", "atmel,24c02"; reg =3D <0x50>; vcc-supply =3D <®_1v8>; @@ -89,11 +96,13 @@ eeprom1: eeprom@54 { }; =20 &ospi0 { + bootph-all; status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins>; =20 flash@0 { + bootph-all; compatible =3D "jedec,spi-nor"; reg =3D <0>; spi-tx-bus-width =3D <8>; @@ -116,6 +125,7 @@ partitions { }; =20 &sdhci0 { + bootph-all; status =3D "okay"; non-removable; disable-wp; @@ -126,6 +136,7 @@ &sdhci0 { =20 &main_pmx0 { main_i2c0_pins: main-i2c0-pins { + bootph-pre-ram; pinctrl-single,pins =3D < /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) @@ -135,6 +146,7 @@ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) }; =20 ospi0_pins: ospi0-pins { + bootph-all; pinctrl-single,pins =3D < /* (N20) OSPI0_CLK */ AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) --=20 TQ-Systems GmbH | M=C3=BChlstra=C3=9Fe 2, Gut Delling | 82229 Seefeld, Germ= any Amtsgericht M=C3=BCnchen, HRB 105018 Gesch=C3=A4ftsf=C3=BChrer: Detlef Schneider, R=C3=BCdiger Stahl, Stefan Sch= neider https://www.tq-group.com/