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charset="utf-8" The QCS8300 SoC uses the 5nm (v4.2) DSI PHY driver. Signed-off-by: Ayushi Makhija --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +++++++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index 4ea681130dba..7b6e30580463 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -559,6 +559,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_7nm_cfgs }, { .compatible =3D "qcom,dsi-phy-7nm-8150", .data =3D &dsi_phy_7nm_8150_cfgs }, + { .compatible =3D "qcom,qcs8300-dsi-phy-5nm", + .data =3D &dsi_phy_5nm_8300_cfgs }, { .compatible =3D "qcom,sa8775p-dsi-phy-5nm", .data =3D &dsi_phy_5nm_8775p_cfgs }, { .compatible =3D "qcom,sar2130p-dsi-phy-5nm", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index e391505fdaf0..8cb95b9d62a3 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -57,6 +57,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_6375_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8300_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index 32f06edd21a9..28a5d6a2e04e 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -1358,6 +1358,29 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = =3D { .quirks =3D DSI_PHY_7NM_QUIRK_V4_1, }; =20 +const struct msm_dsi_phy_cfg dsi_phy_5nm_8300_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_7nm_48000uA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_7nm_48000uA_regulators), + .ops =3D { + .enable =3D dsi_7nm_phy_enable, + .disable =3D dsi_7nm_phy_disable, + .pll_init =3D dsi_pll_7nm_init, + .save_pll_state =3D dsi_7nm_pll_save_state, + .restore_pll_state =3D dsi_7nm_pll_restore_state, + .set_continuous_clock =3D dsi_7nm_set_continuous_clock, + }, + .min_pll_rate =3D 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate =3D 5000000000UL, +#else + .max_pll_rate =3D ULONG_MAX, +#endif + .io_start =3D { 0xae94400 }, + .num_dsi_phy =3D 1, + .quirks =3D DSI_PHY_7NM_QUIRK_V4_2, +}; + const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs =3D { .has_phy_lane =3D true, .regulator_data =3D dsi_phy_7nm_37750uA_regulators, --=20 2.34.1