From nobody Sun Dec 7 17:22:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BB7A21FF3E; Mon, 6 Oct 2025 16:31:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759768314; cv=none; b=BNcqk0gcciXtU/oruH/K+yx0xt6zOQshs8fttmyPW/g5huqhEpmIwqGOBHUWz9ml3/jl4PZOkWzt1YdPYATHFNi+mo1HwgVpcU5KfdmB7k/gBilMo7/RN08cS3rgl3dLJ+SEHfPHdugfv0wqecEa0FMkkvmelwbClLf2A1SL9W8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759768314; c=relaxed/simple; bh=lmmhiSMSM0QI5UtyLT1oRwAi1Xu2NtSABJdRNdbbkNE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=OBrDHVRkKAzsCD/t4B/4QsL0x0zi9Et8SsM5Q7HoNcAyzIQQRMQZV+QqBq4LV7F/wXQ4LaVUIk9PIKsjRLGY5R1jQ5TYyoWCXmO3kVK/RlLMTmTEo+Ig2bR58mxU4+GGIqbMBv9V/BEmWrYglRx8B4uFMd36SkZqZdX5riwTZEA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CwnYn4NH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CwnYn4NH" Received: by smtp.kernel.org (Postfix) with ESMTPS id EC01DC4CEF5; Mon, 6 Oct 2025 16:31:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759768314; bh=lmmhiSMSM0QI5UtyLT1oRwAi1Xu2NtSABJdRNdbbkNE=; h=From:Date:Subject:To:Cc:Reply-To:From; b=CwnYn4NHuuK2n+KeFOkVrYSrz7n6GusDJdpomGbI25ZrSucN60q12b+U00K9N5Jqo tIxIu75efDoSY0RpM6GXkUJ7gFlKNK+Swvp1ee4nlNimP5stM0KRRgznWB3ykSBFhh pszmsF/cfWyXCmT1AR00Cyy1O8ROROl2A3QiLzBLp+gmTea4mBWqaqgOlFiJOPGYfJ Goxm52Ko5z7ft7lhqv+oQ83w5QN6N6I7g7LRLx9tvp+eI62DzGEJIbjh3QtYH7xrje gq/qXCKamoh5wGnf/u7uDmGtc7NLtawyIw6Zp3+Bxc4PbQ9RkwJV18VlWVMRT5/Sks zVE9CJFsWMdJg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D95F8CCA470; Mon, 6 Oct 2025 16:31:53 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Mon, 06 Oct 2025 18:31:28 +0200 Subject: [PATCH] arm64: dts: freescale: Add GMAC Ethernet for S32G2 EVB and RDB2 and S32G3 RDB3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251006-nxp-s32g-boards-v1-1-f70a57b8087f@oss.nxp.com> X-B4-Tracking: v=1; b=H4sIAN/u42gC/x3MMQqAMAxA0atIZgNtJIJeRRysjTVLlQZEEO9uc XzD/w+YFBWDsXmgyKWmR67wbQPrvuQkqLEayBF753rM94nWUcJwLCUaUvTcE3PggaBWZ5FN7/8 4ze/7AaoG5dxhAAAA To: Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran Cc: linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759768312; l=7038; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=TMWFQ/FCO7r1LG54aYnEDegZ7oUI5MIx6sPdhGBxOcA=; b=BYkrZtIcJy8FigoNiS7KdvSacfpqLvQ8+glEubaeNymGK1JA+8tu/tR1m9gshcgR22HkuQ5Mw Cmy9eQyLBqgD4z5OxjWHaoTIiGXyJAXPiv+S2FEYTssNJq0IC465zL+ X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" Add support for the Ethernet connection over GMAC controller connected to the Micrel KSZ9031 Ethernet RGMII PHY located on the boards. The mentioned GMAC controller is one of two network controllers embedded on the NXP Automotive SoCs S32G2 and S32G3. The supported boards: * EVB: S32G-VNP-EVB with S32G2 SoC * RDB2: S32G-VNP-RDB2 * RDB3: S32G-VNP-RDB3 Signed-off-by: Jan Petrous (OSS) --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 50 +++++++++++++++++++++= +++- arch/arm64/boot/dts/freescale/s32g274a-evb.dts | 21 ++++++++++- arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 19 ++++++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 50 +++++++++++++++++++++= +++- arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts | 21 ++++++++++- 5 files changed, 157 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index d167624d1f0c..d06103e9564e 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright 2017-2021, 2024 NXP + * Copyright 2017-2021, 2024-2025 NXP */ =20 #include @@ -738,5 +738,53 @@ gic: interrupt-controller@50800000 { interrupt-controller; #interrupt-cells =3D <3>; }; + + gmac0: ethernet@4033c000 { + compatible =3D "nxp,s32g2-dwmac"; + reg =3D <0x4033c000 0x2000>, /* gmac IP */ + <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + interrupt-parent =3D <&gic>; + interrupts =3D ; + interrupt-names =3D "macirq"; + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + status =3D "disabled"; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <5>; + + queue0 { + }; + queue1 { + }; + queue2 { + }; + queue3 { + }; + queue4 { + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <5>; + + queue0 { + }; + queue1 { + }; + queue2 { + }; + queue3 { + }; + queue4 { + }; + }; + + gmac0mdio: mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/bo= ot/dts/freescale/s32g274a-evb.dts index c4a195dd67bf..f020da03979a 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (c) 2021 SUSE LLC - * Copyright 2019-2021, 2024 NXP + * Copyright 2019-2021, 2024-2025 NXP */ =20 /dts-v1/; @@ -15,6 +15,7 @@ / { =20 aliases { serial0 =3D &uart0; + ethernet0 =3D &gmac0; }; =20 chosen { @@ -43,3 +44,21 @@ &usdhc0 { no-1-8-v; status =3D "okay"; }; + +&gmac0 { + clocks =3D <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>; + clock-names =3D "stmmaceth", "tx", "rx", "ptp_ref"; + phy-mode =3D "rgmii-id"; + phy-handle =3D <&rgmiiaphy4>; + status =3D "okay"; +}; + +&gmac0mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* KSZ 9031 on RGMII */ + rgmiiaphy4: ethernet-phy@4 { + reg =3D <4>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/b= oot/dts/freescale/s32g274a-rdb2.dts index 4f58be68c818..b9c2f964b3f7 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -16,6 +16,7 @@ / { aliases { serial0 =3D &uart0; serial1 =3D &uart1; + ethernet0 =3D &gmac0; }; =20 chosen { @@ -77,3 +78,21 @@ &usdhc0 { no-1-8-v; status =3D "okay"; }; + +&gmac0 { + clocks =3D <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>; + clock-names =3D "stmmaceth", "tx", "rx", "ptp_ref"; + phy-mode =3D "rgmii-id"; + phy-handle =3D <&rgmiiaphy1>; + status =3D "okay"; +}; + +&gmac0mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* KSZ 9031 on RGMII */ + rgmiiaphy1: ethernet-phy@1 { + reg =3D <1>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index be3a582ebc1b..e31184847371 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2024 NXP + * Copyright 2021-2025 NXP * * Authors: Ghennadi Procopciuc * Ciprian Costea @@ -883,6 +883,54 @@ gic: interrupt-controller@50800000 { <0x50420000 0x2000>; interrupts =3D ; }; + + gmac0: ethernet@4033c000 { + compatible =3D "nxp,s32g2-dwmac"; + reg =3D <0x4033c000 0x2000>, /* gmac IP */ + <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + interrupt-parent =3D <&gic>; + interrupts =3D ; + interrupt-names =3D "macirq"; + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + status =3D "disabled"; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <5>; + + queue0 { + }; + queue1 { + }; + queue2 { + }; + queue3 { + }; + queue4 { + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <5>; + + queue0 { + }; + queue1 { + }; + queue2 { + }; + queue3 { + }; + queue4 { + }; + }; + + gmac0mdio: mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + }; + }; }; =20 timer { diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/b= oot/dts/freescale/s32g399a-rdb3.dts index e94f70ad82d9..4a74923789ae 100644 --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2024 NXP + * Copyright 2021-2025 NXP * * NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3) */ @@ -18,6 +18,7 @@ aliases { mmc0 =3D &usdhc0; serial0 =3D &uart0; serial1 =3D &uart1; + ethernet0 =3D &gmac0; }; =20 chosen { @@ -93,3 +94,21 @@ &usdhc0 { disable-wp; status =3D "okay"; }; + +&gmac0 { + clocks =3D <&clks 24>, <&clks 19>, <&clks 18>, <&clks 15>; + clock-names =3D "stmmaceth", "tx", "rx", "ptp_ref"; + phy-mode =3D "rgmii-id"; + phy-handle =3D <&rgmiiaphy1>; + status =3D "okay"; +}; + +&gmac0mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* KSZ 9031 on RGMII */ + rgmiiaphy1: ethernet-phy@1 { + reg =3D <1>; + }; +}; --- base-commit: fd94619c43360eb44d28bd3ef326a4f85c600a07 change-id: 20251006-nxp-s32g-boards-2d156255b592 Best regards, --=20 Jan Petrous (OSS)