From nobody Tue Dec 16 14:06:47 2025 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4243D2BDC33 for ; Sun, 5 Oct 2025 18:25:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759688724; cv=none; b=fzpp7e8JemAmP/FOXxC0ApGhZcNKN0lwEQHhYh/8El8h5l7NhKDNtcAaGi6b/8g/AhExgKH6hmxOKZhn+IZMO+/R6h5ZmDq2bTLQmVDbXkqurgKG4uYkWBnykPSZ1u7f/l2O6moCgcQjxiCgDq4XQuDW7oeXrOrWzJb57O27+TQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759688724; c=relaxed/simple; bh=qMjIbwYMAuOeeb3lZC984a5F6vCSE2V08joJ6sCxp7k=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=QlALkXGUNT/bQqbhMSSZ+ql5cFMABZOa1F21b2wEXC61ioUWHNScqM6mSve3kBKAXdMTzecrKA6UAojQSL9CEwzekQ1cmVyD5iDuIM66s/4U35rRQcfFV0SBrAERbuSCdq3OttTm2xUC91BST6SbLvMjgZFPFem1ZCxSVZ7krnw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=XkdnQv6e; arc=none smtp.client-ip=209.85.214.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="XkdnQv6e" Received: by mail-pl1-f202.google.com with SMTP id d9443c01a7336-269a2b255aaso84450165ad.3 for ; Sun, 05 Oct 2025 11:25:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1759688722; x=1760293522; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=uJhsW1hGYJW72QWRZReISG89bcn0FqU0RmaVC7Uf79w=; b=XkdnQv6ejHnwjn2P7jTsjmkGkNFkjEsHhh1m/a6l6RZHLssHi/kiBIc8RiXYUYWNwP dWp0t5puKyltD/v5ghCdmn2vXdL9PuTCIgIzO/zyVcvRFFMiYunIAxqmOCKqSQxH0bHK k8VHwYqVMiesg8pQxM0qwJXDGmIhkcQHr0rCdSHZXJsFb3E6Cy3fpFnwh5vBDoMRw1+R bCDAdkR1oG6dGeZaL74OKJd4f6xBoNn9p4i58Ztajjlge640Sfw2bwfvPIkdR9pYcPnQ UUYW73H2ppcsuaIugpmaVUEY/qpFar2pD+JoVcpxQJPQ5QfCmAAtvq/fNMBhUio7lvKa tkPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759688722; x=1760293522; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=uJhsW1hGYJW72QWRZReISG89bcn0FqU0RmaVC7Uf79w=; b=o0NLDfvA4Mrk585D/ZSyCM+OC2pRazUqgYNaPe0JVmOM3ysF3gNVlEgFIQ8W6bQvVe /nDpvaWvylB8GmNpGTWu8C0CVWSOw//1Z76Y80i/yIvzuITCYJJczmXETmiTuOQTg3de qkNA9lVHpQGiECBU5jO1ffuFwjWc2jrEFM92DQIFlw62RXdiTHS+BaZ9HkKqoY0wfd/r fky+4OlhcQ9RAcOSCgFcCePQP4VhMdPHmyVGpNVLI5bmwWi3/Z/f1+VfI3TNlFMhdjSR s7loJcHfUxmicMkzBnq8UaX/991P4zkZE2bppag8XTaJCQIcMUKGxTNo8zS/rmAMGatE OR2w== X-Forwarded-Encrypted: i=1; AJvYcCXaaiD6Jw4q5nWsXIXz10jOhAFo66fwCytXWJdDtObnvZq7EEe3uGfo1X2IH/XWSXNGESG9iYpHukUsDEc=@vger.kernel.org X-Gm-Message-State: AOJu0YyUKiBxX8Q8MFJL27sydaaf1FtUWsZPaGRiXwsqc8nGXr59sSbq mzYyDVCMYzBWEtR3d3GEQoO+ufsYkexqOWfvlm3QhJZhWH5ory5vUCMHI8nXGRYnyl3eSXxk4uy 5GUAPEVZPtA== X-Google-Smtp-Source: AGHT+IGmD2E2S0sufuWwBotiMffQlv0OpCpHb4j0ySHRaSIu/JATasNHLEWkm3pwMUXOyJTNQByKnp3Fa6lE X-Received: from plbbj2.prod.google.com ([2002:a17:902:8502:b0:28e:807f:b050]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:244a:b0:25d:37fc:32df with SMTP id d9443c01a7336-28e9a6be280mr137674515ad.47.1759688721729; Sun, 05 Oct 2025 11:25:21 -0700 (PDT) Date: Sun, 5 Oct 2025 11:24:25 -0700 In-Reply-To: <20251005182430.2791371-1-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251005182430.2791371-1-irogers@google.com> X-Mailer: git-send-email 2.51.0.618.g983fd99d29-goog Message-ID: <20251005182430.2791371-23-irogers@google.com> Subject: [PATCH v7 22/27] perf test parse-events: Without a PMU use cpu-cycles rather than cycles From: Ian Rogers To: James Clark , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Adrian Hunter , Xu Yang , Thomas Falcon , Andi Kleen , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Atish Patra , Beeman Strong , Leo Yan , Vince Weaver Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Without a PMU perf matches an event against any PMU with the event. Unfortunately some PMU drivers advertise a "cycles" event which is typically just a core event. Switch to using "cpu-cycles" which is an indentical legacy event but avoids the multiple PMU confusion introduced by the PMU drivers. Note, on x86 cpu-cycles is also a sysfs event but cycles isn't. Signed-off-by: Ian Rogers --- tools/perf/tests/parse-events.c | 61 ++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 28 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index f6cd994f75cf..23f3e265e2a1 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -585,9 +585,10 @@ static int test__checkevent_pmu(struct evlist *evlist) { =20 struct evsel *evsel =3D evlist__first(evlist); + struct perf_pmu *core_pmu =3D perf_pmus__find_core_pmu(); =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong type", core_pmu->type =3D=3D evsel->core.attr.type= ); TEST_ASSERT_VAL("wrong config", test_config(evsel, 10)); TEST_ASSERT_VAL("wrong config1", 1 =3D=3D evsel->core.attr.config1); TEST_ASSERT_VAL("wrong config2", 3 =3D=3D evsel->core.attr.config2); @@ -646,17 +647,18 @@ static int test__checkevent_list(struct evlist *evlis= t) static int test__checkevent_pmu_name(struct evlist *evlist) { struct evsel *evsel =3D evlist__first(evlist); + struct perf_pmu *core_pmu =3D perf_pmus__find_core_pmu(); =20 /* cpu/config=3D1,name=3Dkrava/u */ TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong type", core_pmu->type =3D=3D evsel->core.attr.type= ); TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong name", evsel__name_is(evsel, "krava")); =20 /* cpu/config=3D2/u" */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong type", core_pmu->type =3D=3D evsel->core.attr.type= ); TEST_ASSERT_VAL("wrong config", 2 =3D=3D evsel->core.attr.config); TEST_ASSERT_VAL("wrong name", evsel__name_is(evsel, "cpu/config=3D2/u")); =20 @@ -666,10 +668,11 @@ static int test__checkevent_pmu_name(struct evlist *e= vlist) static int test__checkevent_pmu_partial_time_callgraph(struct evlist *evli= st) { struct evsel *evsel =3D evlist__first(evlist); + struct perf_pmu *core_pmu =3D perf_pmus__find_core_pmu(); =20 /* cpu/config=3D1,call-graph=3Dfp,time,period=3D100000/ */ TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong type", core_pmu->type =3D=3D evsel->core.attr.type= ); TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); /* * The period, time and callgraph value gets configured within evlist__co= nfig, @@ -681,7 +684,7 @@ static int test__checkevent_pmu_partial_time_callgraph(= struct evlist *evlist) =20 /* cpu/config=3D2,call-graph=3Dno,time=3D0,period=3D2000/ */ evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong type", core_pmu->type =3D=3D evsel->core.attr.type= ); TEST_ASSERT_VAL("wrong config", 2 =3D=3D evsel->core.attr.config); /* * The period, time and callgraph value gets configured within evlist__co= nfig, @@ -697,12 +700,14 @@ static int test__checkevent_pmu_partial_time_callgrap= h(struct evlist *evlist) static int test__checkevent_pmu_events(struct evlist *evlist) { struct evsel *evsel; + struct perf_pmu *core_pmu =3D perf_pmus__find_core_pmu(); =20 TEST_ASSERT_VAL("wrong number of entries", 1 <=3D evlist->core.nr_entries= ); =20 evlist__for_each_entry(evlist, evsel) { - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type= || - strcmp(evsel->pmu->name, "cpu")); + TEST_ASSERT_VAL("wrong type", core_pmu->type =3D=3D evsel->core.attr.typ= e || + !strncmp(evsel__name(evsel), evsel->pmu->name, + strlen(evsel->pmu->name))); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1650,7 +1655,7 @@ static int test__checkevent_complex_name(struct evlis= t *evlist) =20 TEST_ASSERT_VAL("wrong complex name parsing", evsel__name_is(evsel, - "COMPLEX_CYCLES_NAME:orig=3Dcycles,desc=3Dchip-clock-ticks")); + "COMPLEX_CYCLES_NAME:orig=3Dcpu-cycles,desc=3Dchip-clock-ticks"= )); return TEST_OK; } =20 @@ -1787,7 +1792,7 @@ static const struct evlist_test test__events[] =3D { /* 4 */ }, { - .name =3D "cycles/period=3D100000,config2/", + .name =3D "cpu-cycles/period=3D100000,config2/", .check =3D test__checkevent_symbolic_name_config, /* 5 */ }, @@ -1902,27 +1907,27 @@ static const struct evlist_test test__events[] =3D { /* 7 */ }, { - .name =3D "{instructions:k,cycles:upp}", + .name =3D "{instructions:k,cpu-cycles:upp}", .check =3D test__group1, /* 8 */ }, { - .name =3D "{faults:k,branches}:u,cycles:k", + .name =3D "{faults:k,branches}:u,cpu-cycles:k", .check =3D test__group2, /* 9 */ }, { - .name =3D "group1{syscalls:sys_enter_openat:H,cycles:kppp},group2{cycle= s,1:3}:G,instructions:u", + .name =3D "group1{syscalls:sys_enter_openat:H,cpu-cycles:kppp},group2{c= pu-cycles,1:3}:G,instructions:u", .check =3D test__group3, /* 0 */ }, { - .name =3D "{cycles:u,instructions:kp}:p", + .name =3D "{cpu-cycles:u,instructions:kp}:p", .check =3D test__group4, /* 1 */ }, { - .name =3D "{cycles,instructions}:G,{cycles:G,instructions:G},cycles", + .name =3D "{cpu-cycles,instructions}:G,{cpu-cycles:G,instructions:G},cp= u-cycles", .check =3D test__group5, /* 2 */ }, @@ -1932,27 +1937,27 @@ static const struct evlist_test test__events[] =3D { /* 3 */ }, { - .name =3D "{cycles,cache-misses:G}:H", + .name =3D "{cpu-cycles,cache-misses:G}:H", .check =3D test__group_gh1, /* 4 */ }, { - .name =3D "{cycles,cache-misses:H}:G", + .name =3D "{cpu-cycles,cache-misses:H}:G", .check =3D test__group_gh2, /* 5 */ }, { - .name =3D "{cycles:G,cache-misses:H}:u", + .name =3D "{cpu-cycles:G,cache-misses:H}:u", .check =3D test__group_gh3, /* 6 */ }, { - .name =3D "{cycles:G,cache-misses:H}:uG", + .name =3D "{cpu-cycles:G,cache-misses:H}:uG", .check =3D test__group_gh4, /* 7 */ }, { - .name =3D "{cycles,cache-misses,branch-misses}:S", + .name =3D "{cpu-cycles,cache-misses,branch-misses}:S", .check =3D test__leader_sample1, /* 8 */ }, @@ -1967,7 +1972,7 @@ static const struct evlist_test test__events[] =3D { /* 0 */ }, { - .name =3D "{cycles,cache-misses,branch-misses}:D", + .name =3D "{cpu-cycles,cache-misses,branch-misses}:D", .check =3D test__pinned_group, /* 1 */ }, @@ -2005,7 +2010,7 @@ static const struct evlist_test test__events[] =3D { /* 6 */ }, { - .name =3D "task-clock:P,cycles", + .name =3D "task-clock:P,cpu-cycles", .check =3D test__checkevent_precise_max_modifier, /* 7 */ }, @@ -2036,17 +2041,17 @@ static const struct evlist_test test__events[] =3D { /* 2 */ }, { - .name =3D "cycles/name=3D'COMPLEX_CYCLES_NAME:orig=3Dcycles,desc=3Dchip= -clock-ticks'/Duk", + .name =3D "cpu-cycles/name=3D'COMPLEX_CYCLES_NAME:orig=3Dcpu-cycles,des= c=3Dchip-clock-ticks'/Duk", .check =3D test__checkevent_complex_name, /* 3 */ }, { - .name =3D "cycles//u", + .name =3D "cpu-cycles//u", .check =3D test__sym_event_slash, /* 4 */ }, { - .name =3D "cycles:k", + .name =3D "cpu-cycles:k", .check =3D test__sym_event_dc, /* 5 */ }, @@ -2056,17 +2061,17 @@ static const struct evlist_test test__events[] =3D { /* 6 */ }, { - .name =3D "{cycles,cache-misses,branch-misses}:e", + .name =3D "{cpu-cycles,cache-misses,branch-misses}:e", .check =3D test__exclusive_group, /* 7 */ }, { - .name =3D "cycles/name=3Dname/", + .name =3D "cpu-cycles/name=3Dname/", .check =3D test__term_equal_term, /* 8 */ }, { - .name =3D "cycles/name=3Dl1d/", + .name =3D "cpu-cycles/name=3Dl1d/", .check =3D test__term_equal_legacy, /* 9 */ }, @@ -2174,7 +2179,7 @@ static const struct evlist_test test__events_pmu[] = =3D { /* 2 */ }, { - .name =3D "cpu/name=3D'COMPLEX_CYCLES_NAME:orig=3Dcycles,desc=3Dchip-cl= ock-ticks',period=3D0x1,event=3D0x2/ukp", + .name =3D "cpu/name=3D'COMPLEX_CYCLES_NAME:orig=3Dcpu-cycles,desc=3Dchi= p-clock-ticks',period=3D0x1,event=3D0x2/ukp", .valid =3D test__pmu_cpu_event_valid, .check =3D test__checkevent_complex_name, /* 3 */ --=20 2.51.0.618.g983fd99d29-goog