From nobody Wed Dec 17 10:48:04 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 20948277C94; Sun, 5 Oct 2025 11:15:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759662914; cv=none; b=uTMHBWmeT7YLC57fbBDgvUWZpmN0S1pqdky+YLTyykimuAOL493z1SvLXgZmULd6RobfA+QUhNh8EWL7dT2PDjNzfrmL/pe0nhs7a6akSqBjDe51bUB6BMKc+IKIRIKTWCQcFA+vBmyf7be4kRQsyfrksAewoG9NdbT5BaZAH38= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759662914; c=relaxed/simple; bh=J4CNEHp4HvP3XE7b+mw/WOyh+fdkB63bMKeRpIS/Lkc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sNcWbJkt2GUWL72+wzlkkfQTXUUqNXS2YoqZ1L6HdVQL/x7uDy4tswtniTi+Wwbc9V0eIUGbFIVNA4UM6SJpybFUcfEavzcXz1fjdz/cqUFiXIbXpxTmkix3VRFa1hobiyS4ax9YE8/sLJ1c3MucIaaM+CSkaoxrNNwb0F50J8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: TMiLM7RYRKGFuew7C0n5Vg== X-CSE-MsgGUID: zubjI6XdQiGmNvxhTdWaBw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 05 Oct 2025 20:15:12 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.25]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9C92A40065D7; Sun, 5 Oct 2025 20:15:08 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 6/6] arm64: defconfig: enable RZ/T2H / RZ/N2H ADC driver Date: Sun, 5 Oct 2025 14:13:22 +0300 Message-ID: <20251005111323.804638-7-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs include three 12-Bit successive approximation A/D converters. RZ/T2H has two ADCs with 4 channels and one with 6. RZ/N2H has two ADCs with 4 channels and one with 15. Enable the driver for them. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8fd1bf869942..3a1326652d47 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1581,6 +1581,7 @@ CONFIG_QCOM_SPMI_VADC=3Dm CONFIG_QCOM_SPMI_ADC5=3Dm CONFIG_ROCKCHIP_SARADC=3Dm CONFIG_RZG2L_ADC=3Dm +CONFIG_RZT2H_ADC=3Dm CONFIG_SOPHGO_CV1800B_ADC=3Dm CONFIG_TI_ADS1015=3Dm CONFIG_TI_AM335X_ADC=3Dm --=20 2.51.0