From nobody Wed Dec 17 08:58:01 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0A68A24DD00; Sun, 5 Oct 2025 11:14:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759662894; cv=none; b=tHzUsvgxEbzyUIcKSngaXjYcLGW3Z3tbV5udR50sQOQM3hpoRMvkQc8/Q4sZeAU8Rk4rnP7wndhAE1UoA0UW9swBCNslFSGPKXs0jYfj5syCNc3VAzykZ0B940xSgsBnlf5KXhe0JPekigSHMKeuGOz+0WzYVs/FigOjInk4hGk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759662894; c=relaxed/simple; bh=flfBbhak/YrsZJhiUlCQnOSGQcRNBKtGFS2x79uQJFw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WzG04N4tIzMMg5+NYwIiqRclttHoVieh/wcnGJIOeSNHk/IXrOf8nhGesu98WZ/GDmeTTbzOmLIXWmdJ5Aiw0NuQo6gKEgpXtMl2nWoBAXJYio3yBEBI62sxyy4ieAl3PMK0YKaeDCcq2z00dl1Yv/5tvZ7hytGtMn4nc73i2c8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: ibfIh42cTBmmRfCe0UUoGw== X-CSE-MsgGUID: K1BREhvAScSrGdjwTUf5Zg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 05 Oct 2025 20:14:45 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.25]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 4C10440062B8; Sun, 5 Oct 2025 20:14:41 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Conor Dooley Subject: [PATCH v4 1/6] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC Date: Sun, 5 Oct 2025 14:13:17 +0300 Message-ID: <20251005111323.804638-2-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the A/D 12-Bit successive approximation converters found in the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. RZ/T2H has two ADCs with 4 channels and one with 6. RZ/N2H has two ADCs with 4 channels and one with 15. Signed-off-by: Cosmin Tanislav Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- .../iio/adc/renesas,r9a09g077-adc.yaml | 135 ++++++++++++++++++ MAINTAINERS | 7 + 2 files changed, 142 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/renesas,r9a09= g077-adc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-ad= c.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.ya= ml new file mode 100644 index 000000000000..dc0206b28231 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/T2H / RZ/N2H ADC12 + +maintainers: + - Cosmin Tanislav + +description: | + A/D Converter block is a successive approximation analog-to-digital conv= erter + with a 12-bit accuracy. Up to 16 analog input channels can be selected. + Conversions can be performed in single or continuous mode. Result of the= ADC + is stored in a 16-bit data register corresponding to each channel. + +properties: + compatible: + oneOf: + - items: + - const: renesas,r9a09g087-adc # RZ/N2H + - const: renesas,r9a09g077-adc # RZ/T2H + - items: + - const: renesas,r9a09g077-adc # RZ/T2H + + reg: + maxItems: 1 + + interrupts: + items: + - description: A/D scan end interrupt + - description: A/D scan end interrupt for Group B + - description: A/D scan end interrupt for Group C + - description: Window A compare match + - description: Window B compare match + - description: Compare match + - description: Compare mismatch + + interrupt-names: + items: + - const: adi + - const: gbadi + - const: gcadi + - const: cmpai + - const: cmpbi + - const: wcmpm + - const: wcmpum + + clocks: + items: + - description: Converter clock + - description: Peripheral clock + + clock-names: + items: + - const: adclk + - const: pclk + + power-domains: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + "#io-channel-cells": + const: 1 + +patternProperties: + "^channel@[0-9a-f]$": + $ref: adc.yaml + type: object + description: The external channels which are connected to the ADC. + + properties: + reg: + description: The channel number. + maximum: 15 + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + + adc@80008000 { + compatible =3D "renesas,r9a09g077-adc"; + reg =3D <0x80008000 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, + <&cpg CPG_MOD 225>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + + channel@0 { + reg =3D <0x0>; + }; + channel@1 { + reg =3D <0x1>; + }; + channel@2 { + reg =3D <0x2>; + }; + channel@3 { + reg =3D <0x3>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 07363437c278..ff2a3257a498 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21835,6 +21835,13 @@ S: Supported F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml F: drivers/counter/rz-mtu3-cnt.c =20 +RENESAS RZ/T2H / RZ/N2H A/D DRIVER +M: Cosmin Tanislav +L: linux-iio@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml + RENESAS RTCA-3 RTC DRIVER M: Claudiu Beznea L: linux-rtc@vger.kernel.org --=20 2.51.0 From nobody Wed Dec 17 08:58:01 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2B5692741C0; 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dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: NAVcumTcRSGqH4BufWjlpw== X-CSE-MsgGUID: f6lN6uW+RZyrFTI+DFoNHA== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 05 Oct 2025 20:14:50 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.25]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id C674C40065C2; Sun, 5 Oct 2025 20:14:46 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/6] iio: adc: add RZ/T2H / RZ/N2H ADC driver Date: Sun, 5 Oct 2025 14:13:18 +0300 Message-ID: <20251005111323.804638-3-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add support for the A/D 12-Bit successive approximation converters found in the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. RZ/T2H has two ADCs with 4 channels and one with 6. RZ/N2H has two ADCs with 4 channels and one with 15. Conversions can be performed in single or continuous mode. Result of the conversion is stored in a 16-bit data register corresponding to each channel. The conversions can be started by a software trigger, a synchronous trigger (from MTU or from ELC) or an asynchronous external trigger (from ADTRGn# pin). Only single mode with software trigger is supported for now. Signed-off-by: Cosmin Tanislav Reviewed-by: Nuno S=C3=A1 --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 11 ++ drivers/iio/adc/Makefile | 1 + drivers/iio/adc/rzt2h_adc.c | 304 ++++++++++++++++++++++++++++++++++++ 4 files changed, 317 insertions(+) create mode 100644 drivers/iio/adc/rzt2h_adc.c diff --git a/MAINTAINERS b/MAINTAINERS index ff2a3257a498..28f939ed03f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21841,6 +21841,7 @@ L: linux-iio@vger.kernel.org L: linux-renesas-soc@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml +F: drivers/iio/adc/rzt2h_adc.c =20 RENESAS RTCA-3 RTC DRIVER M: Claudiu Beznea diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 58a14e6833f6..b0580fcefef5 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1403,6 +1403,17 @@ config RZG2L_ADC To compile this driver as a module, choose M here: the module will be called rzg2l_adc. =20 +config RZT2H_ADC + tristate "Renesas RZ/T2H / RZ/N2H ADC driver" + depends on ARCH_RENESAS || COMPILE_TEST + select IIO_ADC_HELPER + help + Say yes here to build support for the ADC found in Renesas + RZ/T2H / RZ/N2H SoCs. + + To compile this driver as a module, choose M here: the + module will be called rzt2h_adc. + config SC27XX_ADC tristate "Spreadtrum SC27xx series PMICs ADC" depends on MFD_SC27XX_PMIC || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index d008f78dc010..ed647a734c51 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -123,6 +123,7 @@ obj-$(CONFIG_ROHM_BD79112) +=3D rohm-bd79112.o obj-$(CONFIG_ROHM_BD79124) +=3D rohm-bd79124.o obj-$(CONFIG_ROCKCHIP_SARADC) +=3D rockchip_saradc.o obj-$(CONFIG_RZG2L_ADC) +=3D rzg2l_adc.o +obj-$(CONFIG_RZT2H_ADC) +=3D rzt2h_adc.o obj-$(CONFIG_SC27XX_ADC) +=3D sc27xx_adc.o obj-$(CONFIG_SD_ADC_MODULATOR) +=3D sd_adc_modulator.o obj-$(CONFIG_SOPHGO_CV1800B_ADC) +=3D sophgo-cv1800b-adc.o diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c new file mode 100644 index 000000000000..33ce5cc44ff4 --- /dev/null +++ b/drivers/iio/adc/rzt2h_adc.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RZT2H_ADCSR_REG 0x00 +#define RZT2H_ADCSR_ADIE_MASK BIT(12) +#define RZT2H_ADCSR_ADCS_MASK GENMASK(14, 13) +#define RZT2H_ADCSR_ADCS_SINGLE 0b00 +#define RZT2H_ADCSR_ADST_MASK BIT(15) + +#define RZT2H_ADANSA0_REG 0x04 +#define RZT2H_ADANSA0_CH_MASK(x) BIT(x) + +#define RZT2H_ADDR_REG(x) (0x20 + 0x2 * (x)) + +#define RZT2H_ADCALCTL_REG 0x1f0 +#define RZT2H_ADCALCTL_CAL_MASK BIT(0) +#define RZT2H_ADCALCTL_CAL_RDY_MASK BIT(1) +#define RZT2H_ADCALCTL_CAL_ERR_MASK BIT(2) + +#define RZT2H_ADC_MAX_CHANNELS 16 + +struct rzt2h_adc { + void __iomem *base; + struct device *dev; + + struct completion completion; + /* lock to protect against multiple access to the device */ + struct mutex lock; + + const struct iio_chan_spec *channels; + unsigned int num_channels; + unsigned int max_channels; +}; + +static void rzt2h_adc_start(struct rzt2h_adc *adc, unsigned int conversion= _type) +{ + u16 reg; + + reg =3D readw(adc->base + RZT2H_ADCSR_REG); + + /* Set conversion type */ + FIELD_MODIFY(RZT2H_ADCSR_ADCS_MASK, ®, conversion_type); + + /* Set end of conversion interrupt and start bit. */ + reg |=3D RZT2H_ADCSR_ADIE_MASK | RZT2H_ADCSR_ADST_MASK; + + writew(reg, adc->base + RZT2H_ADCSR_REG); +} + +static void rzt2h_adc_stop(struct rzt2h_adc *adc) +{ + u16 reg; + + reg =3D readw(adc->base + RZT2H_ADCSR_REG); + + /* Clear end of conversion interrupt and start bit. */ + reg &=3D ~(RZT2H_ADCSR_ADIE_MASK | RZT2H_ADCSR_ADST_MASK); + + writew(reg, adc->base + RZT2H_ADCSR_REG); +} + +static int rzt2h_adc_read_single(struct rzt2h_adc *adc, unsigned int ch, i= nt *val) +{ + int ret; + + ret =3D pm_runtime_resume_and_get(adc->dev); + if (ret) + return ret; + + mutex_lock(&adc->lock); + + reinit_completion(&adc->completion); + + /* Enable a single channel */ + writew(RZT2H_ADANSA0_CH_MASK(ch), adc->base + RZT2H_ADANSA0_REG); + + rzt2h_adc_start(adc, RZT2H_ADCSR_ADCS_SINGLE); + + /* + * Datasheet Page 2770, Table 41.1: + * 0.32us per channel when sample-and-hold circuits are not in use. + */ + ret =3D wait_for_completion_timeout(&adc->completion, usecs_to_jiffies(1)= ); + if (!ret) { + ret =3D -ETIMEDOUT; + goto disable; + } + + *val =3D readw(adc->base + RZT2H_ADDR_REG(ch)); + ret =3D IIO_VAL_INT; + +disable: + rzt2h_adc_stop(adc); + + mutex_unlock(&adc->lock); + + pm_runtime_put_autosuspend(adc->dev); + + return ret; +} + +static void rzt2h_adc_set_cal(struct rzt2h_adc *adc, bool cal) +{ + u16 val; + + val =3D readw(adc->base + RZT2H_ADCALCTL_REG); + if (cal) + val |=3D RZT2H_ADCALCTL_CAL_MASK; + else + val &=3D ~RZT2H_ADCALCTL_CAL_MASK; + + writew(val, adc->base + RZT2H_ADCALCTL_REG); +} + +static int rzt2h_adc_calibrate(struct rzt2h_adc *adc) +{ + u16 val; + int ret; + + rzt2h_adc_set_cal(adc, true); + + ret =3D read_poll_timeout(readw, val, val & RZT2H_ADCALCTL_CAL_RDY_MASK, + 200, 1000, true, adc->base + RZT2H_ADCALCTL_REG); + if (ret) { + dev_err(adc->dev, "Calibration timed out: %d\n", ret); + return ret; + } + + rzt2h_adc_set_cal(adc, false); + + if (val & RZT2H_ADCALCTL_CAL_ERR_MASK) { + dev_err(adc->dev, "Calibration failed\n"); + return -EINVAL; + } + + return 0; +} + +static int rzt2h_adc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + return rzt2h_adc_read_single(adc, chan->channel, val); + case IIO_CHAN_INFO_SCALE: + *val =3D 1800; + *val2 =3D 12; + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static const struct iio_info rzt2h_adc_iio_info =3D { + .read_raw =3D rzt2h_adc_read_raw, +}; + +static irqreturn_t rzt2h_adc_isr(int irq, void *private) +{ + struct rzt2h_adc *adc =3D private; + + complete(&adc->completion); + + return IRQ_HANDLED; +} + +static const struct iio_chan_spec rzt2h_adc_chan_template =3D { + .indexed =3D 1, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .type =3D IIO_VOLTAGE, +}; + +static int rzt2h_adc_parse_properties(struct rzt2h_adc *adc) +{ + struct iio_chan_spec *chan_array; + unsigned int i; + int ret; + + ret =3D devm_iio_adc_device_alloc_chaninfo_se(adc->dev, + &rzt2h_adc_chan_template, + RZT2H_ADC_MAX_CHANNELS - 1, + &chan_array); + if (ret < 0) + return dev_err_probe(adc->dev, ret, "Failed to read channel info"); + + adc->num_channels =3D ret; + adc->channels =3D chan_array; + + for (i =3D 0; i < adc->num_channels; i++) + if (chan_array[i].channel + 1 > adc->max_channels) + adc->max_channels =3D chan_array[i].channel + 1; + + return 0; +} + +static int rzt2h_adc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct iio_dev *indio_dev; + struct rzt2h_adc *adc; + int ret, irq; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*adc)); + if (!indio_dev) + return -ENOMEM; + + adc =3D iio_priv(indio_dev); + adc->dev =3D dev; + init_completion(&adc->completion); + + ret =3D devm_mutex_init(dev, &adc->lock); + if (ret) + return ret; + + platform_set_drvdata(pdev, adc); + + ret =3D rzt2h_adc_parse_properties(adc); + if (ret) + return ret; + + adc->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(adc->base)) + return PTR_ERR(adc->base); + + pm_runtime_set_autosuspend_delay(dev, 300); + pm_runtime_use_autosuspend(dev); + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + irq =3D platform_get_irq_byname(pdev, "adi"); + if (irq < 0) + return irq; + + ret =3D devm_request_irq(dev, irq, rzt2h_adc_isr, 0, dev_name(dev), adc); + if (ret) + return ret; + + indio_dev->name =3D "rzt2h-adc"; + indio_dev->info =3D &rzt2h_adc_iio_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D adc->channels; + indio_dev->num_channels =3D adc->num_channels; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id rzt2h_adc_match[] =3D { + { .compatible =3D "renesas,r9a09g077-adc" }, + { } +}; +MODULE_DEVICE_TABLE(of, rzt2h_adc_match); + +static int rzt2h_adc_pm_runtime_resume(struct device *dev) +{ + struct rzt2h_adc *adc =3D dev_get_drvdata(dev); + + /* + * Datasheet Page 2810, Section 41.5.6: + * After release from the module-stop state, wait for at least + * 0.5 =C2=B5s before starting A/D conversion. + */ + fsleep(1); + + return rzt2h_adc_calibrate(adc); +} + +static const struct dev_pm_ops rzt2h_adc_pm_ops =3D { + RUNTIME_PM_OPS(NULL, rzt2h_adc_pm_runtime_resume, NULL) +}; + +static struct platform_driver rzt2h_adc_driver =3D { + .probe =3D rzt2h_adc_probe, + .driver =3D { + .name =3D "rzt2h-adc", + .of_match_table =3D rzt2h_adc_match, + .pm =3D pm_ptr(&rzt2h_adc_pm_ops), + }, +}; + +module_platform_driver(rzt2h_adc_driver); + +MODULE_AUTHOR("Cosmin Tanislav "); +MODULE_DESCRIPTION("Renesas RZ/T2H / RZ/N2H ADC driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_DRIVER"); --=20 2.51.0 From nobody Wed Dec 17 08:58:01 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 83525275AFA; Sun, 5 Oct 2025 11:14:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759662898; cv=none; b=S7Xs9T+rowumucpk5sqombTX80b+OqKLVOFjZm1Ci36uQSFOLU+reTroFAUpF59whG+9GnPkzMNqzeWLnP97Xu7lcwKAy/vU1gKAFlBHyn5TcJs+UxzTf7SxqO9uYy1ZZzRectBh+/Z2HNupL4yrw5BU8WuGSyTsfMF/k3cjea0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759662898; c=relaxed/simple; bh=wRYietIbYqy1aTADssYy9XF+qFKPJMGpcKP0PoHKpYM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OT8efxXDMlGExdOsxnhnbB+Bu+VOr2Hb0niLXR4V9qLG1FsbdWcY1etT/mtueZeYfZ/naU8W9aaK5gP5qniIBgMvWnqjyjiw9VYz+n2QaBeuLMmAodtX+r6SlLtDnnNM345uX0+oR9+QYdEzIf4ifCCaqBYS7LY6QMjaKmzmIec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: Cg3ESZTnSSy55z4qZ0+eRA== X-CSE-MsgGUID: 3V1/StNZSRm+PFfq6dju/A== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 05 Oct 2025 20:14:56 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.25]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 347C340065C2; Sun, 5 Oct 2025 20:14:51 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/6] arm64: dts: renesas: r9a09g077: Add ADCs support Date: Sun, 5 Oct 2025 14:13:19 +0300 Message-ID: <20251005111323.804638-4-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Renesas RZ/T2H (R9A09G077) includes three 12-Bit successive approximation A/D converters, two 4-channel ADCs, and one 6-channel ADC. Add support for all of them. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index 37a696d8ec6d..320a7bf5292c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -666,6 +666,72 @@ gic: interrupt-controller@83000000 { interrupts =3D ; }; =20 + adc0: adc@90014000 { + compatible =3D "renesas,r9a09g077-adc"; + reg =3D <0 0x90014000 0 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, + <&cpg CPG_MOD 206>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + + adc1: adc@90014400 { + compatible =3D "renesas,r9a09g077-adc"; + reg =3D <0 0x90014400 0 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, + <&cpg CPG_MOD 207>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + + adc2: adc@80008000 { + compatible =3D "renesas,r9a09g077-adc"; + reg =3D <0 0x80008000 0 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, + <&cpg CPG_MOD 225>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + ohci: usb@92040000 { compatible =3D "generic-ohci"; reg =3D <0 0x92040000 0 0x100>; --=20 2.51.0 From nobody Wed Dec 17 08:58:01 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 05581275AFA; Sun, 5 Oct 2025 11:15:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759662903; cv=none; b=tHemRskMAW8CqTDYYrH6VyeW7MtsxYpKlMgPFwBGNKPBOmBHNlpvE4iyS+iED5Fwy4Ur/cOLbRvB2XQMECtZNN5tTakKGFBOcYq3TuqB5Yxu3Yaf82KERuSwCyzgN8tAbQnLOUNu+wl0w/R7K8zokknT/e39dzeYrErih0Y84Tw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759662903; c=relaxed/simple; bh=ujGjY6RglhSnCCR8wWBzsB/sZtCynLq5C9mq7ypzR/c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mxUE71/Nj0g3daBtW3cCL0Ww/lW39Ng5KkzxlScOOVM233ZOKK4N24bm+QjcvOeaTXaZ1qIfjihx4O0b/rfmPdfRxWnZDM5CqKvrYZvb2ItpoxVhw62dO6ft/wdfZiSpnOodW/A6Mxu8xwwBqhF++vf6SEPzl26TVNN4TGNcX/4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: t+KpznjFSgGvMuUALA8+Ig== X-CSE-MsgGUID: Lo8JF4YtQY++wYiQ1fWmNw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 05 Oct 2025 20:15:01 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.25]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 912B040065D7; Sun, 5 Oct 2025 20:14:57 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/6] arm64: dts: renesas: r9a09g087: Add ADCs support Date: Sun, 5 Oct 2025 14:13:20 +0300 Message-ID: <20251005111323.804638-5-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Renesas RZ/T2H (R9A09G087) includes three 12-Bit successive approximation A/D converters, two 4-channel ADCs, and one 15-channel ADC. Add support for all of them. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi index 88669868f0ee..53d9266e58ca 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -666,6 +666,72 @@ gic: interrupt-controller@83000000 { interrupts =3D ; }; =20 + adc0: adc@90014000 { + compatible =3D "renesas,r9a09g087-adc", "renesas,r9a09g077-adc"; + reg =3D <0 0x90014000 0 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, + <&cpg CPG_MOD 206>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + + adc1: adc@90014400 { + compatible =3D "renesas,r9a09g087-adc", "renesas,r9a09g077-adc"; + reg =3D <0 0x90014400 0 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, + <&cpg CPG_MOD 207>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + + adc2: adc@80008000 { + compatible =3D "renesas,r9a09g087-adc", "renesas,r9a09g077-adc"; + reg =3D <0 0x80008000 0 0x400>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "adi", "gbadi", "gcadi", + "cmpai", "cmpbi", "wcmpm", "wcmpum"; + clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, + <&cpg CPG_MOD 225>; + clock-names =3D "adclk", "pclk"; + power-domains =3D <&cpg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + ohci: usb@92040000 { compatible =3D "generic-ohci"; reg =3D <0 0x92040000 0 0x100>; --=20 2.51.0 From nobody Wed Dec 17 08:58:01 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 76C772750E6; Sun, 5 Oct 2025 11:15:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759662910; cv=none; b=nxNpgqLzEUqYxqJ5F+fw7aJLJ+II1v5V1LTQJ+wPHIcmVpM8mDK5m2/w5qnCTC3Ltv+TD2L/RfiuyIzThATlaFruatU3ypSuOSbCVXazmWJs4LhqPvngW61GaNrgc9VtNCUXCtxWsS9LtF3Cd7pCBb/pWfwlo52FRf56LmWEj1c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759662910; c=relaxed/simple; bh=skxjDaWPB9IA85ZAfsGjn7OJCN/V8auFFnaq1bjdDJE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jTjIHaDSN5fu2NFYn9JwDhq+e5zqQH/EigXg0mSLpFrp1x8dryIyY/i8zPvskIAQLa17d/1Y81o0/MXY6Dy8j77mXvP2d+8gZFbjrXrTjW+m4jh8Gsgs+uMpXh0cLoYXSdh6pOqlwJ1hOwcU6716pzpOeuSskYzRcyHoSB/7yBg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: JZ26yOZwTeW9FfAn0kazqQ== X-CSE-MsgGUID: LlP2ieR3Tki9eBu5XXeDnQ== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 05 Oct 2025 20:15:07 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.25]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 2C6DF40065C2; Sun, 5 Oct 2025 20:15:02 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 5/6] arm64: dts: renesas: rzt2h/rzn2h-evk: enable ADCs Date: Sun, 5 Oct 2025 14:13:21 +0300 Message-ID: <20251005111323.804638-6-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ADCs on RZ/T2H and RZ/N2H are exposed on the evaluation kit boards. Enable them. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 28 +++++++ .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 64 +++++++++++++++ .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 79 +++++++++++++++++++ 3 files changed, 171 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 9170c563208a..e94b84393bd9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -252,3 +252,31 @@ usb_pins: usb-pins { ; /* OVRCUR */ }; }; + +&adc2 { + status =3D "okay"; + + channel@0 { + reg =3D <0x0>; + }; + + channel@1 { + reg =3D <0x1>; + }; + + channel@2 { + reg =3D <0x2>; + }; + + channel@3 { + reg =3D <0x3>; + }; + + channel@4 { + reg =3D <0x4>; + }; + + channel@5 { + reg =3D <0x5>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index 279f2510044b..d27da157c6d6 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -305,3 +305,67 @@ usb_pins: usb-pins { ; /* OVRCUR */ }; }; + +&adc2 { + status =3D "okay"; + + channel@0 { + reg =3D <0x0>; + }; + + channel@1 { + reg =3D <0x1>; + }; + + channel@2 { + reg =3D <0x2>; + }; + + channel@3 { + reg =3D <0x3>; + }; + + channel@4 { + reg =3D <0x4>; + }; + + channel@5 { + reg =3D <0x5>; + }; + + channel@6 { + reg =3D <0x6>; + }; + + channel@7 { + reg =3D <0x7>; + }; + + channel@8 { + reg =3D <0x8>; + }; + + channel@9 { + reg =3D <0x9>; + }; + + channel@a { + reg =3D <0xa>; + }; + + channel@b { + reg =3D <0xb>; + }; + + channel@c { + reg =3D <0xc>; + }; + + channel@d { + reg =3D <0xd>; + }; + + channel@e { + reg =3D <0xe>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/a= rm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 9ca26725a3e9..a7123a9ec684 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -338,3 +338,82 @@ &wdt2 { status =3D "okay"; timeout-sec =3D <60>; }; + +/* + * ADC0 AN000 can be connected to a potentiometer on the board or + * exposed on ADC header. + * + * T2H: + * SW17[1] =3D ON, SW17[2] =3D OFF - Potentiometer + * SW17[1] =3D OFF, SW17[2] =3D ON - CN41 header + * N2H: + * DSW6[1] =3D OFF, DSW6[2] =3D ON - Potentiometer + * DSW6[1] =3D ON, DSW6[2] =3D OFF - CN3 header + */ +&adc0 { + status =3D "okay"; + + channel@0 { + reg =3D <0x0>; + }; + + channel@1 { + reg =3D <0x1>; + }; + + channel@2 { + reg =3D <0x2>; + }; + + channel@3 { + reg =3D <0x3>; + }; +}; + +/* + * ADC1 AN100 can be exposed on ADC header or on mikroBUS connector. + * + * T2H: + * SW18[1] =3D ON, SW18[2] =3D OFF - CN42 header + * SW18[1] =3D OFF, SW18[2] =3D ON - mikroBUS + * N2H: + * DSW6[3] =3D ON, DSW6[4] =3D OFF - CN4 header + * DSW6[3] =3D OFF, DSW6[4] =3D ON - mikroBUS + * + * ADC1 AN101 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[3] =3D ON, SW18[4] =3D OFF - CN42 header + * SW18[3] =3D OFF, SW18[4] =3D ON - Grove2 + * N2H: + * DSW6[5] =3D ON, DSW6[6] =3D OFF - CN4 header + * DSW6[5] =3D OFF, DSW6[6] =3D ON - Grove2 + * + * ADC1 AN102 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[5] =3D ON, SW18[6] =3D OFF - CN42 header + * SW18[5] =3D OFF, SW18[6] =3D ON - Grove2 + * N2H: + * DSW6[7] =3D ON, DSW6[8] =3D OFF - CN4 header + * DSW6[7] =3D OFF, DSW6[8] =3D ON - Grove2 + */ +&adc1 { + status =3D "okay"; + + channel@0 { + reg =3D <0x0>; + }; + + channel@1 { + reg =3D <0x1>; + }; + + channel@2 { + reg =3D <0x2>; + }; + + channel@3 { + reg =3D <0x3>; + }; +}; --=20 2.51.0 From nobody Wed Dec 17 08:58:01 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 20948277C94; Sun, 5 Oct 2025 11:15:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759662914; cv=none; b=uTMHBWmeT7YLC57fbBDgvUWZpmN0S1pqdky+YLTyykimuAOL493z1SvLXgZmULd6RobfA+QUhNh8EWL7dT2PDjNzfrmL/pe0nhs7a6akSqBjDe51bUB6BMKc+IKIRIKTWCQcFA+vBmyf7be4kRQsyfrksAewoG9NdbT5BaZAH38= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759662914; c=relaxed/simple; bh=J4CNEHp4HvP3XE7b+mw/WOyh+fdkB63bMKeRpIS/Lkc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sNcWbJkt2GUWL72+wzlkkfQTXUUqNXS2YoqZ1L6HdVQL/x7uDy4tswtniTi+Wwbc9V0eIUGbFIVNA4UM6SJpybFUcfEavzcXz1fjdz/cqUFiXIbXpxTmkix3VRFa1hobiyS4ax9YE8/sLJ1c3MucIaaM+CSkaoxrNNwb0F50J8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: TMiLM7RYRKGFuew7C0n5Vg== X-CSE-MsgGUID: zubjI6XdQiGmNvxhTdWaBw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 05 Oct 2025 20:15:12 +0900 Received: from demon-pc.localdomain (unknown [10.226.92.25]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9C92A40065D7; Sun, 5 Oct 2025 20:15:08 +0900 (JST) From: Cosmin Tanislav To: Cc: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 6/6] arm64: defconfig: enable RZ/T2H / RZ/N2H ADC driver Date: Sun, 5 Oct 2025 14:13:22 +0300 Message-ID: <20251005111323.804638-7-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251005111323.804638-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs include three 12-Bit successive approximation A/D converters. RZ/T2H has two ADCs with 4 channels and one with 6. RZ/N2H has two ADCs with 4 channels and one with 15. Enable the driver for them. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8fd1bf869942..3a1326652d47 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1581,6 +1581,7 @@ CONFIG_QCOM_SPMI_VADC=3Dm CONFIG_QCOM_SPMI_ADC5=3Dm CONFIG_ROCKCHIP_SARADC=3Dm CONFIG_RZG2L_ADC=3Dm +CONFIG_RZT2H_ADC=3Dm CONFIG_SOPHGO_CV1800B_ADC=3Dm CONFIG_TI_ADS1015=3Dm CONFIG_TI_AM335X_ADC=3Dm --=20 2.51.0