From nobody Wed Dec 17 21:11:38 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B264126C1E; Sun, 5 Oct 2025 13:16:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759670193; cv=none; b=RlHjb/XInNYfaOakPp4p6tOocUaH9dChUzpqHhGMsHzgaD+6kA9TIq1/kFkYsN2WcaKYYRK9G+i8EWa8YrdL6L5WpTM1unvROOzK64CXI+6qWWdL5b3wKGhxoufSyBx5+27AmT6VbEzMi48dBvflbYjU917JvcL0TGGaQ0hICPI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759670193; c=relaxed/simple; bh=JErM5ScgJpejd1xSGbR3OGOLEYV2kFmuZcqKMyHIp0Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Xwnjld6J4ArskywKbeMaGinUUptNru7r1EKX43uF9jOYHNC+mdiFQEOiPHnidPtH8QkZa688duIHpmm+bQ0EOA87avj8QeELNFFZ7X8pK676EUfkesK106jhcYZOYA7cM67PtwLl+L/JMcxD55reQ5D5H7mu/iXS1QGYzGbeaso= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=enJvUKTJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="enJvUKTJ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3F873C4CEFE; Sun, 5 Oct 2025 13:16:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759670193; bh=JErM5ScgJpejd1xSGbR3OGOLEYV2kFmuZcqKMyHIp0Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=enJvUKTJEp9Yta8y3Mi65oqSn1xXKiOP8DzBJQq4SedfQmYY8t/PyNqrpgLKVVI7Q o8NDW1NQxc8lU1LrQRTXEUbLoFDj+c+O9sSYQoKzdHD5llXG4K4pryi6tR9X8uBqlf dsvcEBhmZ/ifo/XXO0XjGRvG6RzBzFddhjd8nMSYIavL//rCjPFs8qNX1TZ6908WQK d9mqg1pVzdQhZMrdBZHZt5sh+PX5KTxc+Q06NeReSg5GQAyffZVV4CHgSFrYVoRjcb GeGTdA4HY5WZ08unP2YAfJJ2NWT0RIXWq7Uvb0TuEKWshP0WCWFEpCcH4RuyWvQuRz Xm6d6MB4O75Fg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37ED5CAC5B8; Sun, 5 Oct 2025 13:16:33 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Sun, 05 Oct 2025 15:16:29 +0200 Subject: [PATCH 2/2] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251005-pixel-3-v1-2-ab8b85f6133f@ixit.cz> References: <20251005-pixel-3-v1-0-ab8b85f6133f@ixit.cz> In-Reply-To: <20251005-pixel-3-v1-0-ab8b85f6133f@ixit.cz> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, David Heidelberg , Amit Pundir , Casey Connolly , Joel Selvaraj , Sumit Semwal , Vinod Koul , Bjorn Andersson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=19359; i=david@ixit.cz; h=from:subject:message-id; bh=jKRi63NZRPoBMo8buLZ14emOcrMVxMODYhjx+7ThNA0=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBo4m+vfV90kVDZRwSGd6NxxeEK71URPpFNK1SEh 6q2FWGvEGuJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaOJvrwAKCRBgAj/E00kg chwdD/94l3gfvZ7EGqzpbvZLV+JS/gSdHilFK0oBu1dYxZVlN40hu44B+6Kj6CXYHOBUUXPPorw FvWvoEL8lKzp04M08A3PThpkzfE6HBw9ugiQyMUQ9+DrSJUcKewo9WMKMDeeh7zTzC2kM7fRWzf 6H+sn1qS0QOo0Fa6kSU+sedo0wIDPfeVIYYVzRqKRRlIvPEAXHresZd4EZa+psPwQH4lzzmgQCq FA4pz6O0jA+NJtv5QGWsPEUkxpqliy6oKGpo51TRoiLFB9uANOgsWv15sIexFbU5jtFVRfphi16 JOqJLUSho5pOxKquN3EjM29oa+2kOX+RR3O4UJohUIs5GpN3nLf8QiLOc08W/rAWyMcRPNV26kr 0cnqCNcOM2ZUicN4xCuvhIl4mw1giT2siOVUkFPot+yN+SwcqE1RAEsXs8m7ZMhmidp/eTxynCo Q78XXvYwwWThI4CsUr2cuk9M7Gfcn3OHxN36MeXiTbe6UKHuLjULGZJxUZKmTO5Ff8rJo8tYn7V rnK/QRUnjRQ/M7ffxYEagzN1CPmBk0ypUm9Wb8iRlBIxiRHXAEDk0ht+g5/dpHbGc4buJ08OqLP d40WEuOyKP0Y59k7v1rZpQX2Zjt+toDitj75UZF9CUKz91gae88HgkQALJr/DYO29wQmIOX2neK BZ8yK0oBxKvxSIw== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg This adds initial device tree support for the following phones: - Google Pixel 3 (blueline) - Google Pixel 3 XL (crosshatch) Both phone boards use the same identifiers and differ only slightly in their connected peripherals. Supported functionality includes: - Debug UART - UFS - Charger - USB-C (peripheral mode) - Display (Pixel 3 only) GPIOs 0=E2=80=933 and 81=E2=80=9384 are not accessible from the application= CPUs, so they are marked as reserved to allow the Pixel 3 to boot. The rmtfs region is allocated using UIO, making it technically "dynamic." Its address and size can be read from sysfs: $ cat /sys/class/uio/uio0/name /sys/class/uio/uio0/maps/map0/addr 0x00000000f2701000 $ cat /sys/class/uio/uio0/maps/map0/size 0x0000000000200000 Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either side of the rmtfs region to work around an XPU bug that would otherwise cause erroneous violations when accessing the rmtfs_mem region. Co-developed-by: Amit Pundir Signed-off-by: Amit Pundir Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Co-developed-by: Casey Connolly Signed-off-by: Casey Connolly Co-developed-by: Joel Selvaraj Signed-off-by: Joel Selvaraj Co-developed-by: Sumit Semwal Signed-off-by: Sumit Semwal Co-developed-by: Vinod Koul Signed-off-by: Vinod Koul Signed-off-by: David Heidelberg --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../arm64/boot/dts/qcom/sdm845-google-blueline.dts | 128 ++++++ arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 467 +++++++++++++++++= ++++ .../boot/dts/qcom/sdm845-google-crosshatch.dts | 137 ++++++ 4 files changed, 734 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 4bfa926b6a085..ba05dc935dc7c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -239,6 +239,8 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine-dtbs :=3D sdm845-db845c.dtb sdm845-db84= 5c-navigation-mezzanine.dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-db845c-navigation-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-google-crosshatch.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-google-blueline.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-lg-judyln.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-lg-judyp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm845-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm= 64/boot/dts/qcom/sdm845-google-blueline.dts new file mode 100644 index 0000000000000..df88982018b9e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sdm845-google-common.dtsi" + +/ { + model =3D "Google Pixel 3"; + compatible =3D "google,blueline", "qcom,sdm845"; + + battery: battery { + compatible =3D "simple-battery"; + + charge-full-design-microamp-hours =3D <2970000>; + voltage-min-design-microvolt =3D <3600000>; + voltage-max-design-microvolt =3D <4400000>; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* for u-boot */ + framebuffer: framebuffer@9d400000 { + compatible =3D "simple-framebuffer"; + reg =3D <0 0x9d400000 0 (2160 * 1080 * 4)>; + width =3D <1080>; + height =3D <2160>; + stride =3D <(1080 * 4)>; + format =3D "a8r8g8b8"; + }; + }; + + reserved-memory { + framebuffer_region@9d400000 { + no-map; + reg =3D <0 0x9d400000 0 0x02400000>; // FIXME + }; + }; +}; + +&gmu { + status =3D "okay"; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + status =3D "okay"; + vdda-supply =3D <&vdda_mipi_dsi0_1p2>; + + ports { + port@1 { + endpoint { + remote-endpoint =3D <&panel_in>; + data-lanes =3D <0 1 2 3>; + qcom,te-source =3D "mdp_vsync_e"; + }; + }; + }; + + panel@0 { + compatible =3D "lg,sw43408"; + reg =3D <0>; + + vddi-supply =3D <&vreg_l14a_1p88>; + vpnl-supply =3D <&vreg_l28a_3p0>; + + reset-gpios =3D <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&panel_reset_pins &panel_te_pin &panel_pmgpio_pins>; + + port { + panel_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&panel_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vdda_mipi_dsi0_pll>; + + status =3D "okay"; +}; + +&pm8998_gpios { + panel_pmgpio_pins: panel-pmgpio-active-state { + pins =3D "gpio2", "gpio5"; + function =3D "normal"; + input-enable; + bias-disable; + power-source =3D <0>; + }; +}; + +&tlmm { + panel_te_pin: panel-te-state { + pins =3D "gpio12"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + panel_reset_pins: panel-active-state { + pins =3D "gpio6"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + panel_suspend: panel-suspend-state { + pins =3D "gpio6"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm6= 4/boot/dts/qcom/sdm845-google-common.dtsi new file mode 100644 index 0000000000000..5015e54aed20c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -0,0 +1,467 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &rmtfs_mem; + +/ { + chassis-type =3D "handset"; + qcom,board-id =3D <0x00021505 0>; + qcom,msm-id =3D ; + + aliases { + serial0 =3D &uart9; + serial1 =3D &uart6; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + reserved-memory { + mpss_region: memory@8e000000 { + reg =3D <0 0x8e000000 0 0x9800000>; + no-map; + }; + + venus_mem: venus@97800000 { + reg =3D <0 0x97800000 0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp-mem@97D00000 { + reg =3D <0 0x97D00000 0 0x800000>; + no-map; + }; + + mba_region: mba@98500000 { + reg =3D <0 0x98500000 0 0x200000>; + no-map; + }; + + slpi_mem: slpi@98700000 { + reg =3D <0 0x98700000 0 0x1400000>; + no-map; + }; + + spss_mem: spss@99B00000 { + reg =3D <0 0x99B00000 0 0x100000>; + no-map; + }; + + /* rmtfs lower guard */ + memory@f2700000 { + reg =3D <0 0xf2700000 0 0x1000>; + no-map; + }; + + rmtfs_mem: memory@f2701000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0 0xf2701000 0 0x200000>; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D <15>; + }; + + /* rmtfs upper guard */ + memory@f2901000 { + reg =3D <0 0xf2901000 0 0x1000>; + no-map; + }; + }; + + volume-keys { + compatible =3D "gpio-keys"; + label =3D "Volume keys"; + autorepeat; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&volume_up_gpio>; + + key-vol-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + }; + + vreg_s4a_1p8: vreg-s4a-1p8-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_s4a_1p8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vph_pwr>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + vdd-s7-supply =3D <&vph_pwr>; + vdd-s8-supply =3D <&vph_pwr>; + vdd-s9-supply =3D <&vph_pwr>; + vdd-s10-supply =3D <&vph_pwr>; + vdd-s11-supply =3D <&vph_pwr>; + vdd-s12-supply =3D <&vph_pwr>; + vdd-s13-supply =3D <&vph_pwr>; + vdd-l1-l27-supply =3D <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply =3D <&vreg_s3a_1p35>; + vdd-l3-l11-supply =3D <&vreg_s7a_1p025>; + vdd-l4-l5-supply =3D <&vreg_s7a_1p025>; + vdd-l6-supply =3D <&vph_pwr>; + vdd-l7-l12-l14-l15-supply =3D <&vreg_s5a_2p04>; + vdd-l9-supply =3D <&vreg_bob>; + vdd-l10-l23-l25-supply =3D <&vreg_bob>; + vdd-l13-l19-l21-supply =3D <&vreg_bob>; + vdd-l16-l28-supply =3D <&vreg_bob>; + vdd-l18-l22-supply =3D <&vreg_bob>; + vdd-l20-l24-supply =3D <&vreg_bob>; + vdd-l26-supply =3D <&vreg_s3a_1p35>; + vin-lvs-1-2-supply =3D <&vreg_s4a_1p8>; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt =3D <1352000>; + regulator-max-microvolt =3D <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt =3D <1904000>; + regulator-max-microvolt =3D <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1028000>; + }; + + vdda_mipi_dsi0_pll: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-boot-on; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-initial-mode =3D ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt =3D <1304000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l19a_3p3: ldo19 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + /* + * The touchscreen needs this to be 3.3v, which is apparently + * quite close to the hardware limit for this LDO (3.312v) + * It must be kept in high power mode to prevent TS brownouts + */ + regulator-allowed-modes =3D ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2968000>; + regulator-initial-mode =3D ; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2968000>; + regulator-initial-mode =3D ; + }; + + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt =3D <3088000>; + regulator-max-microvolt =3D <3088000>; + regulator-initial-mode =3D ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3312000>; + regulator-initial-mode =3D ; + }; + + vdda_mipi_dsi0_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-boot-on; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt =3D <2856000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-bob-supply =3D <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt =3D <3312000>; + regulator-max-microvolt =3D <3600000>; + regulator-initial-mode =3D ; + regulator-allow-bypass; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <600000>; + }; + }; +}; + +&gcc { + protected-clocks =3D , + , + ; +}; + +&gpi_dma0 { + status =3D "okay"; +}; + +&pm8998_gpios { + volume_up_gpio: vol-up-active-state { + pins =3D "gpio6"; + function =3D "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength =3D <0>; + }; +}; + +&pm8998_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&pmi8998_charger { + monitored-battery =3D <&battery>; + + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&qup_uart9_rx { + drive-strength =3D <2>; + bias-pull-up; +}; + +&qup_uart9_tx { + drive-strength =3D <2>; + bias-disable; +}; + +&tlmm { + gpio-reserved-ranges =3D <0 4>, <81 4>; + + touchscreen_reset: ts-reset-state { + pins =3D "gpio99"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + }; + + touchscreen_pins: ts-pins-gpio-state { + pins =3D "gpio125"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + touchscreen_i2c_pins: qup-i2c2-gpio-state { + pins =3D "gpio27", "gpio28"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; +}; + +&uart6 { + pinctrl-0 =3D <&qup_uart6_4pin>; + + status =3D "okay"; +}; + +&uart9 { + label =3D "LS-UART1"; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l1a_0p875>; + vdda-pll-supply =3D <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply =3D <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value =3D <8>; + qcom,hstx-trim-value =3D ; + qcom,preemphasis-level =3D ; + qcom,preemphasis-width =3D ; + + status =3D "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply =3D <&vreg_l26a_1p2>; + vdda-pll-supply =3D <&vreg_l1a_0p875>; + + status =3D "okay"; +}; + +&usb_2 { + status =3D "okay"; +}; + +&usb_2_dwc3 { + dr_mode =3D "host"; +}; + +&usb_2_hsphy { + vdd-supply =3D <&vreg_l1a_0p875>; + vdda-pll-supply =3D <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply =3D <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value =3D <8>; + qcom,hstx-trim-value =3D ; + + status =3D "okay"; +}; + +&usb_2_qmpphy { + vdda-phy-supply =3D <&vreg_l26a_1p2>; + vdda-pll-supply =3D <&vreg_l1a_0p875>; + + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l20a_2p95>; + vcc-max-microamp =3D <800000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1a_0p875>; + vdda-pll-supply =3D <&vreg_l26a_1p2>; + + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/a= rm64/boot/dts/qcom/sdm845-google-crosshatch.dts new file mode 100644 index 0000000000000..dc9938ffc0ab8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sdm845-google-common.dtsi" + +/ { + model =3D "Google Pixel 3 XL"; + compatible =3D "google,crosshatch", "qcom,sdm845"; + + battery: battery { + compatible =3D "simple-battery"; + + charge-full-design-microamp-hours =3D <3480000>; + voltage-min-design-microvolt =3D <3600000>; + voltage-max-design-microvolt =3D <4400000>; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* for u-boot */ + framebuffer: framebuffer@9d400000 { + compatible =3D "simple-framebuffer"; + reg =3D <0 0x9d400000 0 (2960 * 1440 * 4)>; + width =3D <1440>; + height =3D <2960>; + stride =3D <(1440 * 4)>; + format =3D "a8r8g8b8"; + }; + }; + + reserved-memory { + framebuffer_region@9d400000 { + no-map; + reg =3D <0 0x9d400000 0 0x02400000>; + }; + }; +}; + +&gmu { + status =3D "okay"; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vdda_mipi_dsi0_1p2>; + + status =3D "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint =3D <&panel_in>; + data-lanes =3D <0 1 2 3>; + qcom,te-source =3D "mdp_vsync_e"; + }; + }; + }; + + panel@0 { + compatible =3D "samsung,s6e3ha8"; + reg =3D <0>; + + vci-supply =3D <&vreg_l28a_3p0>; // downstream + vdd3-supply =3D <&vreg_l28a_3p0>; + vddr-supply =3D <&vreg_l14a_1p88>; + + reset-gpios =3D <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&panel_reset_pins &panel_te_pin &se8_spiflash &panel_pmgp= io_pins>; + + port { + panel_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&panel_in>; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vdda_mipi_dsi0_pll>; + + status =3D "okay"; +}; + +&pm8998_gpios { + panel_pmgpio_pins: panel-pmgpio-active-state { + pins =3D "gpio2", "gpio5"; + function =3D "normal"; + input-enable; + bias-disable; + power-source =3D <0>; + }; +}; + +&tlmm { + se8_spiflash: se8-spiflash-state { + pins =3D "gpio65", "gpio66", "gpio67", "gpio68"; + function =3D "gpio"; + input-enable; + bias-disable; + }; + + panel_te_pin: panel-te-state { + pins =3D "gpio12"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + panel_reset_pins: panel-active-state { + pins =3D "gpio6"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + panel_suspend: panel-suspend-state { + pins =3D "gpio6"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + +}; --=20 2.51.0