From nobody Wed Dec 17 19:36:06 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A6422BE62D for ; Fri, 3 Oct 2025 16:05:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759507550; cv=none; b=e/46qhFgku+gbMvr/PN7CcbNffN4CyzfAKypWX4/tlMOmRn/9a73rylKcc5U+BlBZ5N4UUyWTTrSZlVTaX18MtyDq1QZsjc1uWLb9dRj3YyLLjFP0zGmZP4zSslPt2F+m5N2uFZZkTTbiM8N65mD8j/BqyBH6g+xobODJRn2YX8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759507550; c=relaxed/simple; bh=CkPAdLrlVh/ddleMtae0Bm+6tKcqVayNFDzb9Me1BGQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KVT6CpJf6NpByv+eTjInJLGXYJMs5OtQ1nbKtIMnAyWxKons5R21M02pL9oWNOJE3dQQHmqJOF7V+QSaT/lCLdrW6HJMCVXs43Bv9ak1IT/FAW9yGaGR7S+auUdFjKTi/bPS8eYtfyxDTRUA+pBeyzM0mJhqtZtTLCR9xxL8uOA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=gN8Ry56Y; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="gN8Ry56Y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1759507547; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ELkbprrf23tmXGdQAfZaq2jr7uQN2PDNYwdGVW1XlsQ=; b=gN8Ry56YYrV2tLB75nsN7KhaLGbueaSshmOeBWQU+HFo/iB5Isyq7tpCWawc+SGqLcSeSN WDqXk0gM1cB2MplY1q0yicRgdxme0VRxs86od4mzFo0vsBup8Vfjazmay+sK07miCbG3NI Uy2hj3ZlTT3ihR83OrEfYoTktY8eeWk= Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-467-jVL1QGJKO9mPod_L3kTvhA-1; Fri, 03 Oct 2025 12:05:44 -0400 X-MC-Unique: jVL1QGJKO9mPod_L3kTvhA-1 X-Mimecast-MFC-AGG-ID: jVL1QGJKO9mPod_L3kTvhA_1759507543 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 49B36180057B; Fri, 3 Oct 2025 16:05:43 +0000 (UTC) Received: from thinkpad-p1.localdomain.com (unknown [10.22.65.162]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id DFEF719560B1; Fri, 3 Oct 2025 16:05:40 +0000 (UTC) From: Radu Rendec To: Thomas Gleixner , Manivannan Sadhasivam Cc: Bjorn Helgaas , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Lorenzo Pieralisi , Jingoo Han , Brian Masney , Eric Chanudet , Alessandro Carminati , Jared Kangas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] PCI: dwc: Enable MSI affinity support Date: Fri, 3 Oct 2025 12:04:21 -0400 Message-ID: <20251003160421.951448-4-rrendec@redhat.com> In-Reply-To: <20251003160421.951448-1-rrendec@redhat.com> References: <20251003160421.951448-1-rrendec@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Leverage the interrupt redirection infrastructure to enable CPU affinity support for MSI interrupts. Since the parent interrupt affinity cannot be changed, affinity control for the child interrupt (MSI) is achieved by redirecting the handler to run in IRQ work context on the target CPU. This patch was originally prepared by Thomas Gleixner (see Link tag below) in a patch series that was never submitted as is, and only parts of that series have made it upstream so far. Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/ Co-developed-by: Radu Rendec Signed-off-by: Radu Rendec --- .../pci/controller/dwc/pcie-designware-host.c | 27 +++++++++++++++---- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 3ee6a464726ec..a3d4b423a2ab9 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -24,9 +24,21 @@ static struct pci_ops dw_pcie_ops; static struct pci_ops dw_child_pcie_ops; =20 +static void dw_pcie_msi_ack(struct irq_data *d) { } + +static bool dw_pcie_init_dev_msi_info(struct device *dev, struct irq_domai= n *domain, + struct irq_domain *real_parent, struct msi_domain_info *info) +{ + if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) + return false; + + info->chip->irq_ack =3D dw_pcie_msi_ack; + info->chip->irq_pre_redirect =3D irq_chip_pre_redirect_parent; + return true; +} + #define DW_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ MSI_FLAG_USE_DEF_CHIP_OPS | \ - MSI_FLAG_NO_AFFINITY | \ MSI_FLAG_PCI_MSI_MASK_PARENT) #define DW_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \ MSI_FLAG_PCI_MSIX | \ @@ -36,9 +48,8 @@ static const struct msi_parent_ops dw_pcie_msi_parent_ops= =3D { .required_flags =3D DW_PCIE_MSI_FLAGS_REQUIRED, .supported_flags =3D DW_PCIE_MSI_FLAGS_SUPPORTED, .bus_select_token =3D DOMAIN_BUS_PCI_MSI, - .chip_flags =3D MSI_CHIP_FLAG_SET_ACK, .prefix =3D "DW-", - .init_dev_msi_info =3D msi_lib_init_dev_msi_info, + .init_dev_msi_info =3D dw_pcie_init_dev_msi_info, }; =20 /* MSI int handler */ @@ -59,7 +70,7 @@ void dw_handle_msi_irq(struct dw_pcie_rp *pp) continue; =20 for_each_set_bit(pos, &status, MAX_MSI_IRQS_PER_CTRL) - generic_handle_domain_irq(pp->irq_domain, irq_off + pos); + generic_handle_demux_domain_irq(pp->irq_domain, irq_off + pos); } } =20 @@ -121,7 +132,9 @@ static void dw_pci_bottom_unmask(struct irq_data *d) dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); } =20 -static void dw_pci_bottom_ack(struct irq_data *d) +static void dw_pci_bottom_ack(struct irq_data *d) { } + +static void dw_pci_pre_redirect(struct irq_data *d) { struct dw_pcie_rp *pp =3D irq_data_get_irq_chip_data(d); struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -140,6 +153,10 @@ static struct irq_chip dw_pci_msi_bottom_irq_chip =3D { .irq_compose_msi_msg =3D dw_pci_setup_msi_msg, .irq_mask =3D dw_pci_bottom_mask, .irq_unmask =3D dw_pci_bottom_unmask, +#ifdef CONFIG_SMP + .irq_pre_redirect =3D dw_pci_pre_redirect, + .irq_set_affinity =3D irq_chip_redirect_set_affinity, +#endif }; =20 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned in= t virq, --=20 2.51.0