From nobody Wed Dec 17 17:41:33 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C48D29E0E1 for ; Fri, 3 Oct 2025 16:05:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759507537; cv=none; b=BMEJzI2OBHddc4Xt6brK4ZDaCjoN4Zg4LNVXYdUguyi6AdTdJI0ShaNnHvUAXqlo+ToV43UZrwsdkeS1LlILSoRwgB+jJJ50GOoGv8WN2xSGe3RKUKcZlwme11GSaBHgBy7bETYo/sV6GS+HMODFoIN+12UNmHYIXL5X8GOa3uw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759507537; c=relaxed/simple; bh=OZKunv1tIHzpqPoiz9m6ygYSyPW+Jg8v11KwTcSxIqs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TcZ8XwU08DUv771KT96Q4dYSrwTfex8+PoGlyDjnzW7iFnpx8pwY/4O3nfuIINoCTThbSVuME5hA5q7oH2iS7LTaPVc0srzVSGCv12FUD5VCiKehKaqBuYUkwNHQsiD9wpvvEZQ2SRna7YrJASTtq+3TTJAvcQnvifyBq7bD7Ls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=abfA0u6s; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="abfA0u6s" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1759507534; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Os0h+26zOa6FygXd+7tqf0CEJj+d2pk6Ugjq5+xQSmQ=; b=abfA0u6sG56TlRdrnuPZqte4fpnXP5UdvpsPxGbzVpb82x6W+rW/nwI2RMATJ7w8UnE8T+ 1A7si49fgRHsGE/MtAVmqvlPHm7odm0oGpGkf4YldlfODHTHrBqOPeu5ZLximzuog2gUnF aJ5pUwv87pj55rOZU6q9GyRcs7XzfVg= Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-358-PezpInW-Pxyk9QgUM3Mm3A-1; Fri, 03 Oct 2025 12:05:30 -0400 X-MC-Unique: PezpInW-Pxyk9QgUM3Mm3A-1 X-Mimecast-MFC-AGG-ID: PezpInW-Pxyk9QgUM3Mm3A_1759507529 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 532C31800378; Fri, 3 Oct 2025 16:05:29 +0000 (UTC) Received: from thinkpad-p1.localdomain.com (unknown [10.22.65.162]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id C80AC19560B1; Fri, 3 Oct 2025 16:05:26 +0000 (UTC) From: Radu Rendec To: Thomas Gleixner , Manivannan Sadhasivam Cc: Bjorn Helgaas , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Lorenzo Pieralisi , Jingoo Han , Brian Masney , Eric Chanudet , Alessandro Carminati , Jared Kangas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] genirq: Add interrupt redirection infrastructure Date: Fri, 3 Oct 2025 12:04:19 -0400 Message-ID: <20251003160421.951448-2-rrendec@redhat.com> In-Reply-To: <20251003160421.951448-1-rrendec@redhat.com> References: <20251003160421.951448-1-rrendec@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Add infrastructure to redirect interrupt handler execution to a different CPU when the current CPU is not part of the interrupt's CPU affinity mask. This is primarily aimed at (de)multiplexed interrupts, where the child interrupt handler runs in the context of the parent interrupt handler, and therefore CPU affinity control for the child interrupt is typically not available. With the new infrastructure, the child interrupt is allowed to freely change its affinity setting, independently of the parent. If the interrupt handler happens to be triggered on an "incompatible" CPU (a CPU that's not part of the child interrupt's affinity mask), the handler is redirected and runs in IRQ work context on a "compatible" CPU. No functional change is being made to any existing irqchip driver, and irqchip drivers must be explicitly modified to use the newly added infrastructure to support interrupt redirection. This is a direct follow up to the patches that Thomas Gleixner proposed in https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/ Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/ Co-developed-by: Radu Rendec Signed-off-by: Radu Rendec --- include/linux/irq.h | 6 +++++ include/linux/irqdesc.h | 11 ++++++++- kernel/irq/chip.c | 20 ++++++++++++++++ kernel/irq/irqdesc.c | 51 +++++++++++++++++++++++++++++++++++++++-- kernel/irq/manage.c | 16 +++++++++++-- 5 files changed, 99 insertions(+), 5 deletions(-) diff --git a/include/linux/irq.h b/include/linux/irq.h index c67e76fbcc077..484d4aed08084 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -459,6 +459,8 @@ static inline irq_hw_number_t irqd_to_hwirq(struct irq_= data *d) * checks against the supplied affinity mask are not * required. This is used for CPU hotplug where the * target CPU is not yet set in the cpu_online_mask. + * @irq_pre_redirect: Optional function to be invoked before redirecting + * an interrupt via irq_work. * @irq_retrigger: resend an IRQ to the CPU * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ * @irq_set_wake: enable/disable power-management wake-on of an IRQ @@ -503,6 +505,7 @@ struct irq_chip { void (*irq_eoi)(struct irq_data *data); =20 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *des= t, bool force); + void (*irq_pre_redirect)(struct irq_data *data); int (*irq_retrigger)(struct irq_data *data); int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); int (*irq_set_wake)(struct irq_data *data, unsigned int on); @@ -690,6 +693,9 @@ extern int irq_chip_request_resources_parent(struct irq= _data *data); extern void irq_chip_release_resources_parent(struct irq_data *data); #endif =20 +int irq_chip_redirect_set_affinity(struct irq_data *data, const struct cpu= mask *dest, bool force); +void irq_chip_pre_redirect_parent(struct irq_data *data); + /* Disable or mask interrupts during a kernel kexec */ extern void machine_kexec_mask_interrupts(void); =20 diff --git a/include/linux/irqdesc.h b/include/linux/irqdesc.h index fd091c35d5721..aeead91884668 100644 --- a/include/linux/irqdesc.h +++ b/include/linux/irqdesc.h @@ -2,9 +2,10 @@ #ifndef _LINUX_IRQDESC_H #define _LINUX_IRQDESC_H =20 -#include +#include #include #include +#include =20 /* * Core internal functions to deal with irq descriptors @@ -29,6 +30,11 @@ struct irqstat { #endif }; =20 +struct irq_redirect { + struct irq_work work; + unsigned int fallback_cpu; +}; + /** * struct irq_desc - interrupt descriptor * @irq_common_data: per irq and chip data passed down to chip functions @@ -46,6 +52,7 @@ struct irqstat { * @threads_handled: stats field for deferred spurious detection of thread= ed handlers * @threads_handled_last: comparator field for deferred spurious detection= of threaded handlers * @lock: locking for SMP + * @redirect: Facility for redirecting interrupts via irq_work * @affinity_hint: hint to user space for preferred irq affinity * @affinity_notify: context for notification of affinity changes * @pending_mask: pending rebalanced interrupts @@ -84,6 +91,7 @@ struct irq_desc { struct cpumask *percpu_enabled; const struct cpumask *percpu_affinity; #ifdef CONFIG_SMP + struct irq_redirect redirect; const struct cpumask *affinity_hint; struct irq_affinity_notify *affinity_notify; #ifdef CONFIG_GENERIC_PENDING_IRQ @@ -186,6 +194,7 @@ int generic_handle_irq_safe(unsigned int irq); int generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwir= q); int generic_handle_domain_irq_safe(struct irq_domain *domain, unsigned int= hwirq); int generic_handle_domain_nmi(struct irq_domain *domain, unsigned int hwir= q); +bool generic_handle_demux_domain_irq(struct irq_domain *domain, unsigned i= nt hwirq); #endif =20 /* Test to see if a driver has successfully requested an irq */ diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 3ffa0d80ddd19..8e74c6fc63f86 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -1215,6 +1215,26 @@ EXPORT_SYMBOL_GPL(handle_fasteoi_mask_irq); =20 #endif /* CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS */ =20 +#ifdef CONFIG_SMP + +int irq_chip_redirect_set_affinity(struct irq_data *data, const struct cpu= mask *dest, bool force) +{ + struct irq_redirect *redir =3D &irq_data_to_desc(data)->redirect; + + WRITE_ONCE(redir->fallback_cpu, cpumask_first(dest)); + return IRQ_SET_MASK_OK; +} +EXPORT_SYMBOL_GPL(irq_chip_redirect_set_affinity); + +void irq_chip_pre_redirect_parent(struct irq_data *data) +{ + data =3D data->parent_data; + data->chip->irq_pre_redirect(data); +} +EXPORT_SYMBOL_GPL(irq_chip_pre_redirect_parent); + +#endif + /** * irq_chip_set_parent_state - set the state of a parent interrupt. * diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index db714d3014b5f..d704025751315 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -78,8 +78,12 @@ static int alloc_masks(struct irq_desc *desc, int node) return 0; } =20 -static void desc_smp_init(struct irq_desc *desc, int node, - const struct cpumask *affinity) +static void irq_redirect_work(struct irq_work *work) +{ + handle_irq_desc(container_of(work, struct irq_desc, redirect.work)); +} + +static void desc_smp_init(struct irq_desc *desc, int node, const struct cp= umask *affinity) { if (!affinity) affinity =3D irq_default_affinity; @@ -91,6 +95,7 @@ static void desc_smp_init(struct irq_desc *desc, int node, #ifdef CONFIG_NUMA desc->irq_common_data.node =3D node; #endif + desc->redirect.work =3D IRQ_WORK_INIT_HARD(irq_redirect_work); } =20 static void free_masks(struct irq_desc *desc) @@ -766,6 +771,48 @@ int generic_handle_domain_nmi(struct irq_domain *domai= n, unsigned int hwirq) WARN_ON_ONCE(!in_nmi()); return handle_irq_desc(irq_resolve_mapping(domain, hwirq)); } + +static bool demux_redirect_remote(struct irq_desc *desc) +{ +#ifdef CONFIG_SMP + const struct cpumask *m =3D irq_data_get_effective_affinity_mask(&desc->i= rq_data); + unsigned int target_cpu =3D READ_ONCE(desc->redirect.fallback_cpu); + + if (!cpumask_test_cpu(smp_processor_id(), m)) { + /* Protect against shutdown */ + if (desc->action) + irq_work_queue_on(&desc->redirect.work, target_cpu); + return true; + } +#endif + return false; +} + +/** + * generic_handle_demux_domain_irq - Invoke the handler for a hardware int= errupt + * of a demultiplexing domain. + * @domain: The domain where to perform the lookup + * @hwirq: The hardware interrupt number to convert to a logical one + * + * Returns: True on success, or false if lookup has failed + */ +bool generic_handle_demux_domain_irq(struct irq_domain *domain, unsigned i= nt hwirq) +{ + struct irq_desc *desc =3D irq_resolve_mapping(domain, hwirq); + + if (unlikely(!desc)) + return false; + + scoped_guard(raw_spinlock, &desc->lock) { + if (desc->irq_data.chip->irq_pre_redirect) + desc->irq_data.chip->irq_pre_redirect(&desc->irq_data); + if (demux_redirect_remote(desc)) + return true; + } + return !handle_irq_desc(desc); +} +EXPORT_SYMBOL_GPL(generic_handle_demux_domain_irq); + #endif =20 /* Dynamic interrupt handling */ diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index c94837382037e..ed8f8b2667b0b 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -35,6 +35,16 @@ static int __init setup_forced_irqthreads(char *arg) early_param("threadirqs", setup_forced_irqthreads); #endif =20 +#ifdef CONFIG_SMP +static inline void synchronize_irqwork(struct irq_desc *desc) +{ + /* Synchronize pending or on the fly redirect work */ + irq_work_sync(&desc->redirect.work); +} +#else +static inline void synchronize_irqwork(struct irq_desc *desc) { } +#endif + static int __irq_get_irqchip_state(struct irq_data *d, enum irqchip_irq_st= ate which, bool *state); =20 static void __synchronize_hardirq(struct irq_desc *desc, bool sync_chip) @@ -43,6 +53,8 @@ static void __synchronize_hardirq(struct irq_desc *desc, = bool sync_chip) bool inprogress; =20 do { + synchronize_irqwork(desc); + /* * Wait until we're out of the critical section. This might * give the wrong answer due to the lack of memory barriers. @@ -108,6 +120,7 @@ EXPORT_SYMBOL(synchronize_hardirq); static void __synchronize_irq(struct irq_desc *desc) { __synchronize_hardirq(desc, true); + /* * We made sure that no hardirq handler is running. Now verify that no * threaded handlers are active. @@ -217,8 +230,7 @@ static inline void irq_validate_effective_affinity(stru= ct irq_data *data) { } =20 static DEFINE_PER_CPU(struct cpumask, __tmp_mask); =20 -int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, - bool force) +int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask,= bool force) { struct cpumask *tmp_mask =3D this_cpu_ptr(&__tmp_mask); struct irq_desc *desc =3D irq_data_to_desc(data); --=20 2.51.0 From nobody Wed Dec 17 17:41:33 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9161229E11A for ; Fri, 3 Oct 2025 16:05:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759507546; cv=none; b=oPeuhw/LmUE11KC0Ovq0pzLrsccpS/D3OauQ7vLi226qB5Zk7wbyaL/jOgIit3nCxSt3pExY/bjGWSpZE1ODi0HvgO5md5enZKXI2UOOqggUDgAChT5IkdBy9BnDQ690FXDy6u8/vv579+OmaQB0ZNOMugtjYhVSmDp9gH0GYz8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759507546; c=relaxed/simple; bh=CyoLDznRn2p8HKqvr83X+kbuXWFFK/LXspTU9qFcULA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZWWgP39Cbsba1AoqhTmATSV8xKgVgkv7qgG1KyetLQmfd1KOIm1+eGfgpbVZVkDLFIxpWyUIBwHcTBKp4pQ0I9v0bNrBwVC8RYFWZP72In9mqOp7be7+UEIfr3m2wHm+fArxhA3w41VMsSxzP0XyFUw+XyVOKSsAHrGmQcRVfLk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=W1E/4oUl; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="W1E/4oUl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1759507543; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fHGW+D+vGYzhHNu1jkYUMa7q0ra1gNLOZtOuho9SWJ8=; b=W1E/4oUlg1k+kV0ejeDAw7hzTIkGM6Yeks/2X4PujaEgNVcdhkh6DGtUFYsPtceNXrzuco qhyMOtf1HSa+HxeYyJ1mobe0kfhuKVbb2Be33jkOfNufy4woQxWWq69um+eUzTSSE4RXgI lMrVX6D5vxanxl0wouavLTT+yOgH788= Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-266-ygVw2LI9MFaMmwWfONZqvg-1; Fri, 03 Oct 2025 12:05:39 -0400 X-MC-Unique: ygVw2LI9MFaMmwWfONZqvg-1 X-Mimecast-MFC-AGG-ID: ygVw2LI9MFaMmwWfONZqvg_1759507538 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 1050C180029B; Fri, 3 Oct 2025 16:05:38 +0000 (UTC) Received: from thinkpad-p1.localdomain.com (unknown [10.22.65.162]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 73BF519560B1; Fri, 3 Oct 2025 16:05:35 +0000 (UTC) From: Radu Rendec To: Thomas Gleixner , Manivannan Sadhasivam Cc: Bjorn Helgaas , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Lorenzo Pieralisi , Jingoo Han , Brian Masney , Eric Chanudet , Alessandro Carminati , Jared Kangas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] PCI: dwc: Code cleanup Date: Fri, 3 Oct 2025 12:04:20 -0400 Message-ID: <20251003160421.951448-3-rrendec@redhat.com> In-Reply-To: <20251003160421.951448-1-rrendec@redhat.com> References: <20251003160421.951448-1-rrendec@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Code cleanup with no functional changes. These changes were originally made by Thomas Gleixner (see Link tag below) in a patch that was never submitted as is. Other parts of that patch were eventually submitted as commit 8e717112caf3 ("PCI: dwc: Switch to msi_create_parent_irq_domain()") and the remaining parts are the code cleanup changes in this patch. Summary of changes: - Use guard()/scoped_guard() instead of open-coded lock/unlock. - Return void in a few functions whose return value is never used. - Simplify dw_handle_msi_irq() by using for_each_set_bit(). One notable deviation from the original patch is that I reverted back to a simple 1 by 1 iteration over the controllers inside dw_handle_msi_irq. The reason is that with the original changes, the IRQ offset was calculated incorrectly. This patch also prepares the ground for the next patch in the series, which enables MSI affinity support, and was originally part of that same series that Thomas Gleixner prepared. Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/ Co-developed-by: Radu Rendec Signed-off-by: Radu Rendec --- .../pci/controller/dwc/pcie-designware-host.c | 98 ++++++------------- drivers/pci/controller/dwc/pcie-designware.h | 7 +- 2 files changed, 34 insertions(+), 71 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 952f8594b5012..3ee6a464726ec 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -42,35 +42,25 @@ static const struct msi_parent_ops dw_pcie_msi_parent_o= ps =3D { }; =20 /* MSI int handler */ -irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) +void dw_handle_msi_irq(struct dw_pcie_rp *pp) { - int i, pos; - unsigned long val; - u32 status, num_ctrls; - irqreturn_t ret =3D IRQ_NONE; struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + unsigned int i, num_ctrls; =20 num_ctrls =3D pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; =20 for (i =3D 0; i < num_ctrls; i++) { - status =3D dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + - (i * MSI_REG_CTRL_BLOCK_SIZE)); + unsigned int reg_off =3D i * MSI_REG_CTRL_BLOCK_SIZE; + unsigned int irq_off =3D i * MAX_MSI_IRQS_PER_CTRL; + unsigned long status, pos; + + status =3D dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + reg_off); if (!status) continue; =20 - ret =3D IRQ_HANDLED; - val =3D status; - pos =3D 0; - while ((pos =3D find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, - pos)) !=3D MAX_MSI_IRQS_PER_CTRL) { - generic_handle_domain_irq(pp->irq_domain, - (i * MAX_MSI_IRQS_PER_CTRL) + - pos); - pos++; - } + for_each_set_bit(pos, &status, MAX_MSI_IRQS_PER_CTRL) + generic_handle_domain_irq(pp->irq_domain, irq_off + pos); } - - return ret; } =20 /* Chained MSI interrupt service routine */ @@ -91,13 +81,10 @@ static void dw_pci_setup_msi_msg(struct irq_data *d, st= ruct msi_msg *msg) { struct dw_pcie_rp *pp =3D irq_data_get_irq_chip_data(d); struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - u64 msi_target; - - msi_target =3D (u64)pp->msi_data; + u64 msi_target =3D (u64)pp->msi_data; =20 msg->address_lo =3D lower_32_bits(msi_target); msg->address_hi =3D upper_32_bits(msi_target); - msg->data =3D d->hwirq; =20 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", @@ -109,18 +96,14 @@ static void dw_pci_bottom_mask(struct irq_data *d) struct dw_pcie_rp *pp =3D irq_data_get_irq_chip_data(d); struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); unsigned int res, bit, ctrl; - unsigned long flags; - - raw_spin_lock_irqsave(&pp->lock, flags); =20 + guard(raw_spinlock)(&pp->lock); ctrl =3D d->hwirq / MAX_MSI_IRQS_PER_CTRL; res =3D ctrl * MSI_REG_CTRL_BLOCK_SIZE; bit =3D d->hwirq % MAX_MSI_IRQS_PER_CTRL; =20 pp->irq_mask[ctrl] |=3D BIT(bit); dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); - - raw_spin_unlock_irqrestore(&pp->lock, flags); } =20 static void dw_pci_bottom_unmask(struct irq_data *d) @@ -128,18 +111,14 @@ static void dw_pci_bottom_unmask(struct irq_data *d) struct dw_pcie_rp *pp =3D irq_data_get_irq_chip_data(d); struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); unsigned int res, bit, ctrl; - unsigned long flags; - - raw_spin_lock_irqsave(&pp->lock, flags); =20 + guard(raw_spinlock)(&pp->lock); ctrl =3D d->hwirq / MAX_MSI_IRQS_PER_CTRL; res =3D ctrl * MSI_REG_CTRL_BLOCK_SIZE; bit =3D d->hwirq % MAX_MSI_IRQS_PER_CTRL; =20 pp->irq_mask[ctrl] &=3D ~BIT(bit); dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); - - raw_spin_unlock_irqrestore(&pp->lock, flags); } =20 static void dw_pci_bottom_ack(struct irq_data *d) @@ -156,54 +135,42 @@ static void dw_pci_bottom_ack(struct irq_data *d) } =20 static struct irq_chip dw_pci_msi_bottom_irq_chip =3D { - .name =3D "DWPCI-MSI", - .irq_ack =3D dw_pci_bottom_ack, - .irq_compose_msi_msg =3D dw_pci_setup_msi_msg, - .irq_mask =3D dw_pci_bottom_mask, - .irq_unmask =3D dw_pci_bottom_unmask, + .name =3D "DWPCI-MSI", + .irq_ack =3D dw_pci_bottom_ack, + .irq_compose_msi_msg =3D dw_pci_setup_msi_msg, + .irq_mask =3D dw_pci_bottom_mask, + .irq_unmask =3D dw_pci_bottom_unmask, }; =20 -static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, - unsigned int virq, unsigned int nr_irqs, - void *args) +static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned in= t virq, + unsigned int nr_irqs, void *args) { struct dw_pcie_rp *pp =3D domain->host_data; - unsigned long flags; - u32 i; int bit; =20 - raw_spin_lock_irqsave(&pp->lock, flags); - - bit =3D bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, - order_base_2(nr_irqs)); - - raw_spin_unlock_irqrestore(&pp->lock, flags); + scoped_guard (raw_spinlock_irq, &pp->lock) { + bit =3D bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors, + order_base_2(nr_irqs)); + } =20 if (bit < 0) return -ENOSPC; =20 - for (i =3D 0; i < nr_irqs; i++) - irq_domain_set_info(domain, virq + i, bit + i, - pp->msi_irq_chip, - pp, handle_edge_irq, - NULL, NULL); - + for (unsigned int i =3D 0; i < nr_irqs; i++) { + irq_domain_set_info(domain, virq + i, bit + i, pp->msi_irq_chip, + pp, handle_edge_irq, NULL, NULL); + } return 0; } =20 -static void dw_pcie_irq_domain_free(struct irq_domain *domain, - unsigned int virq, unsigned int nr_irqs) +static void dw_pcie_irq_domain_free(struct irq_domain *domain, unsigned in= t virq, + unsigned int nr_irqs) { struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); struct dw_pcie_rp *pp =3D domain->host_data; - unsigned long flags; - - raw_spin_lock_irqsave(&pp->lock, flags); =20 - bitmap_release_region(pp->msi_irq_in_use, d->hwirq, - order_base_2(nr_irqs)); - - raw_spin_unlock_irqrestore(&pp->lock, flags); + guard(raw_spinlock_irq)(&pp->lock); + bitmap_release_region(pp->msi_irq_in_use, d->hwirq, order_base_2(nr_irqs)= ); } =20 static const struct irq_domain_ops dw_pcie_msi_domain_ops =3D { @@ -236,8 +203,7 @@ void dw_pcie_free_msi(struct dw_pcie_rp *pp) =20 for (ctrl =3D 0; ctrl < MAX_MSI_CTRLS; ctrl++) { if (pp->msi_irq[ctrl] > 0) - irq_set_chained_handler_and_data(pp->msi_irq[ctrl], - NULL, NULL); + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], NULL, NULL); } =20 irq_domain_remove(pp->irq_domain); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 00f52d472dcdd..226aac41836bc 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -753,7 +753,7 @@ static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(stru= ct dw_pcie *pci) #ifdef CONFIG_PCIE_DW_HOST int dw_pcie_suspend_noirq(struct dw_pcie *pci); int dw_pcie_resume_noirq(struct dw_pcie *pci); -irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); +void dw_handle_msi_irq(struct dw_pcie_rp *pp); void dw_pcie_msi_init(struct dw_pcie_rp *pp); int dw_pcie_msi_host_init(struct dw_pcie_rp *pp); void dw_pcie_free_msi(struct dw_pcie_rp *pp); @@ -774,10 +774,7 @@ static inline int dw_pcie_resume_noirq(struct dw_pcie = *pci) return 0; } =20 -static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) -{ - return IRQ_NONE; -} +static inline void dw_handle_msi_irq(struct dw_pcie_rp *pp) { } =20 static inline void dw_pcie_msi_init(struct dw_pcie_rp *pp) { } --=20 2.51.0 From nobody Wed Dec 17 17:41:33 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A6422BE62D for ; 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Fri, 03 Oct 2025 12:05:44 -0400 X-MC-Unique: jVL1QGJKO9mPod_L3kTvhA-1 X-Mimecast-MFC-AGG-ID: jVL1QGJKO9mPod_L3kTvhA_1759507543 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 49B36180057B; Fri, 3 Oct 2025 16:05:43 +0000 (UTC) Received: from thinkpad-p1.localdomain.com (unknown [10.22.65.162]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id DFEF719560B1; Fri, 3 Oct 2025 16:05:40 +0000 (UTC) From: Radu Rendec To: Thomas Gleixner , Manivannan Sadhasivam Cc: Bjorn Helgaas , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Lorenzo Pieralisi , Jingoo Han , Brian Masney , Eric Chanudet , Alessandro Carminati , Jared Kangas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] PCI: dwc: Enable MSI affinity support Date: Fri, 3 Oct 2025 12:04:21 -0400 Message-ID: <20251003160421.951448-4-rrendec@redhat.com> In-Reply-To: <20251003160421.951448-1-rrendec@redhat.com> References: <20251003160421.951448-1-rrendec@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Leverage the interrupt redirection infrastructure to enable CPU affinity support for MSI interrupts. Since the parent interrupt affinity cannot be changed, affinity control for the child interrupt (MSI) is achieved by redirecting the handler to run in IRQ work context on the target CPU. This patch was originally prepared by Thomas Gleixner (see Link tag below) in a patch series that was never submitted as is, and only parts of that series have made it upstream so far. Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/linux-pci/878qpg4o4t.ffs@tglx/ Co-developed-by: Radu Rendec Signed-off-by: Radu Rendec --- .../pci/controller/dwc/pcie-designware-host.c | 27 +++++++++++++++---- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 3ee6a464726ec..a3d4b423a2ab9 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -24,9 +24,21 @@ static struct pci_ops dw_pcie_ops; static struct pci_ops dw_child_pcie_ops; =20 +static void dw_pcie_msi_ack(struct irq_data *d) { } + +static bool dw_pcie_init_dev_msi_info(struct device *dev, struct irq_domai= n *domain, + struct irq_domain *real_parent, struct msi_domain_info *info) +{ + if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) + return false; + + info->chip->irq_ack =3D dw_pcie_msi_ack; + info->chip->irq_pre_redirect =3D irq_chip_pre_redirect_parent; + return true; +} + #define DW_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ MSI_FLAG_USE_DEF_CHIP_OPS | \ - MSI_FLAG_NO_AFFINITY | \ MSI_FLAG_PCI_MSI_MASK_PARENT) #define DW_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \ MSI_FLAG_PCI_MSIX | \ @@ -36,9 +48,8 @@ static const struct msi_parent_ops dw_pcie_msi_parent_ops= =3D { .required_flags =3D DW_PCIE_MSI_FLAGS_REQUIRED, .supported_flags =3D DW_PCIE_MSI_FLAGS_SUPPORTED, .bus_select_token =3D DOMAIN_BUS_PCI_MSI, - .chip_flags =3D MSI_CHIP_FLAG_SET_ACK, .prefix =3D "DW-", - .init_dev_msi_info =3D msi_lib_init_dev_msi_info, + .init_dev_msi_info =3D dw_pcie_init_dev_msi_info, }; =20 /* MSI int handler */ @@ -59,7 +70,7 @@ void dw_handle_msi_irq(struct dw_pcie_rp *pp) continue; =20 for_each_set_bit(pos, &status, MAX_MSI_IRQS_PER_CTRL) - generic_handle_domain_irq(pp->irq_domain, irq_off + pos); + generic_handle_demux_domain_irq(pp->irq_domain, irq_off + pos); } } =20 @@ -121,7 +132,9 @@ static void dw_pci_bottom_unmask(struct irq_data *d) dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); } =20 -static void dw_pci_bottom_ack(struct irq_data *d) +static void dw_pci_bottom_ack(struct irq_data *d) { } + +static void dw_pci_pre_redirect(struct irq_data *d) { struct dw_pcie_rp *pp =3D irq_data_get_irq_chip_data(d); struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -140,6 +153,10 @@ static struct irq_chip dw_pci_msi_bottom_irq_chip =3D { .irq_compose_msi_msg =3D dw_pci_setup_msi_msg, .irq_mask =3D dw_pci_bottom_mask, .irq_unmask =3D dw_pci_bottom_unmask, +#ifdef CONFIG_SMP + .irq_pre_redirect =3D dw_pci_pre_redirect, + .irq_set_affinity =3D irq_chip_redirect_set_affinity, +#endif }; =20 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned in= t virq, --=20 2.51.0