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([103.218.174.23]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3399bc02e5bsm4164019a91.0.2025.10.03.02.19.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Oct 2025 02:19:25 -0700 (PDT) From: Sudarshan Shetty To: andrzej.hajda@intel.com, neil.armstrong@linaro.org Cc: rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, tessolveupstream@gmail.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm: bridge: ti-sn65dsi83: Fix LVDS output configuration Date: Fri, 3 Oct 2025 14:49:11 +0530 Message-Id: <20251003091911.3269073-2-tessolveupstream@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251003091911.3269073-1-tessolveupstream@gmail.com> References: <20251003091911.3269073-1-tessolveupstream@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the SN65DSI83 bridge driver to improve LVDS output stability and correctness: - Program additional device registers during initialization to ensure proper LVDS configuration. - Adjust the DSI mode_flags to match the recommended settings. Both changes are based on guidance from TI SN65DSI83 experts, addressing cases where the existing driver configuration was insufficient. Signed-off-by: Sudarshan Shetty --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge= /ti-sn65dsi83.c index 033c44326552..d6a2b20be1fe 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -613,6 +613,20 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bri= dge *bridge, mode->hsync_start - mode->hdisplay); regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, mode->vsync_start - mode->vdisplay); + + regmap_write(ctx->regmap, 0x0A, 0x05); + regmap_write(ctx->regmap, 0x0D, 0x00); + regmap_write(ctx->regmap, 0x12, 0x53); + regmap_write(ctx->regmap, 0x18, 0x6f); + regmap_write(ctx->regmap, 0x19, 0x00); + regmap_write(ctx->regmap, 0x24, 0x00); + regmap_write(ctx->regmap, 0x25, 0x00); + regmap_write(ctx->regmap, 0x2c, 0x10); + regmap_write(ctx->regmap, 0x34, 0x28); + regmap_write(ctx->regmap, 0x36, 0x00); + regmap_write(ctx->regmap, 0x38, 0x00); + regmap_write(ctx->regmap, 0x3A, 0x00); + regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); =20 /* Enable PLL */ @@ -912,9 +926,7 @@ static int sn65dsi83_host_attach(struct sn65dsi83 *ctx) =20 dsi->lanes =3D dsi_lanes; dsi->format =3D MIPI_DSI_FMT_RGB888; - dsi->mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP | - MIPI_DSI_MODE_VIDEO_NO_HSA | MIPI_DSI_MODE_NO_EOT_PACKET; + dsi->mode_flags =3D MIPI_DSI_MODE_VIDEO; =20 ret =3D devm_mipi_dsi_attach(dev, dsi); if (ret < 0) { --=20 2.34.1