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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Oct 2025 06:19:20.5825 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2c50b7f-4f00-4f80-6f40-08de0244ca2e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7599 Content-Type: text/plain; charset="utf-8" Optimize AXI DMA control register programming by consolidating coalesce count and delay configuration into a single register write. Previously, the coalesce count was written separately from the delay configuration, resulting in two register writes. Combine these into one write operation to reduce bus overhead. Additionally, avoid redundant channel starts in xilinx_dma_start_transfer() and xilinx_mcdma_start_transfer() by only calling xilinx_dma_start() when the channel is actually idle. Signed-off-by: Suraj Gupta Co-developed-by: Srinivas Neeli Signed-off-by: Srinivas Neeli Tested-by: Folker Schwesinger --- drivers/dma/xilinx/xilinx_dma.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index aa6589e88c5c..a050b06e3b8d 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1561,7 +1561,6 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) reg &=3D ~XILINX_DMA_CR_COALESCE_MAX; reg |=3D chan->desc_pendingcount << XILINX_DMA_CR_COALESCE_SHIFT; - dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); } =20 if (chan->has_sg && list_empty(&chan->active_list)) @@ -1571,7 +1570,8 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) reg |=3D chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); =20 - xilinx_dma_start(chan); + if (chan->idle) + xilinx_dma_start(chan); =20 if (chan->err) return; @@ -1660,7 +1660,8 @@ static void xilinx_mcdma_start_transfer(struct xilinx= _dma_chan *chan) reg |=3D XILINX_MCDMA_CR_RUNSTOP_MASK; dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); =20 - xilinx_dma_start(chan); + if (chan->idle) + xilinx_dma_start(chan); =20 if (chan->err) return; --=20 2.25.1