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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Oct 2025 06:19:20.5160 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81568ea5-4b90-491c-37c1-08de0244ca24 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5682 Content-Type: text/plain; charset="utf-8" Remove the restrictive idle check in xilinx_dma_start_transfer() and xilinx_mcdma_start_transfer() that prevented new transfers from being queued when the channel was busy. Additionally, only update the CURDESC register when the channel is running in scatter-gather mode and active list is empty to avoid interfering with transfers already in progress. When the active list contains transfers, the hardware tail pointer extension mechanism handles chaining automatically. Signed-off-by: Suraj Gupta Co-developed-by: Srinivas Neeli Signed-off-by: Srinivas Neeli Tested-by: Folker Schwesinger --- drivers/dma/xilinx/xilinx_dma.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 53b82ddad007..aa6589e88c5c 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1548,9 +1548,6 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) if (list_empty(&chan->pending_list)) return; =20 - if (!chan->idle) - return; - head_desc =3D list_first_entry(&chan->pending_list, struct xilinx_dma_tx_descriptor, node); tail_desc =3D list_last_entry(&chan->pending_list, @@ -1567,7 +1564,7 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); } =20 - if (chan->has_sg) + if (chan->has_sg && list_empty(&chan->active_list)) xilinx_write(chan, XILINX_DMA_REG_CURDESC, head_desc->async_tx.phys); reg &=3D ~XILINX_DMA_CR_DELAY_MAX; @@ -1627,9 +1624,6 @@ static void xilinx_mcdma_start_transfer(struct xilinx= _dma_chan *chan) if (chan->err) return; =20 - if (!chan->idle) - return; - if (list_empty(&chan->pending_list)) return; =20 @@ -1652,8 +1646,9 @@ static void xilinx_mcdma_start_transfer(struct xilinx= _dma_chan *chan) dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); =20 /* Program current descriptor */ - xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), - head_desc->async_tx.phys); + if (chan->has_sg && list_empty(&chan->active_list)) + xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), + head_desc->async_tx.phys); =20 /* Program channel enable register */ reg =3D dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET); --=20 2.25.1