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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Oct 2025 06:19:16.0686 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05928459-12d8-4b1a-a3eb-08de0244c77d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9728 Content-Type: text/plain; charset="utf-8" Fix a race condition in AXIDMA and MCDMA irq handlers where the channel could be incorrectly marked as idle and attempt spurious transfers when descriptors are still being processed. The issue occurs when: 1. Multiple descriptors are queued and active. 2. An interrupt fires after completing some descriptors. 3. xilinx_dma_complete_descriptor() moves completed descriptors to done_list. 4. Channel is marked idle and start_transfer() is called even though active_list still contains unprocessed descriptors. 5. This leads to premature transfer attempts and potential descriptor corruption or missed completions. Only mark the channel as idle and start new transfers when the active list is actually empty, ensuring proper channel state management and avoiding spurious transfer attempts. Signed-off-by: Suraj Gupta Co-developed-by: Srinivas Neeli Signed-off-by: Srinivas Neeli Fixes: c0bba3a99f07 ("dmaengine: vdma: Add Support for Xilinx AXI Direct Me= mory Access Engine") Tested-by: Folker Schwesinger --- drivers/dma/xilinx/xilinx_dma.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index fabff602065f..53b82ddad007 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1857,8 +1857,10 @@ static irqreturn_t xilinx_mcdma_irq_handler(int irq,= void *data) if (status & XILINX_MCDMA_IRQ_IOC_MASK) { spin_lock(&chan->lock); xilinx_dma_complete_descriptor(chan); - chan->idle =3D true; - chan->start_transfer(chan); + if (list_empty(&chan->active_list)) { + chan->idle =3D true; + chan->start_transfer(chan); + } spin_unlock(&chan->lock); } =20 @@ -1914,8 +1916,10 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, v= oid *data) XILINX_DMA_DMASR_DLY_CNT_IRQ)) { spin_lock(&chan->lock); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Oct 2025 06:19:20.5160 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81568ea5-4b90-491c-37c1-08de0244ca24 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5682 Content-Type: text/plain; charset="utf-8" Remove the restrictive idle check in xilinx_dma_start_transfer() and xilinx_mcdma_start_transfer() that prevented new transfers from being queued when the channel was busy. Additionally, only update the CURDESC register when the channel is running in scatter-gather mode and active list is empty to avoid interfering with transfers already in progress. When the active list contains transfers, the hardware tail pointer extension mechanism handles chaining automatically. Signed-off-by: Suraj Gupta Co-developed-by: Srinivas Neeli Signed-off-by: Srinivas Neeli Tested-by: Folker Schwesinger --- drivers/dma/xilinx/xilinx_dma.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 53b82ddad007..aa6589e88c5c 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1548,9 +1548,6 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) if (list_empty(&chan->pending_list)) return; =20 - if (!chan->idle) - return; - head_desc =3D list_first_entry(&chan->pending_list, struct xilinx_dma_tx_descriptor, node); tail_desc =3D list_last_entry(&chan->pending_list, @@ -1567,7 +1564,7 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); } =20 - if (chan->has_sg) + if (chan->has_sg && list_empty(&chan->active_list)) xilinx_write(chan, XILINX_DMA_REG_CURDESC, head_desc->async_tx.phys); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Oct 2025 06:19:20.5825 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2c50b7f-4f00-4f80-6f40-08de0244ca2e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7599 Content-Type: text/plain; charset="utf-8" Optimize AXI DMA control register programming by consolidating coalesce count and delay configuration into a single register write. Previously, the coalesce count was written separately from the delay configuration, resulting in two register writes. Combine these into one write operation to reduce bus overhead. Additionally, avoid redundant channel starts in xilinx_dma_start_transfer() and xilinx_mcdma_start_transfer() by only calling xilinx_dma_start() when the channel is actually idle. Signed-off-by: Suraj Gupta Co-developed-by: Srinivas Neeli Signed-off-by: Srinivas Neeli Tested-by: Folker Schwesinger --- drivers/dma/xilinx/xilinx_dma.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index aa6589e88c5c..a050b06e3b8d 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1561,7 +1561,6 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) reg &=3D ~XILINX_DMA_CR_COALESCE_MAX; reg |=3D chan->desc_pendingcount << XILINX_DMA_CR_COALESCE_SHIFT; - dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); } =20 if (chan->has_sg && list_empty(&chan->active_list)) @@ -1571,7 +1570,8 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) reg |=3D chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); =20 - xilinx_dma_start(chan); + if (chan->idle) + xilinx_dma_start(chan); =20 if (chan->err) return; @@ -1660,7 +1660,8 @@ static void xilinx_mcdma_start_transfer(struct xilinx= _dma_chan *chan) reg |=3D XILINX_MCDMA_CR_RUNSTOP_MASK; dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); =20 - xilinx_dma_start(chan); + if (chan->idle) + xilinx_dma_start(chan); =20 if (chan->err) return; --=20 2.25.1