From nobody Wed Dec 17 19:39:43 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1123E2D660B for ; Fri, 3 Oct 2025 02:35:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759458981; cv=none; b=Xnir1U0XJ5ZQkELS8gaEEUW8kj0BWt1iB9otTROgd0LF6POTaGRsn0r9MlBzoSZLx9nPtEmrlD0XSwXoRPrxON8no7UQuWasga/W0XUZ6EMpJ9LJhKlfhJTyr8YdujVcnnEega5KeSOEQf3vTvj4cQ6jwwH8QxdFzsWMxdAod+c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759458981; c=relaxed/simple; bh=+8k0N5zfXey/PhwbJ7b5IzAzg5tujuDfGrEQCaPcweg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XmV1zy9HkClQbhywntPaz+/4Fx8NAiNNZ7DRWdWksLPu7vmZryC5v8XuC/+i/4VWy7lYsEhjda2+jEQ6xnjCpbOUU0yOZ5Ov7+OinRS+IzmaZNt77r/brgXzn4fgitgPREt2aAj6Bj5qG/1xGdZmpZwH5xxrAEaIYghx/dJwXCE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 5932Ze6Z070297 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 3 Oct 2025 10:35:40 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 3 Oct 2025 10:35:40 +0800 From: Randolph Lin To: CC: , , , , , , , , , , , , , , , , , , , , , , , Randolph Lin Subject: [PATCH v6 2/5] dt-bindings: PCI: Add Andes QiLai PCIe support Date: Fri, 3 Oct 2025 10:35:24 +0800 Message-ID: <20251003023527.3284787-3-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251003023527.3284787-1-randolph@andestech.com> References: <20251003023527.3284787-1-randolph@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 5932Ze6Z070297 Content-Type: text/plain; charset="utf-8" Add the Andes QiLai PCIe node, which includes 3 Root Complexes. Only one example is required in the DTS bindings YAML file. Signed-off-by: Randolph Lin --- .../bindings/pci/andestech,qilai-pcie.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-p= cie.yaml diff --git a/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yam= l b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml new file mode 100644 index 000000000000..419468430e7e --- /dev/null +++ b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/andestech,qilai-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes QiLai PCIe host controller + +description: + Andes QiLai PCIe host controller is based on the Synopsys DesignWare + PCI core. It shares common features with the PCIe DesignWare core and + inherits common properties defined in + Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. + +maintainers: + - Randolph Lin + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: andestech,qilai-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: APB registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: apb + - const: config + + ranges: + maxItems: 2 + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 1 + + interrupt-map: true + +required: + - reg + - reg-names + - "#interrupt-cells" + - interrupts + - interrupt-names + - interrupt-map-mask + - interrupt-map + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + bus@80000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@80000000 { + compatible =3D "andestech,qilai-pcie"; + device_type =3D "pci"; + reg =3D <0x0 0x80000000 0x0 0x20000000>, + <0x0 0x04000000 0x0 0x00001000>, + <0x0 0x00000000 0x0 0x00010000>; + reg-names =3D "dbi", "apb", "config"; + + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf00= 00000>, + <0x43000000 0x01 0x00000000 0x01 0x0000000 0x1f 0x00000= 000>; + + #interrupt-cells =3D <1>; + interrupts =3D <0xf>; + interrupt-names =3D "msi"; + interrupt-parent =3D <&plic0>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; --=20 2.34.1