From nobody Wed Dec 17 08:56:20 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 979772DAFDF; Fri, 3 Oct 2025 18:14:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759515289; cv=none; b=Gkq6tpZ86Oq134JgX9+OHvGGUdRrYUuqykfbIJkQ2b6YqnYTwbly2o5RkdjivalyWB7jBumRC9expObFeGMBJ/1X8jJWFTzVWlJ2+e5VUOhbWvk4b/HDh8P0kc/pBV1OJ87mINcaDLU/Y1ShrJzb6rOpV4L9H4wkhYMiNz6TCKc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759515289; c=relaxed/simple; bh=NJjpR537809gru4uaUWcWs1RQpcRApH8GUSWZ8RplEQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MUVzgfyUWqeUMkeeFq8+GtrLmSwgG+pPVFVoYt6mtgeqvzovlAGgnK3AMFetoaj2ocVBnuS8nGvoS5613acGDwtaWnWnUPutgmWqNclmQgOLtjfCjyME3KRXYvXX7PnGSBbHKJfsKJtbYDOFwc53UcheyhtJ/SjWecmV05kmNPg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SOEjWnat; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SOEjWnat" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2D5F2C4CEF9; Fri, 3 Oct 2025 18:14:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759515289; bh=NJjpR537809gru4uaUWcWs1RQpcRApH8GUSWZ8RplEQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SOEjWnatsv6hESw1a7uQ9eWq2oamCVaXt5F6l3kRStEloSFUx6oma93YvPrj9M7QN 8xSCNIfEYKSPAemh7Vw+pv7fjh6C9ukq7TaGpx2GE5WWpfn05Zh171W0X1DYEgZnnK KFITRuZVE40Ox7JWRy26pqkWuhfNphnp41T3KP/Xq4cHMbo7FFVTvRSoMIpndSaPO8 0d+ba4KubpmW5qmu6fMOnZq5DF1INrLB7Xb7wPJMT4qvHYZ0Owyk4CxuVcCtF7hCbn juln0489bKim7TsyHCLrhcMeiuOw7rzLI+7jahoKZJ41t864pTTgwtDXv8uO+SqSkS FsI/MPvmoPQyw== From: Konrad Dybcio Date: Fri, 03 Oct 2025 20:14:38 +0200 Subject: [PATCH v2 1/3] dt-bindings: clock: qcom,x1e80100-gcc: Add missing USB4 clocks/resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251003-topic-hamoa_gcc_usb4-v2-1-61d27a14ee65@oss.qualcomm.com> References: <20251003-topic-hamoa_gcc_usb4-v2-0-61d27a14ee65@oss.qualcomm.com> In-Reply-To: <20251003-topic-hamoa_gcc_usb4-v2-0-61d27a14ee65@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Konrad Dybcio , Wesley Cheng , Bryan O'Donoghue , Sibi Sankar , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759515280; l=7939; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=2SEYKECbMAw1/v9/+aajX73j5K02QruptY1QjzSZwBE=; b=naTwxckpKit1VGk/nXHB3hYQC41U7uzVKRKZlrliFfTdfmwZvAtvYe4MnctDtTmImzrNsDZMX 75Fw0QmhhjRCEyEF+thFk8awPhZIiS0njvaRwXQ0Nb2vaUZ67w5Hx1E X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Some of the USB4 muxes, RCGs and resets were not initially described. Add indices for them to allow extending the driver. Acked-by: Rob Herring (Arm) Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,x1e80100-gcc.yaml | 62 ++++++++++++++++++= ++-- include/dt-bindings/clock/qcom,x1e80100-gcc.h | 61 ++++++++++++++++++= +++ 2 files changed, 119 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml= b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml index 68dde0720c711320aa0e7c74040cf3c4422dda72..1b15b507095455c93b1ba39404c= afbb6f96be5a9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml @@ -32,9 +32,36 @@ properties: - description: PCIe 5 pipe clock - description: PCIe 6a pipe clock - description: PCIe 6b pipe clock - - description: USB QMP Phy 0 clock source - - description: USB QMP Phy 1 clock source - - description: USB QMP Phy 2 clock source + - description: USB4_0 QMPPHY clock source + - description: USB4_1 QMPPHY clock source + - description: USB4_2 QMPPHY clock source + - description: USB4_0 PHY DP0 GMUX clock source + - description: USB4_0 PHY DP1 GMUX clock source + - description: USB4_0 PHY PCIE PIPEGMUX clock source + - description: USB4_0 PHY PIPEGMUX clock source + - description: USB4_0 PHY SYS PCIE PIPEGMUX clock source + - description: USB4_1 PHY DP0 GMUX 2 clock source + - description: USB4_1 PHY DP1 GMUX 2 clock source + - description: USB4_1 PHY PCIE PIPEGMUX clock source + - description: USB4_1 PHY PIPEGMUX clock source + - description: USB4_1 PHY SYS PCIE PIPEGMUX clock source + - description: USB4_2 PHY DP0 GMUX 2 clock source + - description: USB4_2 PHY DP1 GMUX 2 clock source + - description: USB4_2 PHY PCIE PIPEGMUX clock source + - description: USB4_2 PHY PIPEGMUX clock source + - description: USB4_2 PHY SYS PCIE PIPEGMUX clock source + - description: USB4_0 PHY RX 0 clock source + - description: USB4_0 PHY RX 1 clock source + - description: USB4_1 PHY RX 0 clock source + - description: USB4_1 PHY RX 1 clock source + - description: USB4_2 PHY RX 0 clock source + - description: USB4_2 PHY RX 1 clock source + - description: USB4_0 PHY PCIE PIPE clock source + - description: USB4_0 PHY max PIPE clock source + - description: USB4_1 PHY PCIE PIPE clock source + - description: USB4_1 PHY max PIPE clock source + - description: USB4_2 PHY PCIE PIPE clock source + - description: USB4_2 PHY max PIPE clock source =20 power-domains: description: @@ -67,7 +94,34 @@ examples: <&pcie6b_phy>, <&usb_1_ss0_qmpphy 0>, <&usb_1_ss1_qmpphy 1>, - <&usb_1_ss2_qmpphy 2>; + <&usb_1_ss2_qmpphy 2>, + <&usb4_0_phy_dp0_gmux_clk>, + <&usb4_0_phy_dp1_gmux_clk>, + <&usb4_0_phy_pcie_pipegmux_clk>, + <&usb4_0_phy_pipegmux_clk>, + <&usb4_0_phy_sys_pcie_pipegmux_clk>, + <&usb4_1_phy_dp0_gmux_2_clk>, + <&usb4_1_phy_dp1_gmux_2_clk>, + <&usb4_1_phy_pcie_pipegmux_clk>, + <&usb4_1_phy_pipegmux_clk>, + <&usb4_1_phy_sys_pcie_pipegmux_clk>, + <&usb4_2_phy_dp0_gmux_2_clk>, + <&usb4_2_phy_dp1_gmux_2_clk>, + <&usb4_2_phy_pcie_pipegmux_clk>, + <&usb4_2_phy_pipegmux_clk>, + <&usb4_2_phy_sys_pcie_pipegmux_clk>, + <&usb4_0_phy_rx_0_clk>, + <&usb4_0_phy_rx_1_clk>, + <&usb4_1_phy_rx_0_clk>, + <&usb4_1_phy_rx_1_clk>, + <&usb4_2_phy_rx_0_clk>, + <&usb4_2_phy_rx_1_clk>, + <&usb4_0_phy_pcie_pipe_clk>, + <&usb4_0_phy_max_pipe_clk>, + <&usb4_1_phy_pcie_pipe_clk>, + <&usb4_1_phy_max_pipe_clk>, + <&usb4_2_phy_pcie_pipe_clk>, + <&usb4_2_phy_max_pipe_clk>; power-domains =3D <&rpmhpd RPMHPD_CX>; #clock-cells =3D <1>; #reset-cells =3D <1>; diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bin= dings/clock/qcom,x1e80100-gcc.h index 710c340f24a57d799ac04650fbe9d4ea0f294bde..62aa1242559270dd3bd31cd1032= 2ee265468b8e4 100644 --- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h +++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h @@ -363,6 +363,30 @@ #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353 #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354 #define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355 +#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 356 +#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 357 +#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC 358 +#define GCC_USB4_0_PHY_DP0_CLK_SRC 359 +#define GCC_USB4_0_PHY_DP1_CLK_SRC 360 +#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC 361 +#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC 362 +#define GCC_USB4_0_PHY_RX0_CLK_SRC 363 +#define GCC_USB4_0_PHY_RX1_CLK_SRC 364 +#define GCC_USB4_0_PHY_SYS_CLK_SRC 365 +#define GCC_USB4_1_PHY_DP0_CLK_SRC 366 +#define GCC_USB4_1_PHY_DP1_CLK_SRC 367 +#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 368 +#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 369 +#define GCC_USB4_1_PHY_RX0_CLK_SRC 370 +#define GCC_USB4_1_PHY_RX1_CLK_SRC 371 +#define GCC_USB4_1_PHY_SYS_CLK_SRC 372 +#define GCC_USB4_2_PHY_DP0_CLK_SRC 373 +#define GCC_USB4_2_PHY_DP1_CLK_SRC 374 +#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC 375 +#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC 376 +#define GCC_USB4_2_PHY_RX0_CLK_SRC 377 +#define GCC_USB4_2_PHY_RX1_CLK_SRC 378 +#define GCC_USB4_2_PHY_SYS_CLK_SRC 379 =20 /* GCC power domains */ #define GCC_PCIE_0_TUNNEL_GDSC 0 @@ -484,4 +508,41 @@ #define GCC_VIDEO_BCR 87 #define GCC_VIDEO_AXI0_CLK_ARES 88 #define GCC_VIDEO_AXI1_CLK_ARES 89 +#define GCC_USB4_0_MISC_USB4_SYS_BCR 90 +#define GCC_USB4_0_MISC_RX_CLK_0_BCR 91 +#define GCC_USB4_0_MISC_RX_CLK_1_BCR 92 +#define GCC_USB4_0_MISC_USB_PIPE_BCR 93 +#define GCC_USB4_0_MISC_PCIE_PIPE_BCR 94 +#define GCC_USB4_0_MISC_TMU_BCR 95 +#define GCC_USB4_0_MISC_SB_IF_BCR 96 +#define GCC_USB4_0_MISC_HIA_MSTR_BCR 97 +#define GCC_USB4_0_MISC_AHB_BCR 98 +#define GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR 99 +#define GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR 100 +#define GCC_USB4_1_MISC_USB4_SYS_BCR 101 +#define GCC_USB4_1_MISC_RX_CLK_0_BCR 102 +#define GCC_USB4_1_MISC_RX_CLK_1_BCR 103 +#define GCC_USB4_1_MISC_USB_PIPE_BCR 104 +#define GCC_USB4_1_MISC_PCIE_PIPE_BCR 105 +#define GCC_USB4_1_MISC_TMU_BCR 106 +#define GCC_USB4_1_MISC_SB_IF_BCR 107 +#define GCC_USB4_1_MISC_HIA_MSTR_BCR 108 +#define GCC_USB4_1_MISC_AHB_BCR 109 +#define GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR 110 +#define GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR 111 +#define GCC_USB4_2_MISC_USB4_SYS_BCR 112 +#define GCC_USB4_2_MISC_RX_CLK_0_BCR 113 +#define GCC_USB4_2_MISC_RX_CLK_1_BCR 114 +#define GCC_USB4_2_MISC_USB_PIPE_BCR 115 +#define GCC_USB4_2_MISC_PCIE_PIPE_BCR 116 +#define GCC_USB4_2_MISC_TMU_BCR 117 +#define GCC_USB4_2_MISC_SB_IF_BCR 118 +#define GCC_USB4_2_MISC_HIA_MSTR_BCR 119 +#define GCC_USB4_2_MISC_AHB_BCR 120 +#define GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR 121 +#define GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR 122 +#define GCC_USB4PHY_PHY_PRIM_BCR 123 +#define GCC_USB4PHY_PHY_SEC_BCR 124 +#define GCC_USB4PHY_PHY_TERT_BCR 125 + #endif --=20 2.51.0 From nobody Wed Dec 17 08:56:20 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E01BD2DF125; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MFes8YcP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A40C4C4CEF5; Fri, 3 Oct 2025 18:14:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759515293; bh=ZJl6Z4zTKGytpGVOdgWZO2i1ABAm4VCif1UcJ273pjc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MFes8YcPFtDdJt26TK5qoXoKx5+iqgodw3RAICAYsxk6R6rNEQQ6yAW4qEsVdyCJk FIE2pOGL+RqgYM11dwTkw/XXwKim4jL8H7IX/zwsjXzcgocZeKR7s3qpIcb4Eo6lnA U4JSIXZRffmWrHWV6Awt3k1a1PBiEEKhmJuUlVC0x1x+JoJ3UdzOoYtRLrxo/8GJUH Ban2gbsRRI4gZZOSccmcoG9/u6Bm2woHjoDLKSPMALrxvp4eRs9isO/KQKLoM9nQqW JOThSm7EXa7vzXaaZ2YhCX8NWtVRnSDP5RpBaQhBn3mzOf3HiJdCsKs+ZHdDPLElr3 t/hibNSE6iqDw== From: Konrad Dybcio Date: Fri, 03 Oct 2025 20:14:39 +0200 Subject: [PATCH v2 2/3] clk: qcom: gcc-x1e80100: Add missing USB4 clocks/resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251003-topic-hamoa_gcc_usb4-v2-2-61d27a14ee65@oss.qualcomm.com> References: <20251003-topic-hamoa_gcc_usb4-v2-0-61d27a14ee65@oss.qualcomm.com> In-Reply-To: <20251003-topic-hamoa_gcc_usb4-v2-0-61d27a14ee65@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Konrad Dybcio , Wesley Cheng , Bryan O'Donoghue , Sibi Sankar , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759515280; l=37967; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=liXYC9eaZiKUosI/bNGxJuxsYBvYyPoyiVaSfLsHBbI=; b=SHRKm5xAQIqoczGb36+KUlgpNa7wEOI1M/FQBrxX3ayHC5i+q6A+8pjp66qLFBnZnZmnrARo/ t/MOheIbua7AYPe94uDats678THN5BJYhIFkLyzA/boNx9lqXF7Wl63 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Currently, some of the USB4 clocks/resets are described, but not all of the back-end muxes are present. Configuring them properly is necessary for proper operation of the hardware. Add all the resets & muxes and wire up any unaccounted USB4 clock paths. Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver f= or X1E80100") Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Reviewed-by: Taniya Das --- drivers/clk/qcom/gcc-x1e80100.c | 698 ++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 681 insertions(+), 17 deletions(-) diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e8010= 0.c index 301fc9fc32d8e6e1ddf59c1d3350d84f6c06e4b6..8804ad5d70be0b7bf911f89877b= 1d847fc4d95ae 100644 --- a/drivers/clk/qcom/gcc-x1e80100.c +++ b/drivers/clk/qcom/gcc-x1e80100.c @@ -32,6 +32,33 @@ enum { DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE, DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE, DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE, + DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, + DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, + DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, + DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, + DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, + DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC, + DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC, + DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, + DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, + DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, + DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, + DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, + DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, + DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, + DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, + DT_QUSB4PHY_0_GCC_USB4_RX0_CLK, + DT_QUSB4PHY_0_GCC_USB4_RX1_CLK, + DT_QUSB4PHY_1_GCC_USB4_RX0_CLK, + DT_QUSB4PHY_1_GCC_USB4_RX1_CLK, + DT_QUSB4PHY_2_GCC_USB4_RX0_CLK, + DT_QUSB4PHY_2_GCC_USB4_RX1_CLK, + DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, + DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, + DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, + DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, + DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, + DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, }; =20 enum { @@ -42,10 +69,40 @@ enum { P_GCC_GPLL7_OUT_MAIN, P_GCC_GPLL8_OUT_MAIN, P_GCC_GPLL9_OUT_MAIN, + P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, + P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, + P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, + P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, + P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, + P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, + P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, + P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, + P_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC, + P_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC, + P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, + P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, + P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, + P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, + P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, + P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, + P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, + P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, + P_QUSB4PHY_0_GCC_USB4_RX0_CLK, + P_QUSB4PHY_0_GCC_USB4_RX1_CLK, + P_QUSB4PHY_1_GCC_USB4_RX0_CLK, + P_QUSB4PHY_1_GCC_USB4_RX1_CLK, + P_QUSB4PHY_2_GCC_USB4_RX0_CLK, + P_QUSB4PHY_2_GCC_USB4_RX1_CLK, P_SLEEP_CLK, P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, + P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, + P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, + P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, + P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, + P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, + P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, }; =20 static struct clk_alpha_pll gcc_gpll0 =3D { @@ -320,6 +377,342 @@ static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = =3D { { } }; =20 +static const struct clk_parent_data gcc_parent_data_13[] =3D { + { .index =3D DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC }, + { .index =3D DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, +}; + +static const struct clk_parent_data gcc_parent_data_14[] =3D { + { .index =3D DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC }, + { .index =3D DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, +}; + +static const struct clk_parent_data gcc_parent_data_15[] =3D { + { .index =3D DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct clk_parent_data gcc_parent_data_16[] =3D { + { .index =3D DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC }, + { .index =3D DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK }, +}; + +static const struct clk_parent_data gcc_parent_data_17[] =3D { + { .index =3D DT_QUSB4PHY_0_GCC_USB4_RX0_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct clk_parent_data gcc_parent_data_18[] =3D { + { .index =3D DT_QUSB4PHY_0_GCC_USB4_RX1_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct clk_parent_data gcc_parent_data_19[] =3D { + { .index =3D DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC }, + { .index =3D DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK }, +}; + +static const struct clk_parent_data gcc_parent_data_20[] =3D { + { .index =3D DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC }, + { .index =3D DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, +}; + +static const struct clk_parent_data gcc_parent_data_21[] =3D { + { .index =3D DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC }, + { .index =3D DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, +}; + +static const struct clk_parent_data gcc_parent_data_22[] =3D { + { .index =3D DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct clk_parent_data gcc_parent_data_23[] =3D { + { .index =3D DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC }, + { .index =3D DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, +}; + +static const struct clk_parent_data gcc_parent_data_24[] =3D { + { .index =3D DT_QUSB4PHY_1_GCC_USB4_RX0_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct clk_parent_data gcc_parent_data_25[] =3D { + { .index =3D DT_QUSB4PHY_1_GCC_USB4_RX1_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct clk_parent_data gcc_parent_data_26[] =3D { + { .index =3D DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC }, + { .index =3D DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK }, +}; + +static const struct clk_parent_data gcc_parent_data_27[] =3D { + { .index =3D DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC }, + { .index =3D DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, +}; + +static const struct clk_parent_data gcc_parent_data_28[] =3D { + { .index =3D DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC }, + { .index =3D DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, +}; + +static const struct clk_parent_data gcc_parent_data_29[] =3D { + { .index =3D DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct clk_parent_data gcc_parent_data_30[] =3D { + { .index =3D DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC }, + { .index =3D DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, +}; + +static const struct clk_parent_data gcc_parent_data_31[] =3D { + { .index =3D DT_QUSB4PHY_2_GCC_USB4_RX0_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct clk_parent_data gcc_parent_data_32[] =3D { + { .index =3D DT_QUSB4PHY_2_GCC_USB4_RX1_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct clk_parent_data gcc_parent_data_33[] =3D { + { .index =3D DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC }, + { .index =3D DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src =3D { + .reg =3D 0x9f06c, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_phy_dp0_clk_src", + .parent_data =3D gcc_parent_data_13, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp1_clk_src =3D { + .reg =3D 0x9f114, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_phy_dp1_clk_src", + .parent_data =3D gcc_parent_data_14, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_0_phy_p2rr2p_pipe_clk_src =3D { + .reg =3D 0x9f0d4, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_phy_p2rr2p_pipe_clk_src", + .parent_data =3D gcc_parent_data_15, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_0_phy_pcie_pipe_mux_clk_src =3D { + .reg =3D 0x9f104, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_phy_pcie_pipe_mux_clk_src", + .parent_data =3D gcc_parent_data_16, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx0_clk_src =3D { + .reg =3D 0x9f0ac, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_phy_rx0_clk_src", + .parent_data =3D gcc_parent_data_17, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx1_clk_src =3D { + .reg =3D 0x9f0bc, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_phy_rx1_clk_src", + .parent_data =3D gcc_parent_data_18, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_0_phy_sys_clk_src =3D { + .reg =3D 0x9f0e4, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_0_phy_sys_clk_src", + .parent_data =3D gcc_parent_data_19, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp0_clk_src =3D { + .reg =3D 0x2b06c, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_phy_dp0_clk_src", + .parent_data =3D gcc_parent_data_20, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp1_clk_src =3D { + .reg =3D 0x2b114, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_phy_dp1_clk_src", + .parent_data =3D gcc_parent_data_21, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src =3D { + .reg =3D 0x2b0d4, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_phy_p2rr2p_pipe_clk_src", + .parent_data =3D gcc_parent_data_22, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src =3D { + .reg =3D 0x2b104, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_phy_pcie_pipe_mux_clk_src", + .parent_data =3D gcc_parent_data_23, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx0_clk_src =3D { + .reg =3D 0x2b0ac, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_phy_rx0_clk_src", + .parent_data =3D gcc_parent_data_24, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx1_clk_src =3D { + .reg =3D 0x2b0bc, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_phy_rx1_clk_src", + .parent_data =3D gcc_parent_data_25, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_1_phy_sys_clk_src =3D { + .reg =3D 0x2b0e4, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_1_phy_sys_clk_src", + .parent_data =3D gcc_parent_data_26, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp0_clk_src =3D { + .reg =3D 0x1106c, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_phy_dp0_clk_src", + .parent_data =3D gcc_parent_data_27, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp1_clk_src =3D { + .reg =3D 0x11114, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_phy_dp1_clk_src", + .parent_data =3D gcc_parent_data_28, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_2_phy_p2rr2p_pipe_clk_src =3D { + .reg =3D 0x110d4, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_phy_p2rr2p_pipe_clk_src", + .parent_data =3D gcc_parent_data_29, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_2_phy_pcie_pipe_mux_clk_src =3D { + .reg =3D 0x11104, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_phy_pcie_pipe_mux_clk_src", + .parent_data =3D gcc_parent_data_30, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx0_clk_src =3D { + .reg =3D 0x110ac, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_phy_rx0_clk_src", + .parent_data =3D gcc_parent_data_31, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx1_clk_src =3D { + .reg =3D 0x110bc, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_phy_rx1_clk_src", + .parent_data =3D gcc_parent_data_32, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_usb4_2_phy_sys_clk_src =3D { + .reg =3D 0x110e4, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb4_2_phy_sys_clk_src", + .parent_data =3D gcc_parent_data_33, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + static struct clk_rcg2 gcc_gp1_clk_src =3D { .cmd_rcgr =3D 0x64004, .mnd_width =3D 16, @@ -2790,6 +3183,11 @@ static struct clk_branch gcc_pcie_0_pipe_clk =3D { .enable_mask =3D BIT(25), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_pcie_0_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -2879,6 +3277,11 @@ static struct clk_branch gcc_pcie_1_pipe_clk =3D { .enable_mask =3D BIT(30), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_pcie_1_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -2968,6 +3371,11 @@ static struct clk_branch gcc_pcie_2_pipe_clk =3D { .enable_mask =3D BIT(23), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_pcie_2_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5156,6 +5564,33 @@ static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_= clk_src =3D { }, }; =20 +static const struct parent_map gcc_parent_map_34[] =3D { + { P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 }, + { P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, + { P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 3 }, +}; + +static const struct clk_parent_data gcc_parent_data_34[] =3D { + { .hw =3D &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw }, + { .index =3D DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, + { .index =3D DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC }, +}; + +static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src =3D { + .reg =3D 0x39070, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_34, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb34_prim_phy_pipe_clk_src", + .parent_data =3D gcc_parent_data_34, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_34), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + static struct clk_branch gcc_usb3_prim_phy_pipe_clk =3D { .halt_reg =3D 0x39068, .halt_check =3D BRANCH_HALT_SKIP, @@ -5167,7 +5602,7 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = =3D { .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb3_prim_phy_pipe_clk", .parent_hws =3D (const struct clk_hw*[]) { - &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, + &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -5227,6 +5662,33 @@ static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_c= lk_src =3D { }, }; =20 +static const struct parent_map gcc_parent_map_35[] =3D { + { P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 }, + { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, + { P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 }, +}; + +static const struct clk_parent_data gcc_parent_data_35[] =3D { + { .hw =3D &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw }, + { .index =3D DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, + { .index =3D DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC }, +}; + +static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src =3D { + .reg =3D 0xa1070, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_35, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb34_sec_phy_pipe_clk_src", + .parent_data =3D gcc_parent_data_35, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_35), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + static struct clk_branch gcc_usb3_sec_phy_pipe_clk =3D { .halt_reg =3D 0xa1068, .halt_check =3D BRANCH_HALT_SKIP, @@ -5238,7 +5700,7 @@ static struct clk_branch gcc_usb3_sec_phy_pipe_clk = =3D { .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb3_sec_phy_pipe_clk", .parent_hws =3D (const struct clk_hw*[]) { - &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, + &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -5298,6 +5760,33 @@ static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_= clk_src =3D { }, }; =20 +static const struct parent_map gcc_parent_map_36[] =3D { + { P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 0 }, + { P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 }, + { P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 3 }, +}; + +static const struct clk_parent_data gcc_parent_data_36[] =3D { + { .hw =3D &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw }, + { .index =3D DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK }, + { .index =3D DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC }, +}; + +static struct clk_regmap_mux gcc_usb34_tert_phy_pipe_clk_src =3D { + .reg =3D 0xa2070, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_36, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb34_tert_phy_pipe_clk_src", + .parent_data =3D gcc_parent_data_36, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_36), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + static struct clk_branch gcc_usb3_tert_phy_pipe_clk =3D { .halt_reg =3D 0xa2068, .halt_check =3D BRANCH_HALT_SKIP, @@ -5309,7 +5798,7 @@ static struct clk_branch gcc_usb3_tert_phy_pipe_clk = =3D { .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb3_tert_phy_pipe_clk", .parent_hws =3D (const struct clk_hw*[]) { - &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw, + &gcc_usb34_tert_phy_pipe_clk_src.clkr.hw, }, .num_parents =3D 1, .flags =3D CLK_SET_RATE_PARENT, @@ -5335,12 +5824,17 @@ static struct clk_branch gcc_usb4_0_cfg_ahb_clk =3D= { =20 static struct clk_branch gcc_usb4_0_dp0_clk =3D { .halt_reg =3D 0x9f060, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x9f060, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_0_dp0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_0_phy_dp0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5348,12 +5842,17 @@ static struct clk_branch gcc_usb4_0_dp0_clk =3D { =20 static struct clk_branch gcc_usb4_0_dp1_clk =3D { .halt_reg =3D 0x9f108, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x9f108, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_0_dp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_0_phy_dp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5385,6 +5884,11 @@ static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_= clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_0_phy_p2rr2p_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5398,6 +5902,11 @@ static struct clk_branch gcc_usb4_0_phy_pcie_pipe_cl= k =3D { .enable_mask =3D BIT(19), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_0_phy_pcie_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5405,12 +5914,17 @@ static struct clk_branch gcc_usb4_0_phy_pcie_pipe_c= lk =3D { =20 static struct clk_branch gcc_usb4_0_phy_rx0_clk =3D { .halt_reg =3D 0x9f0b0, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x9f0b0, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_0_phy_rx0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_0_phy_rx0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5418,12 +5932,17 @@ static struct clk_branch gcc_usb4_0_phy_rx0_clk =3D= { =20 static struct clk_branch gcc_usb4_0_phy_rx1_clk =3D { .halt_reg =3D 0x9f0c0, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x9f0c0, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_0_phy_rx1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_0_phy_rx1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5439,6 +5958,11 @@ static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk= =3D { .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_0_phy_usb_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb34_prim_phy_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5470,6 +5994,11 @@ static struct clk_branch gcc_usb4_0_sys_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_0_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_0_phy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5512,12 +6041,17 @@ static struct clk_branch gcc_usb4_1_cfg_ahb_clk =3D= { =20 static struct clk_branch gcc_usb4_1_dp0_clk =3D { .halt_reg =3D 0x2b060, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x2b060, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_1_dp0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_1_phy_dp0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5525,12 +6059,17 @@ static struct clk_branch gcc_usb4_1_dp0_clk =3D { =20 static struct clk_branch gcc_usb4_1_dp1_clk =3D { .halt_reg =3D 0x2b108, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x2b108, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_1_dp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_1_phy_dp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5562,6 +6101,11 @@ static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_= clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_1_phy_p2rr2p_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5575,6 +6119,11 @@ static struct clk_branch gcc_usb4_1_phy_pcie_pipe_cl= k =3D { .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_1_phy_pcie_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5582,12 +6131,17 @@ static struct clk_branch gcc_usb4_1_phy_pcie_pipe_c= lk =3D { =20 static struct clk_branch gcc_usb4_1_phy_rx0_clk =3D { .halt_reg =3D 0x2b0b0, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x2b0b0, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_1_phy_rx0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_1_phy_rx0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5595,12 +6149,17 @@ static struct clk_branch gcc_usb4_1_phy_rx0_clk =3D= { =20 static struct clk_branch gcc_usb4_1_phy_rx1_clk =3D { .halt_reg =3D 0x2b0c0, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x2b0c0, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_1_phy_rx1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_1_phy_rx1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5616,6 +6175,11 @@ static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk= =3D { .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_1_phy_usb_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb34_sec_phy_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5647,6 +6211,11 @@ static struct clk_branch gcc_usb4_1_sys_clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_1_sys_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_1_phy_sys_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5689,12 +6258,17 @@ static struct clk_branch gcc_usb4_2_cfg_ahb_clk =3D= { =20 static struct clk_branch gcc_usb4_2_dp0_clk =3D { .halt_reg =3D 0x11060, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x11060, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_2_dp0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_2_phy_dp0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5702,12 +6276,17 @@ static struct clk_branch gcc_usb4_2_dp0_clk =3D { =20 static struct clk_branch gcc_usb4_2_dp1_clk =3D { .halt_reg =3D 0x11108, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x11108, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_2_dp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_2_phy_dp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5739,6 +6318,11 @@ static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_= clk =3D { .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_2_phy_p2rr2p_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5752,6 +6336,11 @@ static struct clk_branch gcc_usb4_2_phy_pcie_pipe_cl= k =3D { .enable_mask =3D BIT(1), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_2_phy_pcie_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5759,12 +6348,17 @@ static struct clk_branch gcc_usb4_2_phy_pcie_pipe_c= lk =3D { =20 static struct clk_branch gcc_usb4_2_phy_rx0_clk =3D { .halt_reg =3D 0x110b0, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x110b0, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_2_phy_rx0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_2_phy_rx0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5772,12 +6366,17 @@ static struct clk_branch gcc_usb4_2_phy_rx0_clk =3D= { =20 static struct clk_branch gcc_usb4_2_phy_rx1_clk =3D { .halt_reg =3D 0x110c0, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x110c0, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_2_phy_rx1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb4_2_phy_rx1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5793,6 +6392,11 @@ static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk= =3D { .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_usb4_2_phy_usb_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb34_tert_phy_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -6483,6 +7087,9 @@ static struct clk_regmap *gcc_x1e80100_clocks[] =3D { [GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] =3D &gcc_usb30_tert_mock_utmi_clk_src.= clkr, [GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb30_tert_mock_utmi_= postdiv_clk_src.clkr, [GCC_USB30_TERT_SLEEP_CLK] =3D &gcc_usb30_tert_sleep_clk.clkr, + [GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] =3D &gcc_usb34_prim_phy_pipe_clk_src.cl= kr, + [GCC_USB34_SEC_PHY_PIPE_CLK_SRC] =3D &gcc_usb34_sec_phy_pipe_clk_src.clkr, + [GCC_USB34_TERT_PHY_PIPE_CLK_SRC] =3D &gcc_usb34_tert_phy_pipe_clk_src.cl= kr, [GCC_USB3_MP_PHY_AUX_CLK] =3D &gcc_usb3_mp_phy_aux_clk.clkr, [GCC_USB3_MP_PHY_AUX_CLK_SRC] =3D &gcc_usb3_mp_phy_aux_clk_src.clkr, [GCC_USB3_MP_PHY_COM_AUX_CLK] =3D &gcc_usb3_mp_phy_com_aux_clk.clkr, @@ -6508,11 +7115,18 @@ static struct clk_regmap *gcc_x1e80100_clocks[] =3D= { [GCC_USB4_0_DP1_CLK] =3D &gcc_usb4_0_dp1_clk.clkr, [GCC_USB4_0_MASTER_CLK] =3D &gcc_usb4_0_master_clk.clkr, [GCC_USB4_0_MASTER_CLK_SRC] =3D &gcc_usb4_0_master_clk_src.clkr, + [GCC_USB4_0_PHY_DP0_CLK_SRC] =3D &gcc_usb4_0_phy_dp0_clk_src.clkr, + [GCC_USB4_0_PHY_DP1_CLK_SRC] =3D &gcc_usb4_0_phy_dp1_clk_src.clkr, [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] =3D &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr, + [GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC] =3D &gcc_usb4_0_phy_p2rr2p_pipe_clk_= src.clkr, [GCC_USB4_0_PHY_PCIE_PIPE_CLK] =3D &gcc_usb4_0_phy_pcie_pipe_clk.clkr, [GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] =3D &gcc_usb4_0_phy_pcie_pipe_clk_src.= clkr, + [GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC] =3D &gcc_usb4_0_phy_pcie_pipe_mux_= clk_src.clkr, [GCC_USB4_0_PHY_RX0_CLK] =3D &gcc_usb4_0_phy_rx0_clk.clkr, + [GCC_USB4_0_PHY_RX0_CLK_SRC] =3D &gcc_usb4_0_phy_rx0_clk_src.clkr, [GCC_USB4_0_PHY_RX1_CLK] =3D &gcc_usb4_0_phy_rx1_clk.clkr, + [GCC_USB4_0_PHY_RX1_CLK_SRC] =3D &gcc_usb4_0_phy_rx1_clk_src.clkr, + [GCC_USB4_0_PHY_SYS_CLK_SRC] =3D &gcc_usb4_0_phy_sys_clk_src.clkr, [GCC_USB4_0_PHY_USB_PIPE_CLK] =3D &gcc_usb4_0_phy_usb_pipe_clk.clkr, [GCC_USB4_0_SB_IF_CLK] =3D &gcc_usb4_0_sb_if_clk.clkr, [GCC_USB4_0_SB_IF_CLK_SRC] =3D &gcc_usb4_0_sb_if_clk_src.clkr, @@ -6524,11 +7138,18 @@ static struct clk_regmap *gcc_x1e80100_clocks[] =3D= { [GCC_USB4_1_DP1_CLK] =3D &gcc_usb4_1_dp1_clk.clkr, [GCC_USB4_1_MASTER_CLK] =3D &gcc_usb4_1_master_clk.clkr, [GCC_USB4_1_MASTER_CLK_SRC] =3D &gcc_usb4_1_master_clk_src.clkr, + [GCC_USB4_1_PHY_DP0_CLK_SRC] =3D &gcc_usb4_1_phy_dp0_clk_src.clkr, + [GCC_USB4_1_PHY_DP1_CLK_SRC] =3D &gcc_usb4_1_phy_dp1_clk_src.clkr, [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] =3D &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr, + [GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] =3D &gcc_usb4_1_phy_p2rr2p_pipe_clk_= src.clkr, [GCC_USB4_1_PHY_PCIE_PIPE_CLK] =3D &gcc_usb4_1_phy_pcie_pipe_clk.clkr, [GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] =3D &gcc_usb4_1_phy_pcie_pipe_clk_src.= clkr, + [GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] =3D &gcc_usb4_1_phy_pcie_pipe_mux_= clk_src.clkr, [GCC_USB4_1_PHY_RX0_CLK] =3D &gcc_usb4_1_phy_rx0_clk.clkr, + [GCC_USB4_1_PHY_RX0_CLK_SRC] =3D &gcc_usb4_1_phy_rx0_clk_src.clkr, [GCC_USB4_1_PHY_RX1_CLK] =3D &gcc_usb4_1_phy_rx1_clk.clkr, + [GCC_USB4_1_PHY_RX1_CLK_SRC] =3D &gcc_usb4_1_phy_rx1_clk_src.clkr, + [GCC_USB4_1_PHY_SYS_CLK_SRC] =3D &gcc_usb4_1_phy_sys_clk_src.clkr, [GCC_USB4_1_PHY_USB_PIPE_CLK] =3D &gcc_usb4_1_phy_usb_pipe_clk.clkr, [GCC_USB4_1_SB_IF_CLK] =3D &gcc_usb4_1_sb_if_clk.clkr, [GCC_USB4_1_SB_IF_CLK_SRC] =3D &gcc_usb4_1_sb_if_clk_src.clkr, @@ -6540,11 +7161,18 @@ static struct clk_regmap *gcc_x1e80100_clocks[] =3D= { [GCC_USB4_2_DP1_CLK] =3D &gcc_usb4_2_dp1_clk.clkr, [GCC_USB4_2_MASTER_CLK] =3D &gcc_usb4_2_master_clk.clkr, [GCC_USB4_2_MASTER_CLK_SRC] =3D &gcc_usb4_2_master_clk_src.clkr, + [GCC_USB4_2_PHY_DP0_CLK_SRC] =3D &gcc_usb4_2_phy_dp0_clk_src.clkr, + [GCC_USB4_2_PHY_DP1_CLK_SRC] =3D &gcc_usb4_2_phy_dp1_clk_src.clkr, [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] =3D &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr, + [GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC] =3D &gcc_usb4_2_phy_p2rr2p_pipe_clk_= src.clkr, [GCC_USB4_2_PHY_PCIE_PIPE_CLK] =3D &gcc_usb4_2_phy_pcie_pipe_clk.clkr, [GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] =3D &gcc_usb4_2_phy_pcie_pipe_clk_src.= clkr, + [GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC] =3D &gcc_usb4_2_phy_pcie_pipe_mux_= clk_src.clkr, [GCC_USB4_2_PHY_RX0_CLK] =3D &gcc_usb4_2_phy_rx0_clk.clkr, + [GCC_USB4_2_PHY_RX0_CLK_SRC] =3D &gcc_usb4_2_phy_rx0_clk_src.clkr, [GCC_USB4_2_PHY_RX1_CLK] =3D &gcc_usb4_2_phy_rx1_clk.clkr, + [GCC_USB4_2_PHY_RX1_CLK_SRC] =3D &gcc_usb4_2_phy_rx1_clk_src.clkr, + [GCC_USB4_2_PHY_SYS_CLK_SRC] =3D &gcc_usb4_2_phy_sys_clk_src.clkr, [GCC_USB4_2_PHY_USB_PIPE_CLK] =3D &gcc_usb4_2_phy_usb_pipe_clk.clkr, [GCC_USB4_2_SB_IF_CLK] =3D &gcc_usb4_2_sb_if_clk.clkr, [GCC_USB4_2_SB_IF_CLK_SRC] =3D &gcc_usb4_2_sb_if_clk_src.clkr, @@ -6660,16 +7288,52 @@ static const struct qcom_reset_map gcc_x1e80100_res= ets[] =3D { [GCC_USB3_UNIPHY_MP0_BCR] =3D { 0x19000 }, [GCC_USB3_UNIPHY_MP1_BCR] =3D { 0x54000 }, [GCC_USB3PHY_PHY_PRIM_BCR] =3D { 0x50004 }, + [GCC_USB4PHY_PHY_PRIM_BCR] =3D { 0x5000c }, [GCC_USB3PHY_PHY_SEC_BCR] =3D { 0x2a004 }, + [GCC_USB4PHY_PHY_SEC_BCR] =3D { 0x2a00c }, [GCC_USB3PHY_PHY_TERT_BCR] =3D { 0xa3004 }, + [GCC_USB4PHY_PHY_TERT_BCR] =3D { 0xa300c }, [GCC_USB3UNIPHY_PHY_MP0_BCR] =3D { 0x19004 }, [GCC_USB3UNIPHY_PHY_MP1_BCR] =3D { 0x54004 }, [GCC_USB4_0_BCR] =3D { 0x9f000 }, [GCC_USB4_0_DP0_PHY_PRIM_BCR] =3D { 0x50010 }, - [GCC_USB4_1_DP0_PHY_SEC_BCR] =3D { 0x2a010 }, - [GCC_USB4_2_DP0_PHY_TERT_BCR] =3D { 0xa3010 }, + [GCC_USB4_0_MISC_USB4_SYS_BCR] =3D { .reg =3D 0xad0f8, .bit =3D 0 }, + [GCC_USB4_0_MISC_RX_CLK_0_BCR] =3D { .reg =3D 0xad0f8, .bit =3D 1 }, + [GCC_USB4_0_MISC_RX_CLK_1_BCR] =3D { .reg =3D 0xad0f8, .bit =3D 2 }, + [GCC_USB4_0_MISC_USB_PIPE_BCR] =3D { .reg =3D 0xad0f8, .bit =3D 3 }, + [GCC_USB4_0_MISC_PCIE_PIPE_BCR] =3D { .reg =3D 0xad0f8, .bit =3D 4 }, + [GCC_USB4_0_MISC_TMU_BCR] =3D { .reg =3D 0xad0f8, .bit =3D 5 }, + [GCC_USB4_0_MISC_SB_IF_BCR] =3D { .reg =3D 0xad0f8, .bit =3D 6 }, + [GCC_USB4_0_MISC_HIA_MSTR_BCR] =3D { .reg =3D 0xad0f8, .bit =3D 7 }, + [GCC_USB4_0_MISC_AHB_BCR] =3D { .reg =3D 0xad0f8, .bit =3D 8 }, + [GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR] =3D { .reg =3D 0xad0f8, .bit =3D 9 }, + [GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR] =3D { .reg =3D 0xad0f8, .bit =3D 10 }, [GCC_USB4_1_BCR] =3D { 0x2b000 }, + [GCC_USB4_1_DP0_PHY_SEC_BCR] =3D { 0x2a010 }, + [GCC_USB4_1_MISC_USB4_SYS_BCR] =3D { .reg =3D 0xae0f8, .bit =3D 0 }, + [GCC_USB4_1_MISC_RX_CLK_0_BCR] =3D { .reg =3D 0xae0f8, .bit =3D 1 }, + [GCC_USB4_1_MISC_RX_CLK_1_BCR] =3D { .reg =3D 0xae0f8, .bit =3D 2 }, + [GCC_USB4_1_MISC_USB_PIPE_BCR] =3D { .reg =3D 0xae0f8, .bit =3D 3 }, + [GCC_USB4_1_MISC_PCIE_PIPE_BCR] =3D { .reg =3D 0xae0f8, .bit =3D 4 }, + [GCC_USB4_1_MISC_TMU_BCR] =3D { .reg =3D 0xae0f8, .bit =3D 5 }, + [GCC_USB4_1_MISC_SB_IF_BCR] =3D { .reg =3D 0xae0f8, .bit =3D 6 }, + [GCC_USB4_1_MISC_HIA_MSTR_BCR] =3D { .reg =3D 0xae0f8, .bit =3D 7 }, + [GCC_USB4_1_MISC_AHB_BCR] =3D { .reg =3D 0xae0f8, .bit =3D 8 }, + [GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR] =3D { .reg =3D 0xae0f8, .bit =3D 9 }, + [GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR] =3D { .reg =3D 0xae0f8, .bit =3D 10 }, [GCC_USB4_2_BCR] =3D { 0x11000 }, + [GCC_USB4_2_DP0_PHY_TERT_BCR] =3D { 0xa3010 }, + [GCC_USB4_2_MISC_USB4_SYS_BCR] =3D { .reg =3D 0xaf0f8, .bit =3D 0 }, + [GCC_USB4_2_MISC_RX_CLK_0_BCR] =3D { .reg =3D 0xaf0f8, .bit =3D 1 }, + [GCC_USB4_2_MISC_RX_CLK_1_BCR] =3D { .reg =3D 0xaf0f8, .bit =3D 2 }, + [GCC_USB4_2_MISC_USB_PIPE_BCR] =3D { .reg =3D 0xaf0f8, .bit =3D 3 }, + [GCC_USB4_2_MISC_PCIE_PIPE_BCR] =3D { .reg =3D 0xaf0f8, .bit =3D 4 }, + [GCC_USB4_2_MISC_TMU_BCR] =3D { .reg =3D 0xaf0f8, .bit =3D 5 }, + [GCC_USB4_2_MISC_SB_IF_BCR] =3D { .reg =3D 0xaf0f8, .bit =3D 6 }, + [GCC_USB4_2_MISC_HIA_MSTR_BCR] =3D { .reg =3D 0xaf0f8, .bit =3D 7 }, + [GCC_USB4_2_MISC_AHB_BCR] =3D { .reg =3D 0xaf0f8, .bit =3D 8 }, + [GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR] =3D { .reg =3D 0xaf0f8, .bit =3D 9 }, + [GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR] =3D { .reg =3D 0xaf0f8, .bit =3D 10 }, [GCC_USB_0_PHY_BCR] =3D { 0x50020 }, [GCC_USB_1_PHY_BCR] =3D { 0x2a020 }, [GCC_USB_2_PHY_BCR] =3D { 0xa3020 }, --=20 2.51.0 From nobody Wed Dec 17 08:56:20 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B7072DE6F3; Fri, 3 Oct 2025 18:14:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759515298; cv=none; b=VlxYz8IMUubdC0TTAEIkeDrCutX1b5kLYXSZqcovnKtx/9C/s/xxc+ynP3pg55J3PHD+5bEIF72jPptcS6QhpVweNrWbAOBcyrNmLY3tcIJjSfA4GmRQdvlstHn7IrwG0KovxSDABOnO+Ic6q/lcbaiXL7Ow5ZJ+hCiPp9KWILs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759515298; c=relaxed/simple; bh=62prP2dHzFG2Q4eOW7IrcP7Whf+smyjuX0kmntMCILE=; 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T2+ZqpQuiMQEe7dxYA/hvymCaOa4wohIO1qq0r8QW0bpYATPvr43PofZUTYuXj0f+J cfiK1BlLhsEDOA5VVWjXxZY/irCOA66kpND2En4SLSPQqxmvwZN+S8q3VCR0ft38a2 iytHyPiz6hoaTcM41V+XuxkamyWHaCvEvB4wzAHLNR+YS9WmiUyRL+psvc6eOJQvfy W6KlbLZKlJmdyhy4pGkdF/DPnG7eMeYAl/W3KyJuV1SGra/4lzfsndS8/Ur6J+tpOv WMxk8kele7vOA== From: Konrad Dybcio Date: Fri, 03 Oct 2025 20:14:40 +0200 Subject: [PATCH v2 3/3] arm64: dts: qcom: x1e80100: Extend the gcc input clock list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251003-topic-hamoa_gcc_usb4-v2-3-61d27a14ee65@oss.qualcomm.com> References: <20251003-topic-hamoa_gcc_usb4-v2-0-61d27a14ee65@oss.qualcomm.com> In-Reply-To: <20251003-topic-hamoa_gcc_usb4-v2-0-61d27a14ee65@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Konrad Dybcio , Wesley Cheng , Bryan O'Donoghue , Sibi Sankar , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1759515280; l=1397; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=Ptb3eamm9HjWOiDCCiBnCDMX562eyPz3xJ8RictPz9k=; b=vTrElk6CTem9Y24Vfmy1pHTTdPYZuepuYSeXEbOIUTXkWVVTWN2TqOz5wNXZhDiB1m2zBw9h+ I05mt5vSL9HCyWJOhj3rAvXX8CZQPjeIkGulgKZltls45htk0jDXrJe X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio With the recent dt-bindings update, the missing USB4 clocks have been added. Extend the existing list to make sure the DT contains the expected amount of 'clocks' entries. Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 51576d9c935decbc61a8e4200de83e739f7da814..cc76b9933a9bbff396ec4739f4a= 1dd3d2cc81f0f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -807,7 +807,34 @@ gcc: clock-controller@100000 { <0>, <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, - <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; =20 power-domains =3D <&rpmhpd RPMHPD_CX>; #clock-cells =3D <1>; --=20 2.51.0