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[144.49.247.100]) by smtp-relay.gmail.com with ESMTPS id 6a1803df08f44-878be71f54fsm2106576d6.38.2025.10.02.14.04.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 Oct 2025 14:04:58 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-wm1-f69.google.com with SMTP id 5b1f17b1804b1-46e2c11b94cso8158055e9.3 for ; Thu, 02 Oct 2025 14:04:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1759439096; x=1760043896; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cwbGC/K9B4U3uycXerXPSUMJfx+iuM+3b1WmPO2FpvA=; b=Lla/DPB3WmnBpFo58glyl4E1EX6loBo97OZDqbimiK2yb+184P1kmNfbe/ttz7DQIU dYWeo1bUOoQV6YnXIy045g4h3YXEYUUskeexlto/34/ObsXE+2AfmGGuHZijUNDkOtmt tGD1bpDtn2tUC/d2he9dbo726UHcR0fduO9BU= X-Forwarded-Encrypted: i=1; AJvYcCWRQ1QxLWOoVSnMqS3b15rwiEOayKa/3lfahAUhyxtqvxF8IlSmGH1cWXVn4lVzU6Fb1ULBrD3RxzijoX4=@vger.kernel.org X-Received: by 2002:a05:600c:8b22:b0:45b:4a98:91cf with SMTP id 5b1f17b1804b1-46e71102657mr4393345e9.15.1759439096532; Thu, 02 Oct 2025 14:04:56 -0700 (PDT) X-Received: by 2002:a05:600c:8b22:b0:45b:4a98:91cf with SMTP id 5b1f17b1804b1-46e71102657mr4393165e9.15.1759439096023; Thu, 02 Oct 2025 14:04:56 -0700 (PDT) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e5c4c0321sm61711295e9.8.2025.10.02.14.04.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Oct 2025 14:04:55 -0700 (PDT) From: Kamal Dasu To: andersson@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Kamal Dasu Subject: [PATCH 3/3] mmc: brcmstb: save and restore registers during PM Date: Thu, 2 Oct 2025 17:04:26 -0400 Message-Id: <20251002210426.2490368-4-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251002210426.2490368-1-kamal.dasu@broadcom.com> References: <20251002210426.2490368-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Added support to save and restore registers that are critical during PM. Signed-off-by: Kamal Dasu Reviewed-by: Florian Fainelli --- drivers/mmc/host/sdhci-brcmstb.c | 124 +++++++++++++++++++++++++++++-- 1 file changed, 119 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcm= stb.c index 0905b316a24b..ffa602a99ab7 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -24,7 +24,9 @@ #define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0) #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1) #define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE BIT(2) -#define BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY BIT(4) +#define BRCMSTB_MATCH_FLAGS_HAS_CFG_V1 BIT(3) +#define BRCMSTB_MATCH_FLAGS_HAS_CFG_V2 BIT(4) +#define BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY BIT(5) =20 #define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0) #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK BIT(1) @@ -38,19 +40,39 @@ #define SDIO_CFG_OP_DLY_DEFAULT 0x80000003 #define SDIO_CFG_CQ_CAPABILITY 0x4c #define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) +#define SDIO_CFG_SD_PIN_SEL 0x44 +#define SDIO_CFG_V1_SD_PIN_SEL 0x54 +#define SDIO_CFG_PHY_SW_MODE_0_RX_CTRL 0x7C #define SDIO_CFG_MAX_50MHZ_MODE 0x1ac #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) =20 +#define SDIO_BOOT_MAIN_CTL 0x0 + #define MMC_CAP_HSE_MASK (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V) /* Select all SD UHS type I SDR speed above 50MB/s */ #define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) =20 +enum cfg_core_ver { + SDIO_CFG_CORE_V1 =3D 1, + SDIO_CFG_CORE_V2, +}; + +struct sdhci_brcmstb_saved_regs { + u32 sd_pin_sel; + u32 phy_sw_mode0_rxctrl; + u32 max_50mhz_mode; + u32 boot_main_ctl; +}; + struct sdhci_brcmstb_priv { void __iomem *cfg_regs; + void __iomem *boot_regs; + struct sdhci_brcmstb_saved_regs saved_regs; unsigned int flags; struct clk *base_clk; u32 base_freq_hz; + void (*save_restore_regs)(struct mmc_host *mmc, int save); }; =20 struct brcmstb_match_priv { @@ -60,6 +82,69 @@ struct brcmstb_match_priv { const unsigned int flags; }; =20 +static void sdhci_brcmstb_save_regs(struct mmc_host *mmc, enum cfg_core_ve= r ver) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + struct sdhci_brcmstb_saved_regs *sr =3D &priv->saved_regs; + void __iomem *cr =3D priv->cfg_regs; + bool is_emmc =3D mmc->caps & MMC_CAP_NONREMOVABLE; + + /* save */ + if (is_emmc && priv->boot_regs) + sr->boot_main_ctl =3D readl(priv->boot_regs + SDIO_BOOT_MAIN_CTL); + + if (ver =3D=3D SDIO_CFG_CORE_V1) { + sr->sd_pin_sel =3D readl(cr + SDIO_CFG_V1_SD_PIN_SEL); + return; + } + + sr->sd_pin_sel =3D readl(cr + SDIO_CFG_SD_PIN_SEL); + sr->phy_sw_mode0_rxctrl =3D readl(cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL); + sr->max_50mhz_mode =3D readl(cr + SDIO_CFG_MAX_50MHZ_MODE); +} + +static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, + enum cfg_core_ver ver) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + struct sdhci_brcmstb_saved_regs *sr =3D &priv->saved_regs; + void __iomem *cr =3D priv->cfg_regs; + bool is_emmc =3D mmc->caps & MMC_CAP_NONREMOVABLE; + + /* restore */ + if (is_emmc && priv->boot_regs) + writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL); + + if (ver =3D=3D SDIO_CFG_CORE_V1) { + writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL); + return; + } + + writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL); + writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL); + writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE); +} + +static void sdhci_brcmstb_save_restore_regs_v1(struct mmc_host *mmc, int s= ave) +{ + if (save) + sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V1); + else + sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V1); +} + +static void sdhci_brcmstb_save_restore_regs_v2(struct mmc_host *mmc, int s= ave) +{ + if (save) + sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V2); + else + sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V2); +} + static inline void enable_clock_gating(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); @@ -300,24 +385,33 @@ static struct brcmstb_match_priv match_priv_7425 =3D { .ops =3D &sdhci_brcmstb_ops, }; =20 -static struct brcmstb_match_priv match_priv_7445 =3D { +static struct brcmstb_match_priv match_priv_74371 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, .ops =3D &sdhci_brcmstb_ops, }; =20 +static struct brcmstb_match_priv match_priv_7445 =3D { + .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT | + BRCMSTB_MATCH_FLAGS_HAS_CFG_V1, + .ops =3D &sdhci_brcmstb_ops, +}; + static struct brcmstb_match_priv match_priv_72116 =3D { - .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, + .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT | + BRCMSTB_MATCH_FLAGS_HAS_CFG_V1, .ops =3D &sdhci_brcmstb_ops_72116, }; =20 static const struct brcmstb_match_priv match_priv_7216 =3D { - .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, + .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE | + BRCMSTB_MATCH_FLAGS_HAS_CFG_V2, .hs400es =3D sdhci_brcmstb_hs400es, .ops =3D &sdhci_brcmstb_ops_7216, }; =20 static struct brcmstb_match_priv match_priv_74165b0 =3D { - .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, + .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE | + BRCMSTB_MATCH_FLAGS_HAS_CFG_V2, .hs400es =3D sdhci_brcmstb_hs400es, .ops =3D &sdhci_brcmstb_ops_74165b0, }; @@ -325,6 +419,7 @@ static struct brcmstb_match_priv match_priv_74165b0 =3D= { static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] =3D { { .compatible =3D "brcm,bcm2712-sdhci", .data =3D &match_priv_2712 }, { .compatible =3D "brcm,bcm7425-sdhci", .data =3D &match_priv_7425 }, + { .compatible =3D "brcm,bcm74371-sdhci", .data =3D &match_priv_74371 }, { .compatible =3D "brcm,bcm7445-sdhci", .data =3D &match_priv_7445 }, { .compatible =3D "brcm,bcm72116-sdhci", .data =3D &match_priv_72116 }, { .compatible =3D "brcm,bcm7216-sdhci", .data =3D &match_priv_7216 }, @@ -441,6 +536,19 @@ static int sdhci_brcmstb_probe(struct platform_device = *pdev) if (res) goto err; =20 + /* map non-standard BOOT registers if present */ + if (host->mmc->caps & MMC_CAP_NONREMOVABLE) { + priv->boot_regs =3D devm_platform_get_and_ioremap_resource(pdev, 2, NULL= ); + if (IS_ERR(priv->boot_regs)) + priv->boot_regs =3D NULL; + } + + if (match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CFG_V1) + priv->save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v1; + + if (match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CFG_V2) + priv->save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v2; + /* * Automatic clock gating does not work for SD cards that may * voltage switch so only enable it for non-removable devices. @@ -533,6 +641,9 @@ static int sdhci_brcmstb_suspend(struct device *dev) struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); int ret; =20 + if (priv->save_restore_regs) + priv->save_restore_regs(host->mmc, 1); + clk_disable_unprepare(priv->base_clk); if (host->mmc->caps2 & MMC_CAP2_CQE) { ret =3D cqhci_suspend(host->mmc); @@ -564,6 +675,9 @@ static int sdhci_brcmstb_resume(struct device *dev) ret =3D clk_set_rate(priv->base_clk, priv->base_freq_hz); } =20 + if (priv->save_restore_regs) + priv->save_restore_regs(host->mmc, 0); + if (host->mmc->caps2 & MMC_CAP2_CQE) ret =3D cqhci_resume(host->mmc); =20 --=20 2.34.1