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[144.49.247.19]) by smtp-relay.gmail.com with ESMTPS id 6a1803df08f44-878bac6c1c6sm2255126d6.8.2025.10.02.14.04.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 Oct 2025 14:04:48 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-wm1-f72.google.com with SMTP id 5b1f17b1804b1-46e4c8fa2b1so8147575e9.0 for ; Thu, 02 Oct 2025 14:04:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1759439086; x=1760043886; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d0VBquDv6g415iy1L7kGakH7H853FAzWxsvjxiCHfN8=; b=B+mHKi7FrxKqXf4T4MBS5guhb/3IiPhc4kpJMT8Jx/STD3M/UTs5QwsYI3aQXdqBe6 gCg7OSputMXRtqZg/Sf3Zq6g0mwI7VaJ/P1tM5hyPlI6IDsV0YS/ZBaNgX1GlVYCbBaj p6s/CpiPQ8Caear653sKwVVQ5eCE54X4YmGVY= X-Forwarded-Encrypted: i=1; AJvYcCXBvoaNyu51Lz2BVwAjb+aWRtEeSW7y3cmGUvbxBvTZPvm0fnZbw21Tqd+wixDR99GZO1nXJK8vF5jfhVI=@vger.kernel.org X-Received: by 2002:a05:600d:420d:b0:45b:47e1:ef6d with SMTP id 5b1f17b1804b1-46e71172104mr4721595e9.36.1759439086297; Thu, 02 Oct 2025 14:04:46 -0700 (PDT) X-Received: by 2002:a05:600d:420d:b0:45b:47e1:ef6d with SMTP id 5b1f17b1804b1-46e71172104mr4721505e9.36.1759439085831; Thu, 02 Oct 2025 14:04:45 -0700 (PDT) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e5c4c0321sm61711295e9.8.2025.10.02.14.04.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Oct 2025 14:04:45 -0700 (PDT) From: Kamal Dasu To: andersson@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Kamal Dasu Subject: [PATCH 1/3] dt-bindings: mmc: Add support for BCM72116 and BCM74371 SD host controller Date: Thu, 2 Oct 2025 17:04:24 -0400 Message-Id: <20251002210426.2490368-2-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251002210426.2490368-1-kamal.dasu@broadcom.com> References: <20251002210426.2490368-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Updating compatibility to support BCM72116 and BCM74371 SD host controller similar to other settop SoCs. Signed-off-by: Kamal Dasu Acked-by: Conor Dooley Reviewed-by: Florian Fainelli --- Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml = b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index eee6be7a7867..720d0762078f 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -21,9 +21,11 @@ properties: - items: - enum: - brcm,bcm2712-sdhci + - brcm,bcm72116-sdhci - brcm,bcm74165b0-sdhci - brcm,bcm7445-sdhci - brcm,bcm7425-sdhci + - brcm,bcm74371-sdhci - const: brcm,sdhci-brcmstb =20 reg: --=20 2.34.1 From nobody Sun Feb 8 09:37:50 2026 Received: from mail-yw1-f226.google.com (mail-yw1-f226.google.com [209.85.128.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40F018C1F for ; Thu, 2 Oct 2025 21:04:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759439094; cv=none; b=rdSkO+oBZ6ITcTK1Kzawsae16Ozq2g4prxegGJ8d9Q4Nipadkab+P0da+cSfJMSRhbJRQRl97JuRnzOJWHuP4APAQ1RFwqe8yMjojp/7Lua3HEQlo9mMPMo8KId/U2IYxSIBV1ZFFBswx5FUN0zZa3uNm0y5FfvOoIOJ4bZjKv4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759439094; c=relaxed/simple; bh=SbL6UcwBpYbwRwNOueWqf3w8SnBvv9kw5WB+oOZBTow=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tEBkqxyO3d/6saYP4rChia4LvDl15qhJIzaUyNypARjeVsR+DCAxGSjqpzjn0tFCfaM8oAMz0kd3d9C+kWpRYL0ACdYTbH9uEi8hDE1V/Qr/llg5BLUbGVTFZZNI+8bY9WCku51yKgMjhXAk2hh6ul5G6s2yFzi5jP0qEFLCiC0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=IJYG+P8C; arc=none smtp.client-ip=209.85.128.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="IJYG+P8C" Received: by mail-yw1-f226.google.com with SMTP id 00721157ae682-71d6051aeafso16657297b3.2 for ; Thu, 02 Oct 2025 14:04:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759439092; x=1760043892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ZIU73QOdUXqw8XH54gnOsyWC2NrvdvHxRkWX7Bf2XKY=; b=dFSsOf0WsRBnoAYdbdKldBzP1En8OfBfvbbP7iC0YhMEwLYx2yDlSOY+zq9kQVog7X V69DvRqiVhQ4bvAhrIjpnyEgw53PlbeS2kB+uiJkviXFG6O7rEPwu57LCAs1POkAeaIP AtT6n/cc52TaoQakEatJREMfYBFZswrNKS4CpFzG0rs9nFy/Wmpitk2x5VtVBtgNs8gw OGrWgccFIu5lE2VFt3DB6haVvWFYI289khPfkHRS0JJq5emg12aWEMG4ciT78IP0ByPI LhroDgnsJMQ6Hg0vB+f83CqeuNcYOc5MWfsHjdWS7nhGg2GrotQ+aHkmziJHTzk5iqAV 5jLg== X-Forwarded-Encrypted: i=1; AJvYcCUn0KzVqe2MPU9LGX6U9RK/k94vXJPG+ZFJ45qh1qovtX4CqltAjfmc+xpO6/BrvxWdHzBbdqYugg3+hp4=@vger.kernel.org X-Gm-Message-State: AOJu0YziA4NESMDWU/n9dTv3zvQPEIaVFebX/s12hCPEAU6mDX/+fNXc pt6d6tfYKBvrC7aBS8jQzKudTN2caqP5HWTm3FhMDnAm9SGJ8M6b9+8lcJtF885uRweJVUSQ6za AGk756Mf5J9mHyUyi61HnPcNYpNzABcihUbYDXx5RhqDqoJ/rDBwgdTC3kglxVN9ASuqjXIOVu+ vcGNt+hLTy7+DuD2aeoQQVIz7/XyJ+ngT/TbP71GzcmLMm0ZyNUNiC4xgYze3oG4uGpxIJTGUKb ZQwoDJuNqthvUPq X-Gm-Gg: ASbGncvV7aNHiQj5gA+L6TlMbtWpmtBIvxFiS5T0/gzYqUC1qhNXaktNcPIvoH7Qo/k pP92icDwlEJIFshE/qt29lql6a3RElB7MbL2oWlW1wcTqXmlbJZ8QmTOLQuXVO/NlqSwZFZi52D 2kasQG0m37oOUPrpCvHQ4wFkJO686a9KTYkyGE3FDQ2SEBgbjGmMlqi+5mb+f4/xxuOecSd5cKa KZ8lo2S/RuTh68DmSzbccMY8QVtgx9uP4+Ni4nY2akye+Zme15vdupZE008kvQHuiUv4NgwA3tB Bw8Mg+oOVgndbdJ+pU6/4KYGwqoKJwL4Lzpf8pEMWOMf1B04gefXZy77+Liu2r1ifE7U69qbJ39 hJIEBx7lpvch3mL/ixJvXL0EUzC/p9xRVi6DDXTaK3LETLHHbMIpGIVQ/Kd4zspWUohUMewQkMA i6igGR X-Google-Smtp-Source: AGHT+IG+nWX0kF2nXfJVsjarjv5Kyj8fCg28IhMXhlJiF6CVc1GLlO9B1jJOk6M7D6NQhOEaLzRn4MWm++jL X-Received: by 2002:a05:690c:9a12:b0:77e:6159:e421 with SMTP id 00721157ae682-77f946a37edmr11789337b3.32.1759439092009; Thu, 02 Oct 2025 14:04:52 -0700 (PDT) Received: from smtp-us-east1-p01-i01-si01.dlp.protect.broadcom.com (address-144-49-247-100.dlp.protect.broadcom.com. [144.49.247.100]) by smtp-relay.gmail.com with ESMTPS id 00721157ae682-77f81c0c39bsm1650127b3.4.2025.10.02.14.04.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 Oct 2025 14:04:52 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-wr1-f69.google.com with SMTP id ffacd0b85a97d-3ef9218daf5so1162774f8f.1 for ; Thu, 02 Oct 2025 14:04:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1759439090; x=1760043890; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZIU73QOdUXqw8XH54gnOsyWC2NrvdvHxRkWX7Bf2XKY=; b=IJYG+P8CWCe7DmKOCwG0Mn6Cm7Q1S/brh9hFNUgKNJIgIKNF/dP1kSYACpDfW7KmN+ MgVLwyzDpbB0aofhMsHOvi1pUKmFwVdvwj8ctX/rxnsQu/RoSR/yEORfMt6ujjjw5dK1 3uHoA1VdZcagfUVH25FAG5NfCbVohdJNkGthI= X-Forwarded-Encrypted: i=1; AJvYcCUCPpTp4IHifccTqivYXPEQ5MJEBr6uP7TQKbySZhLmnN20ng3aKZdCN8ulGpX24bZ7F8itoWOomtPKmPU=@vger.kernel.org X-Received: by 2002:a05:600c:348a:b0:46e:1f92:49aa with SMTP id 5b1f17b1804b1-46e7110ef47mr4504975e9.15.1759439090542; Thu, 02 Oct 2025 14:04:50 -0700 (PDT) X-Received: by 2002:a05:600c:348a:b0:46e:1f92:49aa with SMTP id 5b1f17b1804b1-46e7110ef47mr4504845e9.15.1759439090152; Thu, 02 Oct 2025 14:04:50 -0700 (PDT) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e5c4c0321sm61711295e9.8.2025.10.02.14.04.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Oct 2025 14:04:49 -0700 (PDT) From: Kamal Dasu To: andersson@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Kamal Dasu Subject: [PATCH 2/3] mmc: sdhci-brcmstb: clear CFG_OP_DLY when using HS200 Date: Thu, 2 Oct 2025 17:04:25 -0400 Message-Id: <20251002210426.2490368-3-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251002210426.2490368-1-kamal.dasu@broadcom.com> References: <20251002210426.2490368-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Clear SDIO_1_CFG_OP_DLY register when using HS200 mode to be compliant with timing spec. We only need this for on BCM72116 SoCs. Signed-off-by: Kamal Dasu Acked-by: Adrian Hunter Reviewed-by: Florian Fainelli --- drivers/mmc/host/sdhci-brcmstb.c | 37 ++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcm= stb.c index efc2f3bdc631..0905b316a24b 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -31,13 +31,13 @@ =20 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 =20 -#define SDIO_CFG_CQ_CAPABILITY 0x4c -#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) - #define SDIO_CFG_CTRL 0x0 #define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) #define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) - +#define SDIO_CFG_OP_DLY 0x34 +#define SDIO_CFG_OP_DLY_DEFAULT 0x80000003 +#define SDIO_CFG_CQ_CAPABILITY 0x4c +#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) #define SDIO_CFG_MAX_50MHZ_MODE 0x1ac #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) @@ -212,6 +212,22 @@ static void sdhci_brcmstb_cfginit_2712(struct sdhci_ho= st *host) } } =20 +static void sdhci_brcmstb_set_72116_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + u32 reg; + + /* no change to SDIO_CFG_OP_DLY_DEFAULT when using preset clk rate */ + if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) + return; + + reg =3D (timing =3D=3D MMC_TIMING_MMC_HS200) ? 0 : SDIO_CFG_OP_DLY_DEFAUL= T; + writel(reg, priv->cfg_regs + SDIO_CFG_OP_DLY); + sdhci_set_uhs_signaling(host, timing); +} + static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) { sdhci_dumpregs(mmc_priv(mmc)); @@ -252,6 +268,13 @@ static struct sdhci_ops sdhci_brcmstb_ops_2712 =3D { .set_uhs_signaling =3D sdhci_set_uhs_signaling, }; =20 +static struct sdhci_ops sdhci_brcmstb_ops_72116 =3D { + .set_clock =3D sdhci_set_clock, + .set_bus_width =3D sdhci_set_bus_width, + .reset =3D sdhci_reset, + .set_uhs_signaling =3D sdhci_brcmstb_set_72116_uhs_signaling, +}; + static struct sdhci_ops sdhci_brcmstb_ops_7216 =3D { .set_clock =3D sdhci_brcmstb_set_clock, .set_bus_width =3D sdhci_set_bus_width, @@ -282,6 +305,11 @@ static struct brcmstb_match_priv match_priv_7445 =3D { .ops =3D &sdhci_brcmstb_ops, }; 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[144.49.247.100]) by smtp-relay.gmail.com with ESMTPS id 6a1803df08f44-878be71f54fsm2106576d6.38.2025.10.02.14.04.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 Oct 2025 14:04:58 -0700 (PDT) X-Relaying-Domain: broadcom.com X-CFilter-Loop: Reflected Received: by mail-wm1-f69.google.com with SMTP id 5b1f17b1804b1-46e2c11b94cso8158055e9.3 for ; Thu, 02 Oct 2025 14:04:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1759439096; x=1760043896; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cwbGC/K9B4U3uycXerXPSUMJfx+iuM+3b1WmPO2FpvA=; b=Lla/DPB3WmnBpFo58glyl4E1EX6loBo97OZDqbimiK2yb+184P1kmNfbe/ttz7DQIU dYWeo1bUOoQV6YnXIy045g4h3YXEYUUskeexlto/34/ObsXE+2AfmGGuHZijUNDkOtmt tGD1bpDtn2tUC/d2he9dbo726UHcR0fduO9BU= X-Forwarded-Encrypted: i=1; AJvYcCWRQ1QxLWOoVSnMqS3b15rwiEOayKa/3lfahAUhyxtqvxF8IlSmGH1cWXVn4lVzU6Fb1ULBrD3RxzijoX4=@vger.kernel.org X-Received: by 2002:a05:600c:8b22:b0:45b:4a98:91cf with SMTP id 5b1f17b1804b1-46e71102657mr4393345e9.15.1759439096532; Thu, 02 Oct 2025 14:04:56 -0700 (PDT) X-Received: by 2002:a05:600c:8b22:b0:45b:4a98:91cf with SMTP id 5b1f17b1804b1-46e71102657mr4393165e9.15.1759439096023; Thu, 02 Oct 2025 14:04:56 -0700 (PDT) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e5c4c0321sm61711295e9.8.2025.10.02.14.04.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Oct 2025 14:04:55 -0700 (PDT) From: Kamal Dasu To: andersson@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: bcm-kernel-feedback-list@broadcom.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Kamal Dasu Subject: [PATCH 3/3] mmc: brcmstb: save and restore registers during PM Date: Thu, 2 Oct 2025 17:04:26 -0400 Message-Id: <20251002210426.2490368-4-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251002210426.2490368-1-kamal.dasu@broadcom.com> References: <20251002210426.2490368-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e Content-Type: text/plain; charset="utf-8" Added support to save and restore registers that are critical during PM. Signed-off-by: Kamal Dasu Reviewed-by: Florian Fainelli --- drivers/mmc/host/sdhci-brcmstb.c | 124 +++++++++++++++++++++++++++++-- 1 file changed, 119 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcm= stb.c index 0905b316a24b..ffa602a99ab7 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -24,7 +24,9 @@ #define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0) #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1) #define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE BIT(2) -#define BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY BIT(4) +#define BRCMSTB_MATCH_FLAGS_HAS_CFG_V1 BIT(3) +#define BRCMSTB_MATCH_FLAGS_HAS_CFG_V2 BIT(4) +#define BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY BIT(5) =20 #define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0) #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK BIT(1) @@ -38,19 +40,39 @@ #define SDIO_CFG_OP_DLY_DEFAULT 0x80000003 #define SDIO_CFG_CQ_CAPABILITY 0x4c #define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) +#define SDIO_CFG_SD_PIN_SEL 0x44 +#define SDIO_CFG_V1_SD_PIN_SEL 0x54 +#define SDIO_CFG_PHY_SW_MODE_0_RX_CTRL 0x7C #define SDIO_CFG_MAX_50MHZ_MODE 0x1ac #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) =20 +#define SDIO_BOOT_MAIN_CTL 0x0 + #define MMC_CAP_HSE_MASK (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V) /* Select all SD UHS type I SDR speed above 50MB/s */ #define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) =20 +enum cfg_core_ver { + SDIO_CFG_CORE_V1 =3D 1, + SDIO_CFG_CORE_V2, +}; + +struct sdhci_brcmstb_saved_regs { + u32 sd_pin_sel; + u32 phy_sw_mode0_rxctrl; + u32 max_50mhz_mode; + u32 boot_main_ctl; +}; + struct sdhci_brcmstb_priv { void __iomem *cfg_regs; + void __iomem *boot_regs; + struct sdhci_brcmstb_saved_regs saved_regs; unsigned int flags; struct clk *base_clk; u32 base_freq_hz; + void (*save_restore_regs)(struct mmc_host *mmc, int save); }; =20 struct brcmstb_match_priv { @@ -60,6 +82,69 @@ struct brcmstb_match_priv { const unsigned int flags; }; =20 +static void sdhci_brcmstb_save_regs(struct mmc_host *mmc, enum cfg_core_ve= r ver) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + struct sdhci_brcmstb_saved_regs *sr =3D &priv->saved_regs; + void __iomem *cr =3D priv->cfg_regs; + bool is_emmc =3D mmc->caps & MMC_CAP_NONREMOVABLE; + + /* save */ + if (is_emmc && priv->boot_regs) + sr->boot_main_ctl =3D readl(priv->boot_regs + SDIO_BOOT_MAIN_CTL); + + if (ver =3D=3D SDIO_CFG_CORE_V1) { + sr->sd_pin_sel =3D readl(cr + SDIO_CFG_V1_SD_PIN_SEL); + return; + } + + sr->sd_pin_sel =3D readl(cr + SDIO_CFG_SD_PIN_SEL); + sr->phy_sw_mode0_rxctrl =3D readl(cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL); + sr->max_50mhz_mode =3D readl(cr + SDIO_CFG_MAX_50MHZ_MODE); +} + +static void sdhci_brcmstb_restore_regs(struct mmc_host *mmc, + enum cfg_core_ver ver) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + struct sdhci_brcmstb_saved_regs *sr =3D &priv->saved_regs; + void __iomem *cr =3D priv->cfg_regs; + bool is_emmc =3D mmc->caps & MMC_CAP_NONREMOVABLE; + + /* restore */ + if (is_emmc && priv->boot_regs) + writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL); + + if (ver =3D=3D SDIO_CFG_CORE_V1) { + writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL); + return; + } + + writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL); + writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL); + writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE); +} + +static void sdhci_brcmstb_save_restore_regs_v1(struct mmc_host *mmc, int s= ave) +{ + if (save) + sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V1); + else + sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V1); +} + +static void sdhci_brcmstb_save_restore_regs_v2(struct mmc_host *mmc, int s= ave) +{ + if (save) + sdhci_brcmstb_save_regs(mmc, SDIO_CFG_CORE_V2); + else + sdhci_brcmstb_restore_regs(mmc, SDIO_CFG_CORE_V2); +} + static inline void enable_clock_gating(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); @@ -300,24 +385,33 @@ static struct brcmstb_match_priv match_priv_7425 =3D { .ops =3D &sdhci_brcmstb_ops, }; =20 -static struct brcmstb_match_priv match_priv_7445 =3D { +static struct brcmstb_match_priv match_priv_74371 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, .ops =3D &sdhci_brcmstb_ops, }; =20 +static struct brcmstb_match_priv match_priv_7445 =3D { + .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT | + BRCMSTB_MATCH_FLAGS_HAS_CFG_V1, + .ops =3D &sdhci_brcmstb_ops, +}; + static struct brcmstb_match_priv match_priv_72116 =3D { - .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, + .flags =3D BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT | + BRCMSTB_MATCH_FLAGS_HAS_CFG_V1, .ops =3D &sdhci_brcmstb_ops_72116, }; =20 static const struct brcmstb_match_priv match_priv_7216 =3D { - .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, + .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE | + BRCMSTB_MATCH_FLAGS_HAS_CFG_V2, .hs400es =3D sdhci_brcmstb_hs400es, .ops =3D &sdhci_brcmstb_ops_7216, }; =20 static struct brcmstb_match_priv match_priv_74165b0 =3D { - .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, + .flags =3D BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE | + BRCMSTB_MATCH_FLAGS_HAS_CFG_V2, .hs400es =3D sdhci_brcmstb_hs400es, .ops =3D &sdhci_brcmstb_ops_74165b0, }; @@ -325,6 +419,7 @@ static struct brcmstb_match_priv match_priv_74165b0 =3D= { static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] =3D { { .compatible =3D "brcm,bcm2712-sdhci", .data =3D &match_priv_2712 }, { .compatible =3D "brcm,bcm7425-sdhci", .data =3D &match_priv_7425 }, + { .compatible =3D "brcm,bcm74371-sdhci", .data =3D &match_priv_74371 }, { .compatible =3D "brcm,bcm7445-sdhci", .data =3D &match_priv_7445 }, { .compatible =3D "brcm,bcm72116-sdhci", .data =3D &match_priv_72116 }, { .compatible =3D "brcm,bcm7216-sdhci", .data =3D &match_priv_7216 }, @@ -441,6 +536,19 @@ static int sdhci_brcmstb_probe(struct platform_device = *pdev) if (res) goto err; =20 + /* map non-standard BOOT registers if present */ + if (host->mmc->caps & MMC_CAP_NONREMOVABLE) { + priv->boot_regs =3D devm_platform_get_and_ioremap_resource(pdev, 2, NULL= ); + if (IS_ERR(priv->boot_regs)) + priv->boot_regs =3D NULL; + } + + if (match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CFG_V1) + priv->save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v1; + + if (match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CFG_V2) + priv->save_restore_regs =3D sdhci_brcmstb_save_restore_regs_v2; + /* * Automatic clock gating does not work for SD cards that may * voltage switch so only enable it for non-removable devices. @@ -533,6 +641,9 @@ static int sdhci_brcmstb_suspend(struct device *dev) struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); int ret; =20 + if (priv->save_restore_regs) + priv->save_restore_regs(host->mmc, 1); + clk_disable_unprepare(priv->base_clk); if (host->mmc->caps2 & MMC_CAP2_CQE) { ret =3D cqhci_suspend(host->mmc); @@ -564,6 +675,9 @@ static int sdhci_brcmstb_resume(struct device *dev) ret =3D clk_set_rate(priv->base_clk, priv->base_freq_hz); } =20 + if (priv->save_restore_regs) + priv->save_restore_regs(host->mmc, 0); + if (host->mmc->caps2 & MMC_CAP2_CQE) ret =3D cqhci_resume(host->mmc); =20 --=20 2.34.1