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([223.233.78.22]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b62ce55205csm162917a12.18.2025.10.02.11.42.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Oct 2025 11:42:08 -0700 (PDT) From: Akshay Jindal To: dan@dlrobertson.com, jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org Cc: Akshay Jindal , shuah@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/5] iio: accel: bma400: Use index-based register addressing and lookup Date: Fri, 3 Oct 2025 00:11:04 +0530 Message-ID: <20251002184120.495193-4-akshayaj.lkd@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251002184120.495193-1-akshayaj.lkd@gmail.com> References: <20251002184120.495193-1-akshayaj.lkd@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce formula-based macros to compute GEN INTR configuration register addresses from the interrupt number and register index. This reduces the need for 22 explicit register macros to three base definitions. Add a centralized lookup table keyed by IIO event direction and replace get_gen_config_reg() with a helper integrated with this table. Apply these changes across the affected callbacks to ensure consistent access to generic interrupt registers. No functional changes are intended. Signed-off-by: Akshay Jindal --- drivers/iio/accel/bma400.h | 17 +++-- drivers/iio/accel/bma400_core.c | 131 +++++++++++++++++++------------- 2 files changed, 88 insertions(+), 60 deletions(-) diff --git a/drivers/iio/accel/bma400.h b/drivers/iio/accel/bma400.h index 13fe2e5a3175..48fcaeeb553d 100644 --- a/drivers/iio/accel/bma400.h +++ b/drivers/iio/accel/bma400.h @@ -91,6 +91,11 @@ #define BMA400_INT_CONFIG0_GEN2_MASK BIT(3) #define BMA400_INT_CONFIG0_DRDY_MASK BIT(7) =20 +enum bma400_generic_intr { + BMA400_GEN1_INTR =3D 1, + BMA400_GEN2_INTR, +}; + #define BMA400_INT_CONFIG1_REG 0x20 #define BMA400_INT_CONFIG1_STEP_INT_MASK BIT(0) #define BMA400_INT_CONFIG1_S_TAP_MASK BIT(2) @@ -103,8 +108,12 @@ #define BMA400_TWO_BITS_MASK GENMASK(1, 0) =20 /* Generic interrupts register */ -#define BMA400_GEN1INT_CONFIG0_REG 0x3f -#define BMA400_GEN2INT_CONFIG0_REG 0x4A +#define BMA400_GENINT_CONFIG_REG_BASE 0x3f +#define BMA400_NUM_GENINT_CONFIG_REGS 11 +#define BMA400_GENINT_CONFIG_REG(gen_intr, config_idx) \ + (BMA400_GENINT_CONFIG_REG_BASE + \ + (gen_intr - 1) * BMA400_NUM_GENINT_CONFIG_REGS + \ + (config_idx)) #define BMA400_GENINT_CONFIG0_HYST_MASK GENMASK(1, 0) #define BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK GENMASK(3, 2) #define BMA400_GENINT_CONFIG0_DATA_SRC_MASK BIT(4) @@ -138,10 +147,6 @@ enum bma400_detect_criterion { BMA400_DETECT_ACTIVITY, }; =20 -#define BMA400_GEN_CONFIG2_OFF 0x02 -#define BMA400_GEN_CONFIG3_OFF 0x03 -#define BMA400_GEN_CONFIG31_OFF 0x04 - /* TAP config registers */ #define BMA400_TAP_CONFIG_REG 0x57 #define BMA400_TAP_CONFIG_SEN_MASK GENMASK(2, 0) diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_cor= e.c index 58c378ba9931..a0e994f9882b 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -121,6 +121,41 @@ struct bma400_data { __be16 duration; }; =20 +struct bma400_genintr_info { + enum bma400_generic_intr genintr; + unsigned int intrmask; + enum iio_event_direction dir; + enum bma400_detect_criterion detect_mode; +}; + +/* Lookup struct for determining GEN1/GEN2 based on dir */ +static const struct bma400_genintr_info bma400_genintrs[] =3D { + [IIO_EV_DIR_RISING] =3D { + .genintr =3D BMA400_GEN1_INTR, + .intrmask =3D BMA400_INT_CONFIG0_GEN1_MASK, + .dir =3D IIO_EV_DIR_RISING, + .detect_mode =3D BMA400_DETECT_ACTIVITY, + }, + [IIO_EV_DIR_FALLING] =3D { + .genintr =3D BMA400_GEN2_INTR, + .intrmask =3D BMA400_INT_CONFIG0_GEN2_MASK, + .dir =3D IIO_EV_DIR_FALLING, + .detect_mode =3D BMA400_DETECT_INACTIVITY, + } +}; + +static inline const struct bma400_genintr_info * +get_bma400_genintr_info(enum iio_event_direction dir) +{ + switch (dir) { + case IIO_EV_DIR_RISING: + case IIO_EV_DIR_FALLING: + return &bma400_genintrs[dir]; + default: + return NULL; + }; +} + static bool bma400_is_writable_reg(struct device *dev, unsigned int reg) { switch (reg) { @@ -1159,32 +1194,22 @@ static int bma400_activity_event_en(struct bma400_d= ata *data, enum iio_event_direction dir, int state) { - int ret, reg, msk, value; - int field_value =3D 0; + int ret; + unsigned int intrmask, regval; + enum bma400_generic_intr genintr; + enum bma400_detect_criterion detect_criterion; + const struct bma400_genintr_info *bma400_genintr; =20 - switch (dir) { - case IIO_EV_DIR_RISING: - reg =3D BMA400_GEN1INT_CONFIG0_REG; - msk =3D BMA400_INT_CONFIG0_GEN1_MASK; - value =3D FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X= _OR_Y_OR_Z) | - FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_ACTIVIT= Y); - set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN1_MASK, - FIELD_PREP(BMA400_INT_CONFIG0_GEN1_MASK, state)); - break; - case IIO_EV_DIR_FALLING: - reg =3D BMA400_GEN2INT_CONFIG0_REG; - msk =3D BMA400_INT_CONFIG0_GEN2_MASK; - value =3D FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X= _OR_Y_OR_Z) | - FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_INACTIV= ITY); - set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN2_MASK, - FIELD_PREP(BMA400_INT_CONFIG0_GEN2_MASK, state)); - break; - default: + bma400_genintr =3D get_bma400_genintr_info(dir); + if (!bma400_genintr) return -EINVAL; - } + + genintr =3D bma400_genintr->genintr; + detect_criterion =3D bma400_genintr->detect_mode; + intrmask =3D bma400_genintr->intrmask; =20 /* Enabling all axis for interrupt evaluation */ - ret =3D regmap_write(data->regmap, reg, + ret =3D regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 0), BMA400_GENINT_CONFIG0_X_EN_MASK | BMA400_GENINT_CONFIG0_Y_EN_MASK | BMA400_GENINT_CONFIG0_Z_EN_MASK| @@ -1195,31 +1220,32 @@ static int bma400_activity_event_en(struct bma400_d= ata *data, return ret; =20 /* OR combination of all axis for interrupt evaluation */ - ret =3D regmap_write(data->regmap, reg + BMA400_GEN_CONFIG1_OFF, value); + regval =3D FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X= _OR_Y_OR_Z) | + FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, detect_criterion); + ret =3D regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 1), = regval); if (ret) return ret; =20 /* Initial value to avoid interrupts while enabling*/ - ret =3D regmap_write(data->regmap, reg + BMA400_GEN_CONFIG2_OFF, 0x0A); + ret =3D regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 2), = 0x0A); if (ret) return ret; =20 /* Initial duration value to avoid interrupts while enabling*/ - ret =3D regmap_write(data->regmap, reg + BMA400_GEN_CONFIG31_OFF, 0x0F); + ret =3D regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 4), = 0x0F); if (ret) return ret; =20 - ret =3D regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, msk, - field_value); + regval =3D state ? intrmask : 0; + ret =3D regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, intrmask, r= egval); if (ret) return ret; =20 - ret =3D regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, msk, - field_value); + ret =3D regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, intrmask= , regval); if (ret) return ret; =20 - set_mask_bits(&data->generic_event_en, msk, field_value); + set_mask_bits(&data->generic_event_en, intrmask, regval); return 0; } =20 @@ -1344,18 +1370,6 @@ static int bma400_write_event_config(struct iio_dev = *indio_dev, } } =20 -static int get_gen_config_reg(enum iio_event_direction dir) -{ - switch (dir) { - case IIO_EV_DIR_FALLING: - return BMA400_GEN2INT_CONFIG0_REG; - case IIO_EV_DIR_RISING: - return BMA400_GEN1INT_CONFIG0_REG; - default: - return -EINVAL; - } -} - static int bma400_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, enum iio_event_type type, @@ -1364,22 +1378,25 @@ static int bma400_read_event_value(struct iio_dev *= indio_dev, int *val, int *val2) { struct bma400_data *data =3D iio_priv(indio_dev); - int ret, reg, reg_val, raw; + int ret, reg_val, raw; + enum bma400_generic_intr genintr; + const struct bma400_genintr_info *bma400_genintr; =20 if (chan->type !=3D IIO_ACCEL) return -EINVAL; =20 switch (type) { case IIO_EV_TYPE_MAG: - reg =3D get_gen_config_reg(dir); - if (reg < 0) + bma400_genintr =3D get_bma400_genintr_info(dir); + if (!bma400_genintr) return -EINVAL; + genintr =3D bma400_genintr->genintr; =20 *val2 =3D 0; switch (info) { case IIO_EV_INFO_VALUE: ret =3D regmap_read(data->regmap, - reg + BMA400_GEN_CONFIG2_OFF, + BMA400_GENINT_CONFIG_REG(genintr, 2), val); if (ret) return ret; @@ -1387,7 +1404,7 @@ static int bma400_read_event_value(struct iio_dev *in= dio_dev, case IIO_EV_INFO_PERIOD: mutex_lock(&data->mutex); ret =3D regmap_bulk_read(data->regmap, - reg + BMA400_GEN_CONFIG3_OFF, + BMA400_GENINT_CONFIG_REG(genintr, 3), &data->duration, sizeof(data->duration)); if (ret) { @@ -1398,7 +1415,9 @@ static int bma400_read_event_value(struct iio_dev *in= dio_dev, mutex_unlock(&data->mutex); return IIO_VAL_INT; case IIO_EV_INFO_HYSTERESIS: - ret =3D regmap_read(data->regmap, reg, val); + ret =3D regmap_read(data->regmap, + BMA400_GENINT_CONFIG_REG(genintr, 0), + val); if (ret) return ret; *val =3D FIELD_GET(BMA400_GENINT_CONFIG0_HYST_MASK, *val); @@ -1452,16 +1471,19 @@ static int bma400_write_event_value(struct iio_dev = *indio_dev, int val, int val2) { struct bma400_data *data =3D iio_priv(indio_dev); - int reg, ret, raw; + int ret, raw; + enum bma400_generic_intr genintr; + const struct bma400_genintr_info *bma400_genintr; =20 if (chan->type !=3D IIO_ACCEL) return -EINVAL; =20 switch (type) { case IIO_EV_TYPE_MAG: - reg =3D get_gen_config_reg(dir); - if (reg < 0) + bma400_genintr =3D get_bma400_genintr_info(dir); + if (!bma400_genintr) return -EINVAL; + genintr =3D bma400_genintr->genintr; =20 switch (info) { case IIO_EV_INFO_VALUE: @@ -1469,7 +1491,7 @@ static int bma400_write_event_value(struct iio_dev *i= ndio_dev, return -EINVAL; =20 return regmap_write(data->regmap, - reg + BMA400_GEN_CONFIG2_OFF, + BMA400_GENINT_CONFIG_REG(genintr, 2), val); case IIO_EV_INFO_PERIOD: if (val < 1 || val > 65535) @@ -1478,7 +1500,7 @@ static int bma400_write_event_value(struct iio_dev *i= ndio_dev, mutex_lock(&data->mutex); put_unaligned_be16(val, &data->duration); ret =3D regmap_bulk_write(data->regmap, - reg + BMA400_GEN_CONFIG3_OFF, + BMA400_GENINT_CONFIG_REG(genintr, 3), &data->duration, sizeof(data->duration)); mutex_unlock(&data->mutex); @@ -1487,7 +1509,8 @@ static int bma400_write_event_value(struct iio_dev *i= ndio_dev, if (val < 0 || val > 3) return -EINVAL; =20 - return regmap_update_bits(data->regmap, reg, + return regmap_update_bits(data->regmap, + BMA400_GENINT_CONFIG_REG(genintr, 0), BMA400_GENINT_CONFIG0_HYST_MASK, FIELD_PREP(BMA400_GENINT_CONFIG0_HYST_MASK, val)); --=20 2.43.0