From nobody Sun Feb 8 09:37:49 2026 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA8962798EB for ; Thu, 2 Oct 2025 18:41:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759430517; cv=none; b=q6LqeWf8BtqASRtQe31ttCPYulO3i+2CmQBzk4Jgchfd0zXoPiV3QSuj4bPdAXn/MWZv/lWNnEDkqkqlfrp0Fcn9edXOGkWfuc9jsUfh4KZSv+5vdUY5C2y3CKXRW4tXvdA/yMAD6rT81jHw+uORwbjdgi3aOqcQMbwJdBV0cP8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759430517; c=relaxed/simple; bh=uN0/Osr1oyFn4mzHg77jsE3UwiQcSspVPgEqR4FAYEM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QbsaFtcBB5NN+LpULAH1uFYiZtcbyoC1F3TRdwBngtNPD3GBB0bjLhHZ7cL2QCaxtWTOeNdnmH8hvlqVDQLx80CYB/LPc7jKkZN/DE+CY7/wXa+jFepv7BVHsTvoEJczLJWRXt0UdxI4XavQHGMbpW0mk1+9mdsF3UGIdK7Fqi0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=eJri74PT; arc=none smtp.client-ip=209.85.210.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eJri74PT" Received: by mail-pf1-f169.google.com with SMTP id d2e1a72fcca58-7811a5ec5b6so2041893b3a.1 for ; Thu, 02 Oct 2025 11:41:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1759430514; x=1760035314; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GaapfISAKd+MIReLhndo1piHFwvjOUQGdV27T6AdMYA=; b=eJri74PTQytvQbzYnH5GItdZ91t4+Y4eKGVnOm1kKdHb29Zvs+kWPyjCuoRD8tO+Gy z9np6gDrlmpC4LH2TllMqJlHQ+z1JLGPP+nO6TR7QHiEilgHX3ALOVvmUQOBYygOwjtN Up5EGe+fCluRJysOt2A8gla4kmiizfXSEtADtxMIqtjmysqYnl2rec0UioR2Wtrij9S2 Saaqz+1tcXdmzimowyKOzZ4h4N9U4GDIdrm3xbXBQLvYFiIBnQdNK6NoiBqyAA9YqKqa NT0W+y9Zl5QITuJiALLarRj1DU3YU39su94JyS3+eWUspHUnJcik9hksYIsJ1Ppr2VIP kEfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759430514; x=1760035314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GaapfISAKd+MIReLhndo1piHFwvjOUQGdV27T6AdMYA=; b=lMFa/L4EAaomGLMNFmF6S2QGFM0KfCvWGaICOTnmDC4I8uQkFbmw4V6D8qR8TtoE/j jdraUnE2d9uqWA/HrdRo6nun9r85Evsht+ZVA/qadz8XuKSG1u5LHZ33P+mY8Ozj6zyR joU18s9ARkUmFpXVSZLQ9IulWgu30XlUW/3KQ17nzMPTykcF0u5ESSDP9pQmCHfB6bTF xjhAk5TQlgYz7wD8EP/HrW2fYdJaJCmY6PQtkonHuUAneH+NbkDGNNG/r07UENrQvqEb 0heWfBxvCyBZRJ+y4PKmmkchj16FDSmPVoBUHH9PVD8bnCD3e3ow2mlyCrzyHY8G71N3 DAgA== X-Forwarded-Encrypted: i=1; AJvYcCW2jBscXr2D5rLfNaf80eeTlUCFqmpTBCFPWajcOn7rs0sPBJ9Mk01fMEelEKu2Oc81g7Dga1AZxf5EteA=@vger.kernel.org X-Gm-Message-State: AOJu0Yz6h30vHo0M4us0cj2xCS26nIbfUsJY6uRLBrWNiEcZtLs7xq91 hPCfN4ZawEqViAPNdfDs99TIMcFMG7zk/QmkEwKikc2pLofe17hzptsN X-Gm-Gg: ASbGnctAa4rVmDRgAxpGPxKeZlLmoJRQnH/0BkyYmcaTKHNVC1l4DclGctFmrPDV3BN rxcigVu1uApcflF/+9v1AjyLFdlVteS7G58kkEZkkpj3S5IPg00T8tll5CwabT+kKDtXbAyR2ao /wyX5hIMnyG6aWMNiDFbYREU1UE1xs+TLWk2c3FEo1mOAiWaWxjwyVtwdGEU2tHV9zeNYmJaq46 jFYYQ/j0aYKUwpwod52DXZeiUeOQ0gAJ2eEjIpllt5/TZe1+0LWfG78bEApzl5UvU+F8ugLqR4a NMPV5HzY4pKNZSflEQ2IeLMQyWnqZWGWed4U3WNIdRfQGvXZCPRmi4FnmNjXPbTW10/Yg/JxP8e zExU0JeGfNV5GCzZmJJ3wJygmILsryVentDJxLsvpTxluNK1sn8BArEzU X-Google-Smtp-Source: AGHT+IEFKTmkLart7fAKOPfnqqQ7zEOqzJFugPn1K2QewlAC7UPAVH2ZZLzRNudHCcWcidoZKQGaCg== X-Received: by 2002:a05:6a20:3d05:b0:2bd:2798:7ae5 with SMTP id adf61e73a8af0-32a24dc7856mr6043393637.19.1759430513728; Thu, 02 Oct 2025 11:41:53 -0700 (PDT) Received: from akshayaj-lenovo.. ([223.233.78.22]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b62ce55205csm162917a12.18.2025.10.02.11.41.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Oct 2025 11:41:53 -0700 (PDT) From: Akshay Jindal To: dan@dlrobertson.com, jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org Cc: Akshay Jindal , shuah@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/5] iio: accel: bma400: Reorganize and rename register and field macros Date: Fri, 3 Oct 2025 00:11:02 +0530 Message-ID: <20251002184120.495193-2-akshayaj.lkd@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251002184120.495193-1-akshayaj.lkd@gmail.com> References: <20251002184120.495193-1-akshayaj.lkd@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reorganize register and field macros to improve consistency with the datasheet and naming style: - Move field macros next to their corresponding register macros - Reorder register macros to follow address order from the datasheet - Rename field macros to include the register name in the macro name - Add a _REG suffix to register macros where missing No functional changes are intended. Signed-off-by: Akshay Jindal --- drivers/iio/accel/bma400.h | 110 +++++++++-------- drivers/iio/accel/bma400_core.c | 212 ++++++++++++++++---------------- 2 files changed, 163 insertions(+), 159 deletions(-) diff --git a/drivers/iio/accel/bma400.h b/drivers/iio/accel/bma400.h index 932358b45f17..ae3411c090c9 100644 --- a/drivers/iio/accel/bma400.h +++ b/drivers/iio/accel/bma400.h @@ -16,31 +16,37 @@ * Read-Only Registers */ =20 +/* Chip ID of BMA 400 devices found in the chip ID register. */ +#define BMA400_ID_REG_VAL 0x90 + /* Status and ID registers */ #define BMA400_CHIP_ID_REG 0x00 #define BMA400_ERR_REG 0x02 #define BMA400_STATUS_REG 0x03 =20 /* Acceleration registers */ -#define BMA400_X_AXIS_LSB_REG 0x04 -#define BMA400_X_AXIS_MSB_REG 0x05 -#define BMA400_Y_AXIS_LSB_REG 0x06 -#define BMA400_Y_AXIS_MSB_REG 0x07 -#define BMA400_Z_AXIS_LSB_REG 0x08 -#define BMA400_Z_AXIS_MSB_REG 0x09 +#define BMA400_ACC_X_LSB_REG 0x04 +#define BMA400_ACC_X_MSB_REG 0x05 +#define BMA400_ACC_Y_LSB_REG 0x06 +#define BMA400_ACC_Y_MSB_REG 0x07 +#define BMA400_ACC_Z_LSB_REG 0x08 +#define BMA400_ACC_Z_MSB_REG 0x09 =20 /* Sensor time registers */ -#define BMA400_SENSOR_TIME0 0x0a -#define BMA400_SENSOR_TIME1 0x0b -#define BMA400_SENSOR_TIME2 0x0c +#define BMA400_SENSOR_TIME0_REG 0x0a +#define BMA400_SENSOR_TIME1_REG 0x0b +#define BMA400_SENSOR_TIME2_REG 0x0c =20 /* Event and interrupt registers */ #define BMA400_EVENT_REG 0x0d + #define BMA400_INT_STAT0_REG 0x0e #define BMA400_INT_STAT1_REG 0x0f #define BMA400_INT_STAT2_REG 0x10 -#define BMA400_INT12_MAP_REG 0x23 -#define BMA400_INT_ENG_OVRUN_MSK BIT(4) +#define BMA400_ENG_OVRUN_INT_STAT_MASK BIT(4) +#define BMA400_STEP_INT_STAT_MASK GENMASK(9, 8) +#define BMA400_S_TAP_INT_STAT_MASK BIT(10) +#define BMA400_D_TAP_INT_STAT_MASK BIT(11) =20 /* Temperature register */ #define BMA400_TEMP_DATA_REG 0x11 @@ -55,70 +61,68 @@ #define BMA400_STEP_CNT1_REG 0x16 #define BMA400_STEP_CNT3_REG 0x17 #define BMA400_STEP_STAT_REG 0x18 -#define BMA400_STEP_INT_MSK BIT(0) #define BMA400_STEP_RAW_LEN 0x03 -#define BMA400_STEP_STAT_MASK GENMASK(9, 8) =20 /* * Read-write configuration registers */ -#define BMA400_ACC_CONFIG0_REG 0x19 -#define BMA400_ACC_CONFIG1_REG 0x1a +#define BMA400_ACC_CONFIG0_REG 0x19 +#define BMA400_ACC_CONFIG0_LP_OSR_MASK GENMASK(6, 5) +#define BMA400_LP_OSR_SHIFT 5 + +#define BMA400_ACC_CONFIG1_REG 0x1a +#define BMA400_ACC_CONFIG1_ODR_MASK GENMASK(3, 0) +#define BMA400_ACC_CONFIG1_ODR_MIN_RAW 0x05 +#define BMA400_ACC_CONFIG1_ODR_LP_RAW 0x06 +#define BMA400_ACC_CONFIG1_ODR_MAX_RAW 0x0b +#define BMA400_ACC_CONFIG1_ODR_MAX_HZ 800 +#define BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ 25 +#define BMA400_ACC_CONFIG1_ODR_MIN_HZ 12 +#define BMA400_ACC_CONFIG1_NP_OSR_MASK GENMASK(5, 4) +#define BMA400_NP_OSR_SHIFT 4 +#define BMA400_ACC_CONFIG1_ACC_RANGE_MASK GENMASK(7, 6) +#define BMA400_ACC_RANGE_SHIFT 6 + #define BMA400_ACC_CONFIG2_REG 0x1b -#define BMA400_CMD_REG 0x7e =20 /* Interrupt registers */ #define BMA400_INT_CONFIG0_REG 0x1f +#define BMA400_INT_CONFIG0_GEN1_MASK BIT(2) +#define BMA400_INT_CONFIG0_GEN2_MASK BIT(3) +#define BMA400_INT_CONFIG0_DRDY_MASK BIT(7) + #define BMA400_INT_CONFIG1_REG 0x20 +#define BMA400_INT_CONFIG1_STEP_INT_MASK BIT(0) +#define BMA400_INT_CONFIG1_S_TAP_MASK BIT(2) +#define BMA400_INT_CONFIG1_D_TAP_MASK BIT(3) + #define BMA400_INT1_MAP_REG 0x21 +#define BMA400_INT12_MAP_REG 0x23 #define BMA400_INT_IO_CTRL_REG 0x24 -#define BMA400_INT_DRDY_MSK BIT(7) - -/* Chip ID of BMA 400 devices found in the chip ID register. */ -#define BMA400_ID_REG_VAL 0x90 - -#define BMA400_LP_OSR_SHIFT 5 -#define BMA400_NP_OSR_SHIFT 4 -#define BMA400_SCALE_SHIFT 6 =20 #define BMA400_TWO_BITS_MASK GENMASK(1, 0) -#define BMA400_LP_OSR_MASK GENMASK(6, 5) -#define BMA400_NP_OSR_MASK GENMASK(5, 4) -#define BMA400_ACC_ODR_MASK GENMASK(3, 0) -#define BMA400_ACC_SCALE_MASK GENMASK(7, 6) - -#define BMA400_ACC_ODR_MIN_RAW 0x05 -#define BMA400_ACC_ODR_LP_RAW 0x06 -#define BMA400_ACC_ODR_MAX_RAW 0x0b - -#define BMA400_ACC_ODR_MAX_HZ 800 -#define BMA400_ACC_ODR_MIN_WHOLE_HZ 25 -#define BMA400_ACC_ODR_MIN_HZ 12 =20 /* Generic interrupts register */ -#define BMA400_GEN1INT_CONFIG0 0x3f -#define BMA400_GEN2INT_CONFIG0 0x4A +#define BMA400_GEN1INT_CONFIG0_REG 0x3f +#define BMA400_GEN2INT_CONFIG0_REG 0x4A +#define BMA400_GENINT_CONFIG0_HYST_MASK GENMASK(1, 0) + #define BMA400_GEN_CONFIG1_OFF 0x01 #define BMA400_GEN_CONFIG2_OFF 0x02 #define BMA400_GEN_CONFIG3_OFF 0x03 #define BMA400_GEN_CONFIG31_OFF 0x04 -#define BMA400_INT_GEN1_MSK BIT(2) -#define BMA400_INT_GEN2_MSK BIT(3) -#define BMA400_GEN_HYST_MSK GENMASK(1, 0) =20 /* TAP config registers */ -#define BMA400_TAP_CONFIG 0x57 -#define BMA400_TAP_CONFIG1 0x58 -#define BMA400_S_TAP_MSK BIT(2) -#define BMA400_D_TAP_MSK BIT(3) -#define BMA400_INT_S_TAP_MSK BIT(10) -#define BMA400_INT_D_TAP_MSK BIT(11) -#define BMA400_TAP_SEN_MSK GENMASK(2, 0) -#define BMA400_TAP_TICSTH_MSK GENMASK(1, 0) -#define BMA400_TAP_QUIET_MSK GENMASK(3, 2) -#define BMA400_TAP_QUIETDT_MSK GENMASK(5, 4) +#define BMA400_TAP_CONFIG_REG 0x57 +#define BMA400_TAP_CONFIG_SEN_MASK GENMASK(2, 0) + +#define BMA400_TAP_CONFIG1_REG 0x58 +#define BMA400_TAP_CONFIG1_TICSTH_MASK GENMASK(1, 0) +#define BMA400_TAP_CONFIG1_QUIET_MASK GENMASK(3, 2) +#define BMA400_TAP_CONFIG1_QUIETDT_MASK GENMASK(5, 4) #define BMA400_TAP_TIM_LIST_LEN 4 =20 +#define BMA400_CMD_REG 0x7e /* * BMA400_SCALE_MIN macro value represents m/s^2 for 1 LSB before * converting to micro values for +-2g range. @@ -138,8 +142,8 @@ * To select +-8g =3D 9577 << 2 =3D raw value to write is 2. * To select +-16g =3D 9577 << 3 =3D raw value to write is 3. */ -#define BMA400_SCALE_MIN 9577 -#define BMA400_SCALE_MAX 76617 +#define BMA400_ACC_SCALE_MIN 9577 +#define BMA400_ACC_SCALE_MAX 76617 =20 extern const struct regmap_config bma400_regmap_config; =20 diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_cor= e.c index 85e23badf733..35d2b90425f8 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -127,15 +127,15 @@ static bool bma400_is_writable_reg(struct device *dev= , unsigned int reg) case BMA400_CHIP_ID_REG: case BMA400_ERR_REG: case BMA400_STATUS_REG: - case BMA400_X_AXIS_LSB_REG: - case BMA400_X_AXIS_MSB_REG: - case BMA400_Y_AXIS_LSB_REG: - case BMA400_Y_AXIS_MSB_REG: - case BMA400_Z_AXIS_LSB_REG: - case BMA400_Z_AXIS_MSB_REG: - case BMA400_SENSOR_TIME0: - case BMA400_SENSOR_TIME1: - case BMA400_SENSOR_TIME2: + case BMA400_ACC_X_LSB_REG: + case BMA400_ACC_X_MSB_REG: + case BMA400_ACC_Y_LSB_REG: + case BMA400_ACC_Y_MSB_REG: + case BMA400_ACC_Z_LSB_REG: + case BMA400_ACC_Z_MSB_REG: + case BMA400_SENSOR_TIME0_REG: + case BMA400_SENSOR_TIME1_REG: + case BMA400_SENSOR_TIME2_REG: case BMA400_EVENT_REG: case BMA400_INT_STAT0_REG: case BMA400_INT_STAT1_REG: @@ -159,15 +159,15 @@ static bool bma400_is_volatile_reg(struct device *dev= , unsigned int reg) switch (reg) { case BMA400_ERR_REG: case BMA400_STATUS_REG: - case BMA400_X_AXIS_LSB_REG: - case BMA400_X_AXIS_MSB_REG: - case BMA400_Y_AXIS_LSB_REG: - case BMA400_Y_AXIS_MSB_REG: - case BMA400_Z_AXIS_LSB_REG: - case BMA400_Z_AXIS_MSB_REG: - case BMA400_SENSOR_TIME0: - case BMA400_SENSOR_TIME1: - case BMA400_SENSOR_TIME2: + case BMA400_ACC_X_LSB_REG: + case BMA400_ACC_X_MSB_REG: + case BMA400_ACC_Y_LSB_REG: + case BMA400_ACC_Y_MSB_REG: + case BMA400_ACC_Z_LSB_REG: + case BMA400_ACC_Z_MSB_REG: + case BMA400_SENSOR_TIME0_REG: + case BMA400_SENSOR_TIME1_REG: + case BMA400_SENSOR_TIME2_REG: case BMA400_EVENT_REG: case BMA400_INT_STAT0_REG: case BMA400_INT_STAT1_REG: @@ -275,11 +275,11 @@ static ssize_t in_accel_gesture_tap_maxtomin_time_sho= w(struct device *dev, struct bma400_data *data =3D iio_priv(indio_dev); int ret, reg_val, raw, vals[2]; =20 - ret =3D regmap_read(data->regmap, BMA400_TAP_CONFIG1, ®_val); + ret =3D regmap_read(data->regmap, BMA400_TAP_CONFIG1_REG, ®_val); if (ret) return ret; =20 - raw =3D FIELD_GET(BMA400_TAP_TICSTH_MSK, reg_val); + raw =3D FIELD_GET(BMA400_TAP_CONFIG1_TICSTH_MASK, reg_val); vals[0] =3D 0; vals[1] =3D tap_max2min_time[raw]; =20 @@ -302,9 +302,9 @@ static ssize_t in_accel_gesture_tap_maxtomin_time_store= (struct device *dev, if (raw < 0) return -EINVAL; =20 - ret =3D regmap_update_bits(data->regmap, BMA400_TAP_CONFIG1, - BMA400_TAP_TICSTH_MSK, - FIELD_PREP(BMA400_TAP_TICSTH_MSK, raw)); + ret =3D regmap_update_bits(data->regmap, BMA400_TAP_CONFIG1_REG, + BMA400_TAP_CONFIG1_TICSTH_MASK, + FIELD_PREP(BMA400_TAP_CONFIG1_TICSTH_MASK, raw)); if (ret) return ret; =20 @@ -449,13 +449,13 @@ static int bma400_get_accel_reg(struct bma400_data *d= ata, =20 switch (chan->channel2) { case IIO_MOD_X: - lsb_reg =3D BMA400_X_AXIS_LSB_REG; + lsb_reg =3D BMA400_ACC_X_LSB_REG; break; case IIO_MOD_Y: - lsb_reg =3D BMA400_Y_AXIS_LSB_REG; + lsb_reg =3D BMA400_ACC_Y_LSB_REG; break; case IIO_MOD_Z: - lsb_reg =3D BMA400_Z_AXIS_LSB_REG; + lsb_reg =3D BMA400_ACC_Z_LSB_REG; break; default: dev_err(data->dev, "invalid axis channel modifier\n"); @@ -475,8 +475,8 @@ static int bma400_get_accel_reg(struct bma400_data *dat= a, static void bma400_output_data_rate_from_raw(int raw, unsigned int *val, unsigned int *val2) { - *val =3D BMA400_ACC_ODR_MAX_HZ >> (BMA400_ACC_ODR_MAX_RAW - raw); - if (raw > BMA400_ACC_ODR_MIN_RAW) + *val =3D BMA400_ACC_CONFIG1_ODR_MAX_HZ >> (BMA400_ACC_CONFIG1_ODR_MAX_RAW= - raw); + if (raw > BMA400_ACC_CONFIG1_ODR_MIN_RAW) *val2 =3D 0; else *val2 =3D 500000; @@ -494,7 +494,7 @@ static int bma400_get_accel_output_data_rate(struct bma= 400_data *data) * Runs at a fixed rate in low-power mode. See section 4.3 * in the datasheet. */ - bma400_output_data_rate_from_raw(BMA400_ACC_ODR_LP_RAW, + bma400_output_data_rate_from_raw(BMA400_ACC_CONFIG1_ODR_LP_RAW, &data->sample_freq.hz, &data->sample_freq.uhz); return 0; @@ -507,9 +507,9 @@ static int bma400_get_accel_output_data_rate(struct bma= 400_data *data) if (ret) goto error; =20 - odr =3D val & BMA400_ACC_ODR_MASK; - if (odr < BMA400_ACC_ODR_MIN_RAW || - odr > BMA400_ACC_ODR_MAX_RAW) { + odr =3D val & BMA400_ACC_CONFIG1_ODR_MASK; + if (odr < BMA400_ACC_CONFIG1_ODR_MIN_RAW || + odr > BMA400_ACC_CONFIG1_ODR_MAX_RAW) { ret =3D -EINVAL; goto error; } @@ -539,19 +539,19 @@ static int bma400_set_accel_output_data_rate(struct b= ma400_data *data, unsigned int val; int ret; =20 - if (hz >=3D BMA400_ACC_ODR_MIN_WHOLE_HZ) { - if (uhz || hz > BMA400_ACC_ODR_MAX_HZ) + if (hz >=3D BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ) { + if (uhz || hz > BMA400_ACC_CONFIG1_ODR_MAX_HZ) return -EINVAL; =20 /* Note this works because MIN_WHOLE_HZ is odd */ idx =3D __ffs(hz); =20 - if (hz >> idx !=3D BMA400_ACC_ODR_MIN_WHOLE_HZ) + if (hz >> idx !=3D BMA400_ACC_CONFIG1_ODR_MIN_WHOLE_HZ) return -EINVAL; =20 - idx +=3D BMA400_ACC_ODR_MIN_RAW + 1; - } else if (hz =3D=3D BMA400_ACC_ODR_MIN_HZ && uhz =3D=3D 500000) { - idx =3D BMA400_ACC_ODR_MIN_RAW; + idx +=3D BMA400_ACC_CONFIG1_ODR_MIN_RAW + 1; + } else if (hz =3D=3D BMA400_ACC_CONFIG1_ODR_MIN_HZ && uhz =3D=3D 500000) { + idx =3D BMA400_ACC_CONFIG1_ODR_MIN_RAW; } else { return -EINVAL; } @@ -561,7 +561,7 @@ static int bma400_set_accel_output_data_rate(struct bma= 400_data *data, return ret; =20 /* preserve the range and normal mode osr */ - odr =3D (~BMA400_ACC_ODR_MASK & val) | idx; + odr =3D (~BMA400_ACC_CONFIG1_ODR_MASK & val) | idx; =20 ret =3D regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, odr); if (ret) @@ -592,7 +592,7 @@ static int bma400_get_accel_oversampling_ratio(struct b= ma400_data *data) return ret; } =20 - osr =3D (val & BMA400_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT; + osr =3D (val & BMA400_ACC_CONFIG0_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT; =20 data->oversampling_ratio =3D osr; return 0; @@ -603,7 +603,7 @@ static int bma400_get_accel_oversampling_ratio(struct b= ma400_data *data) return ret; } =20 - osr =3D (val & BMA400_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT; + osr =3D (val & BMA400_ACC_CONFIG1_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT; =20 data->oversampling_ratio =3D osr; return 0; @@ -637,7 +637,7 @@ static int bma400_set_accel_oversampling_ratio(struct b= ma400_data *data, return ret; =20 ret =3D regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG, - (acc_config & ~BMA400_LP_OSR_MASK) | + (acc_config & ~BMA400_ACC_CONFIG0_LP_OSR_MASK) | (val << BMA400_LP_OSR_SHIFT)); if (ret) { dev_err(data->dev, "Failed to write out OSR\n"); @@ -653,7 +653,7 @@ static int bma400_set_accel_oversampling_ratio(struct b= ma400_data *data, return ret; =20 ret =3D regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, - (acc_config & ~BMA400_NP_OSR_MASK) | + (acc_config & ~BMA400_ACC_CONFIG1_NP_OSR_MASK) | (val << BMA400_NP_OSR_SHIFT)); if (ret) { dev_err(data->dev, "Failed to write out OSR\n"); @@ -679,7 +679,7 @@ static int bma400_accel_scale_to_raw(struct bma400_data= *data, /* Note this works because BMA400_SCALE_MIN is odd */ raw =3D __ffs(val); =20 - if (val >> raw !=3D BMA400_SCALE_MIN) + if (val >> raw !=3D BMA400_ACC_SCALE_MIN) return -EINVAL; =20 return raw; @@ -695,11 +695,11 @@ static int bma400_get_accel_scale(struct bma400_data = *data) if (ret) return ret; =20 - raw_scale =3D (val & BMA400_ACC_SCALE_MASK) >> BMA400_SCALE_SHIFT; + raw_scale =3D (val & BMA400_ACC_CONFIG1_ACC_RANGE_MASK) >> BMA400_ACC_RAN= GE_SHIFT; if (raw_scale > BMA400_TWO_BITS_MASK) return -EINVAL; =20 - data->scale =3D BMA400_SCALE_MIN << raw_scale; + data->scale =3D BMA400_ACC_SCALE_MIN << raw_scale; =20 return 0; } @@ -719,8 +719,8 @@ static int bma400_set_accel_scale(struct bma400_data *d= ata, unsigned int val) return raw; =20 ret =3D regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, - (acc_config & ~BMA400_ACC_SCALE_MASK) | - (raw << BMA400_SCALE_SHIFT)); + (acc_config & ~BMA400_ACC_CONFIG1_ACC_RANGE_MASK) | + (raw << BMA400_ACC_RANGE_SHIFT)); if (ret) return ret; =20 @@ -786,8 +786,8 @@ static int bma400_enable_steps(struct bma400_data *data= , int val) return 0; =20 ret =3D regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG, - BMA400_STEP_INT_MSK, - FIELD_PREP(BMA400_STEP_INT_MSK, val ? 1 : 0)); + BMA400_INT_CONFIG1_STEP_INT_MASK, + FIELD_PREP(BMA400_INT_CONFIG1_STEP_INT_MASK, val ? 1 : 0)); if (ret) return ret; data->steps_enabled =3D val; @@ -826,7 +826,7 @@ static void bma400_init_tables(void) for (i =3D 0; i + 1 < ARRAY_SIZE(bma400_scales); i +=3D 2) { raw =3D i / 2; bma400_scales[i] =3D 0; - bma400_scales[i + 1] =3D BMA400_SCALE_MIN << raw; + bma400_scales[i + 1] =3D BMA400_ACC_SCALE_MIN << raw; } } =20 @@ -1063,7 +1063,7 @@ static int bma400_write_raw(struct iio_dev *indio_dev, return ret; case IIO_CHAN_INFO_SCALE: if (val !=3D 0 || - val2 < BMA400_SCALE_MIN || val2 > BMA400_SCALE_MAX) + val2 < BMA400_ACC_SCALE_MIN || val2 > BMA400_ACC_SCALE_MAX) return -EINVAL; =20 mutex_lock(&data->mutex); @@ -1114,16 +1114,16 @@ static int bma400_read_event_config(struct iio_dev = *indio_dev, case IIO_ACCEL: switch (dir) { case IIO_EV_DIR_RISING: - return FIELD_GET(BMA400_INT_GEN1_MSK, + return FIELD_GET(BMA400_INT_CONFIG0_GEN1_MASK, data->generic_event_en); case IIO_EV_DIR_FALLING: - return FIELD_GET(BMA400_INT_GEN2_MSK, + return FIELD_GET(BMA400_INT_CONFIG0_GEN2_MASK, data->generic_event_en); case IIO_EV_DIR_SINGLETAP: - return FIELD_GET(BMA400_S_TAP_MSK, + return FIELD_GET(BMA400_INT_CONFIG1_S_TAP_MASK, data->tap_event_en_bitmask); case IIO_EV_DIR_DOUBLETAP: - return FIELD_GET(BMA400_D_TAP_MSK, + return FIELD_GET(BMA400_INT_CONFIG1_D_TAP_MASK, data->tap_event_en_bitmask); default: return -EINVAL; @@ -1146,8 +1146,8 @@ static int bma400_steps_event_enable(struct bma400_da= ta *data, int state) return ret; =20 ret =3D regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG, - BMA400_STEP_INT_MSK, - FIELD_PREP(BMA400_STEP_INT_MSK, + BMA400_INT_CONFIG1_STEP_INT_MASK, + FIELD_PREP(BMA400_INT_CONFIG1_STEP_INT_MASK, state)); if (ret) return ret; @@ -1164,18 +1164,18 @@ static int bma400_activity_event_en(struct bma400_d= ata *data, =20 switch (dir) { case IIO_EV_DIR_RISING: - reg =3D BMA400_GEN1INT_CONFIG0; - msk =3D BMA400_INT_GEN1_MSK; + reg =3D BMA400_GEN1INT_CONFIG0_REG; + msk =3D BMA400_INT_CONFIG0_GEN1_MASK; value =3D 2; - set_mask_bits(&field_value, BMA400_INT_GEN1_MSK, - FIELD_PREP(BMA400_INT_GEN1_MSK, state)); + set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN1_MASK, + FIELD_PREP(BMA400_INT_CONFIG0_GEN1_MASK, state)); break; case IIO_EV_DIR_FALLING: - reg =3D BMA400_GEN2INT_CONFIG0; - msk =3D BMA400_INT_GEN2_MSK; + reg =3D BMA400_GEN2INT_CONFIG0_REG; + msk =3D BMA400_INT_CONFIG0_GEN2_MASK; value =3D 0; - set_mask_bits(&field_value, BMA400_INT_GEN2_MSK, - FIELD_PREP(BMA400_INT_GEN2_MSK, state)); + set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN2_MASK, + FIELD_PREP(BMA400_INT_CONFIG0_GEN2_MASK, state)); break; default: return -EINVAL; @@ -1240,21 +1240,21 @@ static int bma400_tap_event_en(struct bma400_data *= data, } =20 ret =3D regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG, - BMA400_S_TAP_MSK, - FIELD_PREP(BMA400_S_TAP_MSK, state)); + BMA400_INT_CONFIG1_S_TAP_MASK, + FIELD_PREP(BMA400_INT_CONFIG1_S_TAP_MASK, state)); if (ret) return ret; =20 switch (dir) { case IIO_EV_DIR_SINGLETAP: - mask =3D BMA400_S_TAP_MSK; - set_mask_bits(&field_value, BMA400_S_TAP_MSK, - FIELD_PREP(BMA400_S_TAP_MSK, state)); + mask =3D BMA400_INT_CONFIG1_S_TAP_MASK; + set_mask_bits(&field_value, BMA400_INT_CONFIG1_S_TAP_MASK, + FIELD_PREP(BMA400_INT_CONFIG1_S_TAP_MASK, state)); break; case IIO_EV_DIR_DOUBLETAP: - mask =3D BMA400_D_TAP_MSK; - set_mask_bits(&field_value, BMA400_D_TAP_MSK, - FIELD_PREP(BMA400_D_TAP_MSK, state)); + mask =3D BMA400_INT_CONFIG1_D_TAP_MASK; + set_mask_bits(&field_value, BMA400_INT_CONFIG1_D_TAP_MASK, + FIELD_PREP(BMA400_INT_CONFIG1_D_TAP_MASK, state)); break; default: return -EINVAL; @@ -1340,9 +1340,9 @@ static int get_gen_config_reg(enum iio_event_directio= n dir) { switch (dir) { case IIO_EV_DIR_FALLING: - return BMA400_GEN2INT_CONFIG0; + return BMA400_GEN2INT_CONFIG0_REG; case IIO_EV_DIR_RISING: - return BMA400_GEN1INT_CONFIG0; + return BMA400_GEN1INT_CONFIG0_REG; default: return -EINVAL; } @@ -1393,7 +1393,7 @@ static int bma400_read_event_value(struct iio_dev *in= dio_dev, ret =3D regmap_read(data->regmap, reg, val); if (ret) return ret; - *val =3D FIELD_GET(BMA400_GEN_HYST_MSK, *val); + *val =3D FIELD_GET(BMA400_GENINT_CONFIG0_HYST_MASK, *val); return IIO_VAL_INT; default: return -EINVAL; @@ -1401,30 +1401,30 @@ static int bma400_read_event_value(struct iio_dev *= indio_dev, case IIO_EV_TYPE_GESTURE: switch (info) { case IIO_EV_INFO_VALUE: - ret =3D regmap_read(data->regmap, BMA400_TAP_CONFIG, + ret =3D regmap_read(data->regmap, BMA400_TAP_CONFIG_REG, ®_val); if (ret) return ret; =20 - *val =3D FIELD_GET(BMA400_TAP_SEN_MSK, reg_val); + *val =3D FIELD_GET(BMA400_TAP_CONFIG_SEN_MASK, reg_val); return IIO_VAL_INT; case IIO_EV_INFO_RESET_TIMEOUT: - ret =3D regmap_read(data->regmap, BMA400_TAP_CONFIG1, + ret =3D regmap_read(data->regmap, BMA400_TAP_CONFIG1_REG, ®_val); if (ret) return ret; =20 - raw =3D FIELD_GET(BMA400_TAP_QUIET_MSK, reg_val); + raw =3D FIELD_GET(BMA400_TAP_CONFIG1_QUIET_MASK, reg_val); *val =3D 0; *val2 =3D tap_reset_timeout[raw]; return IIO_VAL_INT_PLUS_MICRO; case IIO_EV_INFO_TAP2_MIN_DELAY: - ret =3D regmap_read(data->regmap, BMA400_TAP_CONFIG1, + ret =3D regmap_read(data->regmap, BMA400_TAP_CONFIG1_REG, ®_val); if (ret) return ret; =20 - raw =3D FIELD_GET(BMA400_TAP_QUIETDT_MSK, reg_val); + raw =3D FIELD_GET(BMA400_TAP_CONFIG1_QUIETDT_MASK, reg_val); *val =3D 0; *val2 =3D double_tap2_min_delay[raw]; return IIO_VAL_INT_PLUS_MICRO; @@ -1480,8 +1480,8 @@ static int bma400_write_event_value(struct iio_dev *i= ndio_dev, return -EINVAL; =20 return regmap_update_bits(data->regmap, reg, - BMA400_GEN_HYST_MSK, - FIELD_PREP(BMA400_GEN_HYST_MSK, + BMA400_GENINT_CONFIG0_HYST_MASK, + FIELD_PREP(BMA400_GENINT_CONFIG0_HYST_MASK, val)); default: return -EINVAL; @@ -1493,9 +1493,9 @@ static int bma400_write_event_value(struct iio_dev *i= ndio_dev, return -EINVAL; =20 return regmap_update_bits(data->regmap, - BMA400_TAP_CONFIG, - BMA400_TAP_SEN_MSK, - FIELD_PREP(BMA400_TAP_SEN_MSK, + BMA400_TAP_CONFIG_REG, + BMA400_TAP_CONFIG_SEN_MASK, + FIELD_PREP(BMA400_TAP_CONFIG_SEN_MASK, val)); case IIO_EV_INFO_RESET_TIMEOUT: raw =3D usec_to_tapreg_raw(val2, tap_reset_timeout); @@ -1503,9 +1503,9 @@ static int bma400_write_event_value(struct iio_dev *i= ndio_dev, return -EINVAL; =20 return regmap_update_bits(data->regmap, - BMA400_TAP_CONFIG1, - BMA400_TAP_QUIET_MSK, - FIELD_PREP(BMA400_TAP_QUIET_MSK, + BMA400_TAP_CONFIG1_REG, + BMA400_TAP_CONFIG1_QUIET_MASK, + FIELD_PREP(BMA400_TAP_CONFIG1_QUIET_MASK, raw)); case IIO_EV_INFO_TAP2_MIN_DELAY: raw =3D usec_to_tapreg_raw(val2, double_tap2_min_delay); @@ -1513,9 +1513,9 @@ static int bma400_write_event_value(struct iio_dev *i= ndio_dev, return -EINVAL; =20 return regmap_update_bits(data->regmap, - BMA400_TAP_CONFIG1, - BMA400_TAP_QUIETDT_MSK, - FIELD_PREP(BMA400_TAP_QUIETDT_MSK, + BMA400_TAP_CONFIG1_REG, + BMA400_TAP_CONFIG1_QUIETDT_MASK, + FIELD_PREP(BMA400_TAP_CONFIG1_QUIETDT_MASK, raw)); default: return -EINVAL; @@ -1533,14 +1533,14 @@ static int bma400_data_rdy_trigger_set_state(struct= iio_trigger *trig, int ret; =20 ret =3D regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, - BMA400_INT_DRDY_MSK, - FIELD_PREP(BMA400_INT_DRDY_MSK, state)); + BMA400_INT_CONFIG0_DRDY_MASK, + FIELD_PREP(BMA400_INT_CONFIG0_DRDY_MASK, state)); if (ret) return ret; =20 return regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, - BMA400_INT_DRDY_MSK, - FIELD_PREP(BMA400_INT_DRDY_MSK, state)); + BMA400_INT_CONFIG0_DRDY_MASK, + FIELD_PREP(BMA400_INT_CONFIG0_DRDY_MASK, state)); } =20 static const unsigned long bma400_avail_scan_masks[] =3D { @@ -1578,7 +1578,7 @@ static irqreturn_t bma400_trigger_handler(int irq, vo= id *p) mutex_lock(&data->mutex); =20 /* bulk read six registers, with the base being the LSB register */ - ret =3D regmap_bulk_read(data->regmap, BMA400_X_AXIS_LSB_REG, + ret =3D regmap_bulk_read(data->regmap, BMA400_ACC_X_LSB_REG, &data->buffer.buff, sizeof(data->buffer.buff)); if (ret) goto unlock_err; @@ -1628,13 +1628,13 @@ static irqreturn_t bma400_interrupt(int irq, void *= private) * Disable all advance interrupts if interrupt engine overrun occurs. * See section 4.7 "Interrupt engine overrun" in datasheet v1.2. */ - if (FIELD_GET(BMA400_INT_ENG_OVRUN_MSK, le16_to_cpu(data->status))) { + if (FIELD_GET(BMA400_ENG_OVRUN_INT_STAT_MASK, le16_to_cpu(data->status)))= { bma400_disable_adv_interrupt(data); dev_err(data->dev, "Interrupt engine overrun\n"); goto unlock_err; } =20 - if (FIELD_GET(BMA400_INT_S_TAP_MSK, le16_to_cpu(data->status))) + if (FIELD_GET(BMA400_S_TAP_INT_STAT_MASK, le16_to_cpu(data->status))) iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z, @@ -1642,7 +1642,7 @@ static irqreturn_t bma400_interrupt(int irq, void *pr= ivate) IIO_EV_DIR_SINGLETAP), timestamp); =20 - if (FIELD_GET(BMA400_INT_D_TAP_MSK, le16_to_cpu(data->status))) + if (FIELD_GET(BMA400_D_TAP_INT_STAT_MASK, le16_to_cpu(data->status))) iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X_OR_Y_OR_Z, @@ -1650,10 +1650,10 @@ static irqreturn_t bma400_interrupt(int irq, void *= private) IIO_EV_DIR_DOUBLETAP), timestamp); =20 - if (FIELD_GET(BMA400_INT_GEN1_MSK, le16_to_cpu(data->status))) + if (FIELD_GET(BMA400_INT_CONFIG0_GEN1_MASK, le16_to_cpu(data->status))) ev_dir =3D IIO_EV_DIR_RISING; =20 - if (FIELD_GET(BMA400_INT_GEN2_MSK, le16_to_cpu(data->status))) + if (FIELD_GET(BMA400_INT_CONFIG0_GEN2_MASK, le16_to_cpu(data->status))) ev_dir =3D IIO_EV_DIR_FALLING; =20 if (ev_dir !=3D IIO_EV_DIR_NONE) { @@ -1664,7 +1664,7 @@ static irqreturn_t bma400_interrupt(int irq, void *pr= ivate) timestamp); } =20 - if (FIELD_GET(BMA400_STEP_STAT_MASK, le16_to_cpu(data->status))) { + if (FIELD_GET(BMA400_STEP_INT_STAT_MASK, le16_to_cpu(data->status))) { iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_STEPS, 0, IIO_NO_MOD, IIO_EV_TYPE_CHANGE, @@ -1686,7 +1686,7 @@ static irqreturn_t bma400_interrupt(int irq, void *pr= ivate) } } =20 - if (FIELD_GET(BMA400_INT_DRDY_MSK, le16_to_cpu(data->status))) { + if (FIELD_GET(BMA400_INT_CONFIG0_DRDY_MASK, le16_to_cpu(data->status))) { mutex_unlock(&data->mutex); iio_trigger_poll_nested(data->trig); return IRQ_HANDLED; --=20 2.43.0 From nobody Sun Feb 8 09:37:49 2026 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B523279DB4 for ; Thu, 2 Oct 2025 18:42:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759430525; cv=none; b=Ml6vdBEbRfE0pj0WpqxyzDIRLlAuKxxBw8AChmIPydN7ZpepeMGlUoQPzSnxgp14pdUbkRKxeBLdB+BzUs1G7m2OD296jAac/eod9B9ob0aioiHjIc4O34XSG/RUEAr1YYH2MvARyQt/cHyL2QNaZU3sWeQjthSPe6Pn65/1SrA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759430525; c=relaxed/simple; bh=a7D9hz3epqZ0bQU6txYeaeBNSIwXAUcTbzwa7CuoZaw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=A7GVRljjuVjseZaKcw9R23UtoGhvhCvk51qwt45MRsR7eEktC1wQnmMn8NHvLMbcS73SciPnPrDeuo2ArQCFoA15kQX5LA6QUKaK+w75bqaRKcQHgkM5NpPpdrHvfceXC8/KrJQdL4ymkXVju5vMm/5UhF6fakBnLo/73PaIsNo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gfP38l1B; arc=none smtp.client-ip=209.85.210.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gfP38l1B" Received: by mail-pf1-f180.google.com with SMTP id d2e1a72fcca58-7800ff158d5so1300802b3a.1 for ; Thu, 02 Oct 2025 11:42:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1759430523; x=1760035323; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rqjFYu+ePtbWEe02tU57DLUXg0AvCayHuA5DoSCV2Vg=; b=gfP38l1BkSbPzpiikZythvRXzOr+umHXU8MgUjX0LyvRl0SzOxd+iTqGvI2Bdw+6mo xSbD6fXxquuF2E2dKtkr+2aio/LG7ykBC/kGLEebV6HKrU2gn+FRaksFzjIyelpBgcvM JqfyBNu5gtA3cXy+nBi3gtCs9gBEfk1g/sQi/DubBw8HRfDGCOZJuzhGBx26IfdT0X+r kiqz9ETCCtteaTyyHBgHug3qmV9RCIkBT2xVTF5qrRZ+zd3VerXInoG2x+6ABlyZLxPL +zUAbAcerwZHkBpExn5xbtxGLAb72Tt4kA1QpY/SWmI7HqdCWLST6A03D1GCRQh6QxUz foHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759430523; x=1760035323; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rqjFYu+ePtbWEe02tU57DLUXg0AvCayHuA5DoSCV2Vg=; b=JMNC27sj4kNluXuPoDYaiH5fFjDnJII34qSiLLm7bxkQehUdlJ53wzU9NR1tJ1scGO UecNLZZyI/yYJma15lvt5+LpKuZEy2Tk8VrTesCtQuYhhoafRHUSAleqe/LqN7nFwLxf Nn/oLPflJ1q2Xo3GVaw8+Vw4v8VGh2R3M3XLcjcrK2fW02sEtCv3ZBhlNQrE8x03oyjc Q0Npq/wLImGQvezqC5rlZDxU7Cj7L3BqULpO/JRSuCjMf3z4DLJt8MEe+tTJ7qH5ZvDd Ug6BU/sFu8EHLcgEL4aNo6MeVGwa57dTUqWFD8Y5bgDidX/t7oEFAnqttB+w4ZuXpZ/J omBg== X-Forwarded-Encrypted: i=1; AJvYcCVRUENLNGFbp25/TPA4ndcbwn2Uol6UWkYqs3nvWJjHg4RLhg+Rv1XL11rqzKb0kZDIWO5fww5Zq8TJF9s=@vger.kernel.org X-Gm-Message-State: AOJu0YzjRWXhU3EyM8ET1msU9tY+sclVJ8qnGv8pmkfpRP8Xon+ThIEf 6DQDL5Ri1vX/pXRDDk69BAGmaI+shlyyJb0Xx9zGlTWAS3mf6FsjfICB X-Gm-Gg: ASbGnct5I1y2nyZAw6HdNEknBTql7tn/UCETFMemKs84JqPpKqVMqmyLR37Zw/kvNt0 cQBUTP3eOnJRLiejDVJ9UYO3t8nkXrQxMsP245DxfKQ67/FJNEH7K0GTeRX5biUOnbjcfvVMvmt jcYWKkwRxcsy1evUWCHQHFwozVOC7/ZNWbNgYA4ds6fUVf/BOwS4A1xVEnAcChFEDLdpUmD1AJv YS7QIfScaIIg3u8ZT/+zMBoG71TbB3u4CfwO4X+6w35zRrc7RS8ljtfG/7BeAuid1Ce4pq34Q7R n64xaGBk3c9SAmU1QpJZlv1T603lGaaDTKhXmRKePu6yKTCtzqCvqOXDqrHsnwviQ4iLbEVxyop BZV6BD9TH1ZL+41sLZSjLbJ+pW9X9jTxT2AZPpPmXX8ZRnt0PXpBF6kAX X-Google-Smtp-Source: AGHT+IHsG5bz1iYiNfYk+h6yX5OFWi97oMSan5DkcHZBV6+S7qJwwY+wRw4tFAkjKIQyhbpMAdXjYQ== X-Received: by 2002:a05:6a20:6a08:b0:2f9:dc8d:d2a2 with SMTP id adf61e73a8af0-32b61dee151mr513803637.2.1759430522853; Thu, 02 Oct 2025 11:42:02 -0700 (PDT) Received: from akshayaj-lenovo.. ([223.233.78.22]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b62ce55205csm162917a12.18.2025.10.02.11.41.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Oct 2025 11:42:02 -0700 (PDT) From: Akshay Jindal To: dan@dlrobertson.com, jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org Cc: Akshay Jindal , shuah@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/5] iio: accel: bma400: Use macros for generic event configuration values Date: Fri, 3 Oct 2025 00:11:03 +0530 Message-ID: <20251002184120.495193-3-akshayaj.lkd@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251002184120.495193-1-akshayaj.lkd@gmail.com> References: <20251002184120.495193-1-akshayaj.lkd@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add macros and enums for configuration values used in generic event handling for activity and inactivity detection. Replace hard-coded values in activity_event_en() with the new definitions to make the configuration explicit. No functional changes are intended. Signed-off-by: Akshay Jindal --- drivers/iio/accel/bma400.h | 30 ++++++++++++++++++++++++++++++ drivers/iio/accel/bma400_core.c | 14 +++++++++++--- 2 files changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/iio/accel/bma400.h b/drivers/iio/accel/bma400.h index ae3411c090c9..13fe2e5a3175 100644 --- a/drivers/iio/accel/bma400.h +++ b/drivers/iio/accel/bma400.h @@ -106,8 +106,38 @@ #define BMA400_GEN1INT_CONFIG0_REG 0x3f #define BMA400_GEN2INT_CONFIG0_REG 0x4A #define BMA400_GENINT_CONFIG0_HYST_MASK GENMASK(1, 0) +#define BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK GENMASK(3, 2) +#define BMA400_GENINT_CONFIG0_DATA_SRC_MASK BIT(4) +#define BMA400_GENINT_CONFIG0_X_EN_MASK BIT(5) +#define BMA400_GENINT_CONFIG0_Y_EN_MASK BIT(6) +#define BMA400_GENINT_CONFIG0_Z_EN_MASK BIT(7) + +enum bma400_accel_data_src { + ACCEL_FILT1, + ACCEL_FILT2, +}; + +enum bma400_ref_updt_mode { + BMA400_REF_MANUAL_UPDT_MODE, + BMA400_REF_ONETIME_UPDT_MODE, + BMA400_REF_EVERYTIME_UPDT_MODE, + BMA400_REF_EVERYTIME_LP_UPDT_MODE, +}; =20 #define BMA400_GEN_CONFIG1_OFF 0x01 +#define BMA400_GENINT_CONFIG1_AXES_COMB_MASK BIT(0) +#define BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK BIT(1) + +enum bma400_genintr_acceleval_axescomb { + BMA400_EVAL_X_OR_Y_OR_Z, + BMA400_EVAL_X_AND_Y_AND_Z, +}; + +enum bma400_detect_criterion { + BMA400_DETECT_INACTIVITY, + BMA400_DETECT_ACTIVITY, +}; + #define BMA400_GEN_CONFIG2_OFF 0x02 #define BMA400_GEN_CONFIG3_OFF 0x03 #define BMA400_GEN_CONFIG31_OFF 0x04 diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_cor= e.c index 35d2b90425f8..58c378ba9931 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -1166,14 +1166,16 @@ static int bma400_activity_event_en(struct bma400_d= ata *data, case IIO_EV_DIR_RISING: reg =3D BMA400_GEN1INT_CONFIG0_REG; msk =3D BMA400_INT_CONFIG0_GEN1_MASK; - value =3D 2; + value =3D FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X= _OR_Y_OR_Z) | + FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_ACTIVIT= Y); set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN1_MASK, FIELD_PREP(BMA400_INT_CONFIG0_GEN1_MASK, state)); break; case IIO_EV_DIR_FALLING: reg =3D BMA400_GEN2INT_CONFIG0_REG; msk =3D BMA400_INT_CONFIG0_GEN2_MASK; - value =3D 0; + value =3D FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X= _OR_Y_OR_Z) | + FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_INACTIV= ITY); set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN2_MASK, FIELD_PREP(BMA400_INT_CONFIG0_GEN2_MASK, state)); break; @@ -1182,7 +1184,13 @@ static int bma400_activity_event_en(struct bma400_da= ta *data, } =20 /* Enabling all axis for interrupt evaluation */ - ret =3D regmap_write(data->regmap, reg, 0xF8); + ret =3D regmap_write(data->regmap, reg, + BMA400_GENINT_CONFIG0_X_EN_MASK | + BMA400_GENINT_CONFIG0_Y_EN_MASK | + BMA400_GENINT_CONFIG0_Z_EN_MASK| + FIELD_PREP(BMA400_GENINT_CONFIG0_DATA_SRC_MASK, ACCEL_FILT2)| + FIELD_PREP(BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK, + BMA400_REF_EVERYTIME_UPDT_MODE)); if (ret) return ret; =20 --=20 2.43.0 From nobody Sun Feb 8 09:37:49 2026 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39B0427B35F for ; Thu, 2 Oct 2025 18:42:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759430533; cv=none; b=c2ntlJanmzl6DOvzTJMZG018ETNZ8qspP0mjj15gIIKgSFjB6PqS2Pdq6q45mJ6KD+/+gc1UCugPwCTCcnejaK1lBDYwIl5ZWu6Lvnh0OQi4KFRB+y4d8Jtnk6jla3PnUUnQCdoy6i2EXuGsgWRW76Z5OCcc4GXsp6ZG7OB9HHA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759430533; c=relaxed/simple; bh=CgdLoSRqcqubsg0rI377cLUrOqK7eOYKEPqDrL7PqVI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hZ2gEhumM/IyvPsj7yA8ZrVtghawaM/IhCUM9X8OMCMBVC6en6ZcYUpCoDLVdW+/SUJ0n4+D4ShhlYzvZ8YFEabSgbuMGz8xPYDxx+3OAubWbyeIOcyzKo9ZzQSzdK76FS5hXn/gSVd+iyHQol33saHWYYMnzQxZhicz/UBIoN0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=abo1N0yi; arc=none smtp.client-ip=209.85.210.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="abo1N0yi" Received: by mail-pf1-f180.google.com with SMTP id d2e1a72fcca58-77f5d497692so2004827b3a.1 for ; Thu, 02 Oct 2025 11:42:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1759430529; x=1760035329; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XDyDktYkrwmeCiCnLdbEvncGAxhs/BH7a/A0BkO50cg=; b=abo1N0yiwGc9rCzEndi3uUgf+ADodkbL9AVrYl/qUe3NYohiCKApw6m+XI4TqsLBj8 BZrfStpLvUX9sbxMQcqnoAFlDzuF7q9KWqy1bcoOHcMMIMO9PRNhm46MJuvV/rwUvuum Z7GPh+lTKcqhlx6zmylIBnf1Q6TsNNUjEpPnOpzDHhDlsmX1GByXEx6GWSOjm4/kAu6i c3Q1jYCwyyjEmR8J1NiutAk7LCeXDRsOfvQBRSmnsanuyKgz5dyd9RO0oyxoZcc0Hy5W L86Uq2qMpM8GtKiGcZ4tyj7b2854ZwNxY8bYmtpCzu+jn9MCk/6cZdoYmRD+xSa1AKLv cNgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759430529; x=1760035329; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XDyDktYkrwmeCiCnLdbEvncGAxhs/BH7a/A0BkO50cg=; b=ZiYAB+b49uRryRasdD0kRWJ3QIKLt4QKLa0gv6VQMR1HqEsuJfu7tlmeKvcF9K9+Cm 7mmPDH+0Pa7HZB1/TyF1Ii0GpKSRIo0q1VU/OLijOtF+vknnfutdgS8V1oKE065PWYMg z8Mv+eA7KQF2G091ngmME8OCDCw6vgR71Pa9wZHdyzp2OHMVsk0bBonpUhNyauk2ir3W q2yxwdn0ZVOD9N0UpF9KCRU7MphjjejB0kEAA/oDT2Z1kVu41N1vWnXATZSYJGFqgxLf GJyAiw3jjGTAPUI1HVv9Bre67d8FN/B5HLsVjSEu+HcO6J/X9pWgr8rqS/bOmPyJmoIY QpIQ== X-Forwarded-Encrypted: i=1; AJvYcCWahd7V+vw6o/WpznOMbd0a7kkFv6ozMdV4l6wuSrgKbWQenLRc0K9PBKIuNU/RvRvMaqoYwWhhdlLFCMg=@vger.kernel.org X-Gm-Message-State: AOJu0Yxonrj0B4o1t5ylWw7XwczDV+YZO44hLfj4WOZez8c5Lk+iIftA l6UJWEo/BBc0d+2sXjDgnDWpto/m5Wyf3ifXUSuXzK5S/yjeRgVZnrGE X-Gm-Gg: ASbGncsqoEUbKHboxsiFjUEkHgvvdCjXi0qSaqkpDbKKVccp1Sf7KxJU7LGyaXSEH0z iTP47yxBLCW0+ZcpuihYciWsG6KF3L4VkIxD3LaUyO6ZcuYw7OVq4+PF4gZhCS2SfY+zXBF/IAP HfzwVYtv+KFVTgp5JiAb2pbv2CONjK1MQ2x5pVfSCMPmeJrwyPoTaQNJuZO8lP/732/NQ0Mn3/V lql30nsR1KJrnMeb7/X6h5+5Bf4z4Q40uOmLAW2qWaAlZxgmFJP7stGMQwkVD/uaPnVMPSsKtw7 mYb+9GdigcmvKntRI64g9Y8Kpd8X01nAncVRKshw8Tp1sxodPcZaKYTaAOFB4bjpeLluhAIcYeK h8DgqBRCPZ8YKSzVX1BgUetq3bibT0jqfaQ8vlLZtTlwxCijYKM26lPKI/7+Zc4Oeyuk= X-Google-Smtp-Source: AGHT+IGP8WFUpp6D5O3V3PcWBOeK8FWgcAKMa1vb9ii5DoVIizWgPxfaNyi7VlxqzxFNS83t349/jA== X-Received: by 2002:a05:6a21:998e:b0:302:9f3b:3e5c with SMTP id adf61e73a8af0-32b620a8d65mr538970637.39.1759430529439; Thu, 02 Oct 2025 11:42:09 -0700 (PDT) Received: from akshayaj-lenovo.. ([223.233.78.22]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b62ce55205csm162917a12.18.2025.10.02.11.42.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Oct 2025 11:42:08 -0700 (PDT) From: Akshay Jindal To: dan@dlrobertson.com, jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org Cc: Akshay Jindal , shuah@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/5] iio: accel: bma400: Use index-based register addressing and lookup Date: Fri, 3 Oct 2025 00:11:04 +0530 Message-ID: <20251002184120.495193-4-akshayaj.lkd@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251002184120.495193-1-akshayaj.lkd@gmail.com> References: <20251002184120.495193-1-akshayaj.lkd@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce formula-based macros to compute GEN INTR configuration register addresses from the interrupt number and register index. This reduces the need for 22 explicit register macros to three base definitions. Add a centralized lookup table keyed by IIO event direction and replace get_gen_config_reg() with a helper integrated with this table. Apply these changes across the affected callbacks to ensure consistent access to generic interrupt registers. No functional changes are intended. Signed-off-by: Akshay Jindal --- drivers/iio/accel/bma400.h | 17 +++-- drivers/iio/accel/bma400_core.c | 131 +++++++++++++++++++------------- 2 files changed, 88 insertions(+), 60 deletions(-) diff --git a/drivers/iio/accel/bma400.h b/drivers/iio/accel/bma400.h index 13fe2e5a3175..48fcaeeb553d 100644 --- a/drivers/iio/accel/bma400.h +++ b/drivers/iio/accel/bma400.h @@ -91,6 +91,11 @@ #define BMA400_INT_CONFIG0_GEN2_MASK BIT(3) #define BMA400_INT_CONFIG0_DRDY_MASK BIT(7) =20 +enum bma400_generic_intr { + BMA400_GEN1_INTR =3D 1, + BMA400_GEN2_INTR, +}; + #define BMA400_INT_CONFIG1_REG 0x20 #define BMA400_INT_CONFIG1_STEP_INT_MASK BIT(0) #define BMA400_INT_CONFIG1_S_TAP_MASK BIT(2) @@ -103,8 +108,12 @@ #define BMA400_TWO_BITS_MASK GENMASK(1, 0) =20 /* Generic interrupts register */ -#define BMA400_GEN1INT_CONFIG0_REG 0x3f -#define BMA400_GEN2INT_CONFIG0_REG 0x4A +#define BMA400_GENINT_CONFIG_REG_BASE 0x3f +#define BMA400_NUM_GENINT_CONFIG_REGS 11 +#define BMA400_GENINT_CONFIG_REG(gen_intr, config_idx) \ + (BMA400_GENINT_CONFIG_REG_BASE + \ + (gen_intr - 1) * BMA400_NUM_GENINT_CONFIG_REGS + \ + (config_idx)) #define BMA400_GENINT_CONFIG0_HYST_MASK GENMASK(1, 0) #define BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK GENMASK(3, 2) #define BMA400_GENINT_CONFIG0_DATA_SRC_MASK BIT(4) @@ -138,10 +147,6 @@ enum bma400_detect_criterion { BMA400_DETECT_ACTIVITY, }; =20 -#define BMA400_GEN_CONFIG2_OFF 0x02 -#define BMA400_GEN_CONFIG3_OFF 0x03 -#define BMA400_GEN_CONFIG31_OFF 0x04 - /* TAP config registers */ #define BMA400_TAP_CONFIG_REG 0x57 #define BMA400_TAP_CONFIG_SEN_MASK GENMASK(2, 0) diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_cor= e.c index 58c378ba9931..a0e994f9882b 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -121,6 +121,41 @@ struct bma400_data { __be16 duration; }; =20 +struct bma400_genintr_info { + enum bma400_generic_intr genintr; + unsigned int intrmask; + enum iio_event_direction dir; + enum bma400_detect_criterion detect_mode; +}; + +/* Lookup struct for determining GEN1/GEN2 based on dir */ +static const struct bma400_genintr_info bma400_genintrs[] =3D { + [IIO_EV_DIR_RISING] =3D { + .genintr =3D BMA400_GEN1_INTR, + .intrmask =3D BMA400_INT_CONFIG0_GEN1_MASK, + .dir =3D IIO_EV_DIR_RISING, + .detect_mode =3D BMA400_DETECT_ACTIVITY, + }, + [IIO_EV_DIR_FALLING] =3D { + .genintr =3D BMA400_GEN2_INTR, + .intrmask =3D BMA400_INT_CONFIG0_GEN2_MASK, + .dir =3D IIO_EV_DIR_FALLING, + .detect_mode =3D BMA400_DETECT_INACTIVITY, + } +}; + +static inline const struct bma400_genintr_info * +get_bma400_genintr_info(enum iio_event_direction dir) +{ + switch (dir) { + case IIO_EV_DIR_RISING: + case IIO_EV_DIR_FALLING: + return &bma400_genintrs[dir]; + default: + return NULL; + }; +} + static bool bma400_is_writable_reg(struct device *dev, unsigned int reg) { switch (reg) { @@ -1159,32 +1194,22 @@ static int bma400_activity_event_en(struct bma400_d= ata *data, enum iio_event_direction dir, int state) { - int ret, reg, msk, value; - int field_value =3D 0; + int ret; + unsigned int intrmask, regval; + enum bma400_generic_intr genintr; + enum bma400_detect_criterion detect_criterion; + const struct bma400_genintr_info *bma400_genintr; =20 - switch (dir) { - case IIO_EV_DIR_RISING: - reg =3D BMA400_GEN1INT_CONFIG0_REG; - msk =3D BMA400_INT_CONFIG0_GEN1_MASK; - value =3D FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X= _OR_Y_OR_Z) | - FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_ACTIVIT= Y); - set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN1_MASK, - FIELD_PREP(BMA400_INT_CONFIG0_GEN1_MASK, state)); - break; - case IIO_EV_DIR_FALLING: - reg =3D BMA400_GEN2INT_CONFIG0_REG; - msk =3D BMA400_INT_CONFIG0_GEN2_MASK; - value =3D FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X= _OR_Y_OR_Z) | - FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_INACTIV= ITY); - set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN2_MASK, - FIELD_PREP(BMA400_INT_CONFIG0_GEN2_MASK, state)); - break; - default: + bma400_genintr =3D get_bma400_genintr_info(dir); + if (!bma400_genintr) return -EINVAL; - } + + genintr =3D bma400_genintr->genintr; + detect_criterion =3D bma400_genintr->detect_mode; + intrmask =3D bma400_genintr->intrmask; =20 /* Enabling all axis for interrupt evaluation */ - ret =3D regmap_write(data->regmap, reg, + ret =3D regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 0), BMA400_GENINT_CONFIG0_X_EN_MASK | BMA400_GENINT_CONFIG0_Y_EN_MASK | BMA400_GENINT_CONFIG0_Z_EN_MASK| @@ -1195,31 +1220,32 @@ static int bma400_activity_event_en(struct bma400_d= ata *data, return ret; =20 /* OR combination of all axis for interrupt evaluation */ - ret =3D regmap_write(data->regmap, reg + BMA400_GEN_CONFIG1_OFF, value); + regval =3D FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X= _OR_Y_OR_Z) | + FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, detect_criterion); + ret =3D regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 1), = regval); if (ret) return ret; =20 /* Initial value to avoid interrupts while enabling*/ - ret =3D regmap_write(data->regmap, reg + BMA400_GEN_CONFIG2_OFF, 0x0A); + ret =3D regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 2), = 0x0A); if (ret) return ret; =20 /* Initial duration value to avoid interrupts while enabling*/ - ret =3D regmap_write(data->regmap, reg + BMA400_GEN_CONFIG31_OFF, 0x0F); + ret =3D regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 4), = 0x0F); if (ret) return ret; =20 - ret =3D regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, msk, - field_value); + regval =3D state ? intrmask : 0; + ret =3D regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, intrmask, r= egval); if (ret) return ret; =20 - ret =3D regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, msk, - field_value); + ret =3D regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, intrmask= , regval); if (ret) return ret; =20 - set_mask_bits(&data->generic_event_en, msk, field_value); + set_mask_bits(&data->generic_event_en, intrmask, regval); return 0; } =20 @@ -1344,18 +1370,6 @@ static int bma400_write_event_config(struct iio_dev = *indio_dev, } } =20 -static int get_gen_config_reg(enum iio_event_direction dir) -{ - switch (dir) { - case IIO_EV_DIR_FALLING: - return BMA400_GEN2INT_CONFIG0_REG; - case IIO_EV_DIR_RISING: - return BMA400_GEN1INT_CONFIG0_REG; - default: - return -EINVAL; - } -} - static int bma400_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, enum iio_event_type type, @@ -1364,22 +1378,25 @@ static int bma400_read_event_value(struct iio_dev *= indio_dev, int *val, int *val2) { struct bma400_data *data =3D iio_priv(indio_dev); - int ret, reg, reg_val, raw; + int ret, reg_val, raw; + enum bma400_generic_intr genintr; + const struct bma400_genintr_info *bma400_genintr; =20 if (chan->type !=3D IIO_ACCEL) return -EINVAL; =20 switch (type) { case IIO_EV_TYPE_MAG: - reg =3D get_gen_config_reg(dir); - if (reg < 0) + bma400_genintr =3D get_bma400_genintr_info(dir); + if (!bma400_genintr) return -EINVAL; + genintr =3D bma400_genintr->genintr; =20 *val2 =3D 0; switch (info) { case IIO_EV_INFO_VALUE: ret =3D regmap_read(data->regmap, - reg + BMA400_GEN_CONFIG2_OFF, + BMA400_GENINT_CONFIG_REG(genintr, 2), val); if (ret) return ret; @@ -1387,7 +1404,7 @@ static int bma400_read_event_value(struct iio_dev *in= dio_dev, case IIO_EV_INFO_PERIOD: mutex_lock(&data->mutex); ret =3D regmap_bulk_read(data->regmap, - reg + BMA400_GEN_CONFIG3_OFF, + BMA400_GENINT_CONFIG_REG(genintr, 3), &data->duration, sizeof(data->duration)); if (ret) { @@ -1398,7 +1415,9 @@ static int bma400_read_event_value(struct iio_dev *in= dio_dev, mutex_unlock(&data->mutex); return IIO_VAL_INT; case IIO_EV_INFO_HYSTERESIS: - ret =3D regmap_read(data->regmap, reg, val); + ret =3D regmap_read(data->regmap, + BMA400_GENINT_CONFIG_REG(genintr, 0), + val); if (ret) return ret; *val =3D FIELD_GET(BMA400_GENINT_CONFIG0_HYST_MASK, *val); @@ -1452,16 +1471,19 @@ static int bma400_write_event_value(struct iio_dev = *indio_dev, int val, int val2) { struct bma400_data *data =3D iio_priv(indio_dev); - int reg, ret, raw; + int ret, raw; + enum bma400_generic_intr genintr; + const struct bma400_genintr_info *bma400_genintr; =20 if (chan->type !=3D IIO_ACCEL) return -EINVAL; =20 switch (type) { case IIO_EV_TYPE_MAG: - reg =3D get_gen_config_reg(dir); - if (reg < 0) + bma400_genintr =3D get_bma400_genintr_info(dir); + if (!bma400_genintr) return -EINVAL; + genintr =3D bma400_genintr->genintr; =20 switch (info) { case IIO_EV_INFO_VALUE: @@ -1469,7 +1491,7 @@ static int bma400_write_event_value(struct iio_dev *i= ndio_dev, return -EINVAL; =20 return regmap_write(data->regmap, - reg + BMA400_GEN_CONFIG2_OFF, + BMA400_GENINT_CONFIG_REG(genintr, 2), val); case IIO_EV_INFO_PERIOD: if (val < 1 || val > 65535) @@ -1478,7 +1500,7 @@ static int bma400_write_event_value(struct iio_dev *i= ndio_dev, mutex_lock(&data->mutex); put_unaligned_be16(val, &data->duration); ret =3D regmap_bulk_write(data->regmap, - reg + BMA400_GEN_CONFIG3_OFF, + BMA400_GENINT_CONFIG_REG(genintr, 3), &data->duration, sizeof(data->duration)); mutex_unlock(&data->mutex); @@ -1487,7 +1509,8 @@ static int bma400_write_event_value(struct iio_dev *i= ndio_dev, if (val < 0 || val > 3) return -EINVAL; =20 - return regmap_update_bits(data->regmap, reg, + return regmap_update_bits(data->regmap, + BMA400_GENINT_CONFIG_REG(genintr, 0), BMA400_GENINT_CONFIG0_HYST_MASK, FIELD_PREP(BMA400_GENINT_CONFIG0_HYST_MASK, val)); --=20 2.43.0 From nobody Sun Feb 8 09:37:49 2026 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2038A27B33E for ; Thu, 2 Oct 2025 18:42:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759430537; cv=none; b=Ny3U+DSKjw2/XmJwj3yRl0A5VMLuoGznVp3/HaaOVUwsvEdSlXq536ez8+4gpxNHyC21mBs9Vqa1VK+lJJ4SIFiAhQpE5sqSvYoyM3G43Tyx+1KY41q0B6Y1htdvbbSfUalzTX1HU5YDSFlk9ZPqpqamR8aqc5teZ4zwWwhA2h0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759430537; c=relaxed/simple; bh=wujo6oR6KRs+dKd5VCfSi/HrfuVzG23TWqKEr0OV7js=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UPAMjZ6yQvYgeZ5kPNzLiXjkqRpQu2At42k7Fg2P/FsFvAfuaGS06dNqBwJZGOPyDq82/ahg95REdMuTOhLsoK7cK40udI+fdRaY2XZma9sOTZ1Gg/UhE+FaQ+ewXGqJHOpT1TANRuQ6V25o+ASfTjtAfFNbEYLeWHTojeHFTvA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KO62vc4I; arc=none smtp.client-ip=209.85.210.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KO62vc4I" Received: by mail-pf1-f177.google.com with SMTP id d2e1a72fcca58-78125ed4052so1637385b3a.0 for ; Thu, 02 Oct 2025 11:42:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1759430535; x=1760035335; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sUZYODvSV6S3UG56hxwOik5nzkLbs7prF1klJbRcNxE=; b=KO62vc4IrA5cqetuPs23pSSYMP/d6bFJVYX5tuZjUpeyyaYmyxpDm2b/4w0ZnhEBIZ kqAkSTpqhU5cWj/MsHd7Wky9RPkPxyiF7IDMQFrMUjXzFlv0PaN2imQqSnXDGgL9acFf CwPiignzd+Wx1Eb9UMuOZGfe9eVWcsFnIMKUTKA9J1BEjUCIudaQdIcVGahuO6dOSeD6 u+Xkr/GHnxJNNTUTWrD7S6lj/5hWCUG2ghwy8EM2UzIUHbJUHjH0IwrfZET4KtRJx7IV Si8m8jk7sxt2EQGrYKe8zQ3kxrJvL/yrbxAKVW7q6O5ZW9RkUq478oHkTuy0K610DHQp Lsow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759430535; x=1760035335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sUZYODvSV6S3UG56hxwOik5nzkLbs7prF1klJbRcNxE=; b=RP0aA+hKQ45/F0uK3gVPDbUIbGzlCpWQDTXyFJ8w0CxW/9T59jKvIhDHDw45q5xG4K nI+8QwPdtsvL/SI7HODqYI4FMlyJnY+Ffa+bUaoOTUMDUI9PWE4zie4CxugkhWEAvo4/ gu6Zb0MsEuGsQlqsDuxjZfnDGd9e2u3HcZoMCBfnnDe9M6ZBr3kdAGbQmlUj/jnWNVVd Lbz/gPFm5WhyzQnGTNZbCkebunbF4Jw3eVdIKlb+QNswTookHu66bTm6Wk0M7tR/e8Td RThWFguBpiDDSbSVT9V1pMObw0miQm9ax7X2PGE4M/dopvJOAf6yWYcZoeeDWFaGW0DK dppA== X-Forwarded-Encrypted: i=1; AJvYcCWdKHyaYkE+4ArWQMX0Ei3NG/2F7+PhyV3+UY9lKTM8Xfe4Qgn6/e/dsXHh1+r0bi6AD0/Zgdrdo4MOGb4=@vger.kernel.org X-Gm-Message-State: AOJu0YyKs+/Msz3OjoJeH5ROVSaUgJtcNx0WGwu7mzdvJ8HLpJLKbDfF 8Bqf+++57WRcx3DUX9abVrTzbl2SRQ8v6/OiNh1C4HBpeaQSlMXi3k5h X-Gm-Gg: ASbGnct5qdoBVP9NVyzGCqyNUCMgPPqO3h1D8HF1piUKsVXFTAc3drDEYNOAlsrVC6Q oALFsEbsfdVhhEW/sLodDg0TxCkJqFb2dbJ0d0yoofMIqOL7H9QZfFmYfAN8/lb+0aIUwt82SAc 4PRVcWU0y3+WVovtZvWN6KamOjbWkZXqgO2tN9q3J/GoOp1MiZYH51lmYqLnRYisk3T5+5oBYIG +Hz7mfFGljz1BXl0AamIN0zTMdinZOykHFeVLYYsTqahM5H4VauyNSPbC+L8mhIe36IrVYVdE3d XQWFeIMU3WX2YWF5DpgTTUEYvC4PoQDrr+wamScv4O4yhY1AZxKKmV9OENrwf+M/h8GZ8Ec6lEw phVvlC8jqslZKN4EJQyA+giFTkp5gpvzQl1WdNqwU6OB5rH/rbG66iZCh56S8TESpN60= X-Google-Smtp-Source: AGHT+IEP2vjy7P17pql5sZfYw/KjKSGAfQViyYu0lFY3uTuOnWp8xnin7dh+GmQxvjNLW8IZDmVSbA== X-Received: by 2002:a05:6a20:72a3:b0:2be:81e3:1124 with SMTP id adf61e73a8af0-32b61dfb9b6mr569531637.2.1759430535216; Thu, 02 Oct 2025 11:42:15 -0700 (PDT) Received: from akshayaj-lenovo.. ([223.233.78.22]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b62ce55205csm162917a12.18.2025.10.02.11.42.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Oct 2025 11:42:14 -0700 (PDT) From: Akshay Jindal To: dan@dlrobertson.com, jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org Cc: Akshay Jindal , shuah@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/5] iio: accel: bma400: Rename activity_event_en() to generic_event_en() Date: Fri, 3 Oct 2025 00:11:05 +0530 Message-ID: <20251002184120.495193-5-akshayaj.lkd@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251002184120.495193-1-akshayaj.lkd@gmail.com> References: <20251002184120.495193-1-akshayaj.lkd@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The function activity_event_en() configures the generic interrupts GEN1 and GEN2, which are used for activity and inactivity detection as per the datasheet. The existing name is misleading, since the device also provides activity change and activity recognition interrupts. Activity change interrupt is not supported yet whereas Activity recognition interrupt is configured in a different function. Rename activity_event_en() to generic_event_en() to better reflect its actual purpose. No functional changes intended. Signed-off-by: Akshay Jindal --- drivers/iio/accel/bma400_core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_cor= e.c index a0e994f9882b..41e95291b36b 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -1190,9 +1190,9 @@ static int bma400_steps_event_enable(struct bma400_da= ta *data, int state) return 0; } =20 -static int bma400_activity_event_en(struct bma400_data *data, - enum iio_event_direction dir, - int state) +static int bma400_generic_event_en(struct bma400_data *data, + enum iio_event_direction dir, + int state) { int ret; unsigned int intrmask, regval; @@ -1337,7 +1337,7 @@ static int bma400_write_event_config(struct iio_dev *= indio_dev, switch (type) { case IIO_EV_TYPE_MAG: mutex_lock(&data->mutex); - ret =3D bma400_activity_event_en(data, dir, state); + ret =3D bma400_generic_event_en(data, dir, state); mutex_unlock(&data->mutex); return ret; case IIO_EV_TYPE_GESTURE: --=20 2.43.0 From nobody Sun Feb 8 09:37:49 2026 Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 870EB27A924 for ; Thu, 2 Oct 2025 18:42:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759430542; cv=none; b=MGhPdQok6JxAKzIxObv70BuwXDPRdkoomRsnwC5IlOO23P6RmfZMKh3uU3eU2YYVuSW/zqfXkPCA5qgkShWqo/CA2P74b5GGbb5wkHiLizUfyYcFL4cbzv3UZd7gWSFgncmJjyTVAaKXFBWZnB3PQuE+5/FV+Vnl0F7HlHN7vm4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759430542; c=relaxed/simple; bh=HhCHFa0EFtA8AuRvrj8xtXesClEos9CJZT5NVSJ5C8o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C4YIYoKILseaswDO7oFsNt7qAOOTZo37jHBCrVHcEQdDUn4sqpCOlCtPREhkG6/1A19h3q6307u4pBX1C/EEwCgTRFrAw/nfp6gizEmS7ftvk5tQ78/qbqcdrHkmwxTKiShmVk0Ob5cti49Vb/n+mevKgQa9BEdTaHH3yt+tyvA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=P+thbIqr; arc=none smtp.client-ip=209.85.210.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="P+thbIqr" Received: by mail-pf1-f175.google.com with SMTP id d2e1a72fcca58-789fb76b466so1380475b3a.0 for ; Thu, 02 Oct 2025 11:42:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1759430541; x=1760035341; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7qPjlv1lJ8MR6fVmoY/AaU1ujSOHO/r4FwpJCh/Gigc=; b=P+thbIqr9MS/sGnKeKRgJJgjqpy75emZGNeRU97cH/xtMH55/m9veurh/SfDTjnlEp mUD25J6wBpPw1hc4AA/fqD9SO8s9i/uEq5bB+2zJrNgO40DPdT6zRgpax0SP9fyTKEND q/qiuh/5BsuvsXuLkLhYen3tODNKaQapsCu6RSSTq2PQRGYAC4UaQ/Sv2cTOT2XJQGt9 ifGks+HxLUHy2oJetbyPpTsBtyQY1N3011am5vO+3MdwJkyew/JjgqemEwqR3d6B8tCD jf+F0Ck+IrYEklYTlUCSTot+HqvELTu6TpyYVc3ZMAx6PKd+en/UUk2RcPwkkc2VZvyB o6cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1759430541; x=1760035341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7qPjlv1lJ8MR6fVmoY/AaU1ujSOHO/r4FwpJCh/Gigc=; b=OTlh0GJAFwQcRt9DGmvyMEKOrqMvnSPjzqLMAhZlVkDXwSLPc61VZ/ofORQpHbai+T JSLFvfWR1Q10wHYvuYqacEbtP8g0iKas+BMHYOcSk8Ed2t5tpngAv+15O/hAfeyS0PkT PL19lacG01rGlUoUAUjevnQp3jjhW4baA4uK+KLo3qHhSrJY7RPp2rgxA82Aoo127ogM khxP4qjZ9ZpbhmlRo3JxEynt+e0M9O/Ogcq+cXuU5dfbUpqW3LRei7I2LuD1yc4UlBWS gqI+mCT5ievm4GbdsGhxSIV6x9n7jn0frkUsnTOBELgXMNqzeMByVNDPgwtnbYgGu/xW zLpg== X-Forwarded-Encrypted: i=1; AJvYcCXhnKpudZL+7BdFI8UlbuA/CoSAmxk4KaRqA0iPpQxQj3J5+8uEXMfglKVUf7FuAY3dkuOzFpef119/kYk=@vger.kernel.org X-Gm-Message-State: AOJu0Yx9GFTVJliOk6+EfsmyWlyR1V93rDc5bTfPNC1ztuJamC6LwGl9 AyDw5ff76ISjyiUxcM5nc+qsCWWHfmV53F5gnfF9H4/tLteMuI2vS/aw4cR9tA== X-Gm-Gg: ASbGncuEwP4EJKOZgf2BAMvUA+pvePU8DUwh6V6jNxy8aAn8dlbzjeoxbfwXZN71JTz wv6M4WtuyHhTp/hW7ptYlKDMdUfwBiVdXTk8nG83y9nWUQU7GAFT9sGBZVlhpo42CO2bFvjIoJN Z9EdaUu6mCn8MGKANoDwO8sC2NDYqlgfsewmLKUk9T2XmEYAow37Yi03+UIrd77CEy1sKu8r2eg tiSEHBu2OOvLOBMV6bEAOB/yWfzdwl3Zia2UsJDVSBIZsO5NdEtZAjd/He1yRLjbAfos1bSL7vT hOjynOJTtnLegS/z3aIhOk3JfMIZV1jU7IOSeJ1r01apW7gGRIrVOUuslmpjKlemdM7KK4IvdeD 9LbXMjU0+0SF6ygLfte9sHrPt3WbK3cOSIiE40qprqZoP2rQGkr2lQXWl X-Google-Smtp-Source: AGHT+IE158JkUSIaEaS3oXYZ4vFl7nu8N6VKeXlcYX2Ca7DdlwgbiaYwME8zie6eNvnBRdAOll7WXQ== X-Received: by 2002:a05:6a21:3396:b0:2f6:9592:9065 with SMTP id adf61e73a8af0-32b6209567cmr471844637.30.1759430540647; Thu, 02 Oct 2025 11:42:20 -0700 (PDT) Received: from akshayaj-lenovo.. ([223.233.78.22]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b62ce55205csm162917a12.18.2025.10.02.11.42.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Oct 2025 11:42:20 -0700 (PDT) From: Akshay Jindal To: dan@dlrobertson.com, jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org Cc: Akshay Jindal , shuah@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/5] iio: accel: bma400: Add detail to comments in GEN INTR configuration Date: Fri, 3 Oct 2025 00:11:06 +0530 Message-ID: <20251002184120.495193-6-akshayaj.lkd@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251002184120.495193-1-akshayaj.lkd@gmail.com> References: <20251002184120.495193-1-akshayaj.lkd@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Append additional information to existing comments in the generic interrupt configuration code to provide more context. Signed-off-by: Akshay Jindal --- drivers/iio/accel/bma400_core.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_cor= e.c index 41e95291b36b..c42cdf0a1645 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -1208,7 +1208,10 @@ static int bma400_generic_event_en(struct bma400_dat= a *data, detect_criterion =3D bma400_genintr->detect_mode; intrmask =3D bma400_genintr->intrmask; =20 - /* Enabling all axis for interrupt evaluation */ + /* + * Enabling all axis for interrupt evaluation + * Acc_filt2 is recommended as data source in datasheet (Section 4.7) + */ ret =3D regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 0), BMA400_GENINT_CONFIG0_X_EN_MASK | BMA400_GENINT_CONFIG0_Y_EN_MASK | @@ -1226,7 +1229,10 @@ static int bma400_generic_event_en(struct bma400_dat= a *data, if (ret) return ret; =20 - /* Initial value to avoid interrupts while enabling*/ + /* + * Initial value to avoid interrupts while enabling + * Value is in units of 8mg/lsb, i.e. effective val is val * 8mg/lsb + */ ret =3D regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 2), = 0x0A); if (ret) return ret; --=20 2.43.0